Commit 75a511b1 authored by Konrad Dybcio's avatar Konrad Dybcio Committed by Bjorn Andersson

arm64: dts: qcom: sm6350: Add GPUCC node

Add and configure a node for the GPU clock controller.
Signed-off-by: default avatarKonrad Dybcio <konrad.dybcio@somainline.org>
Reviewed-by: default avatarLuca Weiss <luca.weiss@fairphone.com>
Signed-off-by: default avatarKonrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20230315-topic-lagoon_gpu-v2-3-afcdfb18bb13@linaro.orgSigned-off-by: default avatarBjorn Andersson <andersson@kernel.org>
parent 3091e582
......@@ -5,6 +5,7 @@
*/
#include <dt-bindings/clock/qcom,gcc-sm6350.h>
#include <dt-bindings/clock/qcom,gpucc-sm6350.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/clock/qcom,sm6350-camcc.h>
#include <dt-bindings/dma/qcom-gpi.h>
......@@ -1308,6 +1309,20 @@ compute-cb@5 {
};
};
gpucc: clock-controller@3d90000 {
compatible = "qcom,sm6350-gpucc";
reg = <0 0x03d90000 0 0x9000>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&gcc GCC_GPU_GPLL0_CLK>,
<&gcc GCC_GPU_GPLL0_DIV_CLK>;
clock-names = "bi_tcxo",
"gcc_gpu_gpll0_clk_src",
"gcc_gpu_gpll0_div_clk_src";
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
};
mpss: remoteproc@4080000 {
compatible = "qcom,sm6350-mpss-pas";
reg = <0x0 0x04080000 0x0 0x4040>;
......
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