drm/amd/display: DP compliance automation test fixes

Fixes:
1. Removing pending flag since we are executing teh entire flow without context switches
2. Adding stream enablment - connection between DIG BE to DIG FE during test link training
Signed-off-by: Leon Elazar <leon.elazar@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c

@@ -1738,8 +1738,7 @@ static void handle_automated_test(struct core_link *link)
 	}
 	if (test_request.bits.LINK_TEST_PATTRN) {
 		dp_test_send_link_test_pattern(link);
-		link->public.compliance_test_state.bits.
-			SET_TEST_PATTERN_PENDING = 1;
+		test_response.bits.ACK = 1;
 	}
 	if (test_request.bits.PHY_TEST_PATTERN) {
 		dp_test_send_phy_test_pattern(link);
@@ -2308,11 +2307,9 @@ bool dc_link_dp_set_test_pattern(
 	unsigned int i;
 	unsigned char link_qual_pattern[LANE_COUNT_DP_MAX] = {0};
 	union dpcd_training_pattern training_pattern;
-	union test_response test_response;
 	enum dpcd_phy_test_patterns pattern;
 
 	memset(&training_pattern, 0, sizeof(training_pattern));
-	memset(&test_response, 0, sizeof(test_response));
 
 	for (i = 0; i < MAX_PIPES; i++) {
 		if (pipes[i].stream->sink->link == core_link) {
@@ -2442,20 +2439,6 @@ bool dc_link_dp_set_test_pattern(
 		set_crtc_test_pattern(core_link, &pipe_ctx, test_pattern);
 		/* Set Test Pattern state */
 		core_link->public.test_pattern_enabled = true;
-
-		/* If this is called because of compliance test request,
-		 * we respond ack here.
-		 */
-		if (core_link->public.compliance_test_state.bits.
-				SET_TEST_PATTERN_PENDING == 1) {
-			core_link->public.compliance_test_state.bits.
-						SET_TEST_PATTERN_PENDING = 0;
-			test_response.bits.ACK = 1;
-			core_link_write_dpcd(core_link,
-					DP_TEST_RESPONSE,
-					&test_response.raw,
-					sizeof(test_response));
-		}
 	}
 
 	return true;

drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c

@@ -251,6 +251,8 @@ void dp_retrain_link_dp_test(struct core_link *link,
 
 			dp_receiver_power_ctrl(link, false);
 
+			link->dc->hwss.disable_stream(&pipes[i]);
+
 			link->link_enc->funcs->disable_output(
 					link->link_enc,
 					SIGNAL_TYPE_DISPLAY_PORT);
@@ -273,6 +275,8 @@ void dp_retrain_link_dp_test(struct core_link *link,
 
 			link->public.cur_link_settings = *link_setting;
 
+			link->dc->hwss.enable_stream(&pipes[i]);
+
 			link->dc->hwss.unblank_stream(&pipes[i],
 					link_setting);
 		}

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

@@ -432,8 +432,7 @@ union phy_test_pattern {
 union compliance_test_state {
 	struct {
 		unsigned char STEREO_3D_RUNNING        : 1;
-		unsigned char SET_TEST_PATTERN_PENDING : 1;
-		unsigned char RESERVED                 : 6;
+		unsigned char RESERVED                 : 7;
 	} bits;
 	unsigned char raw;
 };