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Commit 75f5653a authored by David S. Miller's avatar David S. Miller
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Merge branch 'mvpp2-next' 

Stefan Chulski says:

====================
net: mvpp2: Minor non functional driver code improvements

The patch series contains minor code improvements and did not change any functionality.
====================
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents 7f6334f7 935a1184
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Showing with 28 additions and 32 deletions
drivers/net/ethernet/marvell/mvpp2/mvpp2.h
View file @ 75f5653a
......@@ -673,9 +673,9 @@
#define GENCONF_PORT_CTRL1_EN(p) BIT(p)
#define GENCONF_PORT_CTRL1_RESET(p) (BIT(p) << 28)
#define GENCONF_CTRL0 0x1120
#define GENCONF_CTRL0_PORT0_RGMII BIT(0)
#define GENCONF_CTRL0_PORT1_RGMII_MII BIT(1)
#define GENCONF_CTRL0_PORT1_RGMII BIT(2)
#define GENCONF_CTRL0_PORT2_RGMII BIT(0)
#define GENCONF_CTRL0_PORT3_RGMII_MII BIT(1)
#define GENCONF_CTRL0_PORT3_RGMII BIT(2)
/* Various constants */
......
drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
View file @ 75f5653a
......@@ -329,7 +329,7 @@ static int mvpp2_get_nrxqs(struct mvpp2 *priv)
{
unsigned int nrxqs;
if (priv->hw_version != MVPP21 && queue_mode == MVPP2_QDIST_SINGLE_MODE)
if (priv->hw_version >= MVPP22 && queue_mode == MVPP2_QDIST_SINGLE_MODE)
return 1;
/* According to the PPv2.2 datasheet and our experiments on
......@@ -469,7 +469,7 @@ static void mvpp2_bm_bufs_get_addrs(struct device *dev, struct mvpp2 *priv,
MVPP2_BM_PHY_ALLOC_REG(bm_pool->id));
*phys_addr = mvpp2_thread_read(priv, thread, MVPP2_BM_VIRT_ALLOC_REG);
if (priv->hw_version != MVPP21) {
if (priv->hw_version >= MVPP22) {
u32 val;
u32 dma_addr_highbits, phys_addr_highbits;
......@@ -963,7 +963,7 @@ static inline void mvpp2_bm_pool_put(struct mvpp2_port *port, int pool,
if (test_bit(thread, &port->priv->lock_map))
spin_lock_irqsave(&port->bm_lock[thread], flags);
if (port->priv->hw_version != MVPP21) {
if (port->priv->hw_version >= MVPP22) {
u32 val = 0;
if (sizeof(dma_addr_t) == 8)
......@@ -1462,7 +1462,7 @@ static bool mvpp2_port_supports_xlg(struct mvpp2_port *port)
static bool mvpp2_port_supports_rgmii(struct mvpp2_port *port)
{
return !(port->priv->hw_version != MVPP21 && port->gop_id == 0);
return !(port->priv->hw_version >= MVPP22 && port->gop_id == 0);
}
/* Port configuration routines */
......@@ -1494,9 +1494,9 @@ static void mvpp22_gop_init_rgmii(struct mvpp2_port *port)
regmap_read(priv->sysctrl_base, GENCONF_CTRL0, &val);
if (port->gop_id == 2)
val |= GENCONF_CTRL0_PORT0_RGMII;
val |= GENCONF_CTRL0_PORT2_RGMII;
else if (port->gop_id == 3)
val |= GENCONF_CTRL0_PORT1_RGMII_MII;
val |= GENCONF_CTRL0_PORT3_RGMII_MII;
regmap_write(priv->sysctrl_base, GENCONF_CTRL0, val);
}
......@@ -1513,9 +1513,9 @@ static void mvpp22_gop_init_sgmii(struct mvpp2_port *port)
if (port->gop_id > 1) {
regmap_read(priv->sysctrl_base, GENCONF_CTRL0, &val);
if (port->gop_id == 2)
val &= ~GENCONF_CTRL0_PORT0_RGMII;
val &= ~GENCONF_CTRL0_PORT2_RGMII;
else if (port->gop_id == 3)
val &= ~GENCONF_CTRL0_PORT1_RGMII_MII;
val &= ~GENCONF_CTRL0_PORT3_RGMII_MII;
regmap_write(priv->sysctrl_base, GENCONF_CTRL0, val);
}
}
......@@ -2125,7 +2125,7 @@ static void mvpp2_mac_reset_assert(struct mvpp2_port *port)
MVPP2_GMAC_PORT_RESET_MASK;
writel(val, port->base + MVPP2_GMAC_CTRL_2_REG);
if (port->priv->hw_version != MVPP21 && port->gop_id == 0) {
if (port->priv->hw_version >= MVPP22 && port->gop_id == 0) {
val = readl(port->base + MVPP22_XLG_CTRL0_REG) &
~MVPP22_XLG_CTRL0_MAC_RESET_DIS;
writel(val, port->base + MVPP22_XLG_CTRL0_REG);
......@@ -4016,7 +4016,7 @@ static void mvpp2_txdesc_clear_ptp(struct mvpp2_port *port,
struct mvpp2_tx_desc *desc)
{
/* We only need to clear the low bits */
if (port->priv->hw_version != MVPP21)
if (port->priv->hw_version >= MVPP22)
desc->pp22.ptp_descriptor &=
cpu_to_le32(~MVPP22_PTP_DESC_MASK_LOW);
}
......@@ -4528,7 +4528,7 @@ static void mvpp2_start_dev(struct mvpp2_port *port)
/* Enable interrupts on all threads */
mvpp2_interrupts_enable(port);
if (port->priv->hw_version != MVPP21)
if (port->priv->hw_version >= MVPP22)
mvpp22_mode_reconfigure(port);
if (port->phylink) {
......@@ -4746,7 +4746,7 @@ static int mvpp2_open(struct net_device *dev)
valid = true;
}
if (priv->hw_version != MVPP21 && port->port_irq) {
if (priv->hw_version >= MVPP22 && port->port_irq) {
err = request_irq(port->port_irq, mvpp2_port_isr, 0,
dev->name, port);
if (err) {
......@@ -6399,7 +6399,7 @@ static int mvpp2__mac_prepare(struct phylink_config *config, unsigned int mode,
MVPP2_GMAC_PORT_RESET_MASK,
MVPP2_GMAC_PORT_RESET_MASK);
if (port->priv->hw_version != MVPP21) {
if (port->priv->hw_version >= MVPP22) {
mvpp22_gop_mask_irq(port);
phy_power_off(port->comphy);
......@@ -6453,7 +6453,7 @@ static int mvpp2_mac_finish(struct phylink_config *config, unsigned int mode,
{
struct mvpp2_port *port = mvpp2_phylink_to_port(config);
if (port->priv->hw_version != MVPP21 &&
if (port->priv->hw_version >= MVPP22 &&
port->phy_interface != interface) {
port->phy_interface = interface;
......@@ -7200,7 +7200,7 @@ static int mvpp2_init(struct platform_device *pdev, struct mvpp2 *priv)
if (dram_target_info)
mvpp2_conf_mbus_windows(dram_target_info, priv);
if (priv->hw_version != MVPP21)
if (priv->hw_version >= MVPP22)
mvpp2_axi_init(priv);
/* Disable HW PHY polling */
......@@ -7277,10 +7277,8 @@ static int mvpp2_get_sram(struct platform_device *pdev,
}
priv->cm3_base = devm_ioremap_resource(&pdev->dev, res);
if (IS_ERR(priv->cm3_base))
return PTR_ERR(priv->cm3_base);
return 0;
return PTR_ERR_OR_ZERO(priv->cm3_base);
}
static int mvpp2_probe(struct platform_device *pdev)
......@@ -7350,7 +7348,7 @@ static int mvpp2_probe(struct platform_device *pdev)
priv->global_tx_fc = true;
}
if (priv->hw_version != MVPP21 && dev_of_node(&pdev->dev)) {
if (priv->hw_version >= MVPP22 && dev_of_node(&pdev->dev)) {
priv->sysctrl_base =
syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
"marvell,system-controller");
......@@ -7363,7 +7361,7 @@ static int mvpp2_probe(struct platform_device *pdev)
priv->sysctrl_base = NULL;
}
if (priv->hw_version != MVPP21 &&
if (priv->hw_version >= MVPP22 &&
mvpp2_get_nrxqs(priv) * 2 <= MVPP2_BM_MAX_POOLS)
priv->percpu_pools = 1;
......@@ -7408,7 +7406,7 @@ static int mvpp2_probe(struct platform_device *pdev)
if (err < 0)
goto err_pp_clk;
if (priv->hw_version != MVPP21) {
if (priv->hw_version >= MVPP22) {
priv->mg_clk = devm_clk_get(&pdev->dev, "mg_clk");
if (IS_ERR(priv->mg_clk)) {
err = PTR_ERR(priv->mg_clk);
......@@ -7449,7 +7447,7 @@ static int mvpp2_probe(struct platform_device *pdev)
return -EINVAL;
}
if (priv->hw_version != MVPP21) {
if (priv->hw_version >= MVPP22) {
err = dma_set_mask(&pdev->dev, MVPP2_DESC_DMA_MASK);
if (err)
goto err_axi_clk;
......@@ -7469,10 +7467,8 @@ static int mvpp2_probe(struct platform_device *pdev)
priv->port_map |= BIT(i);
}
if (priv->hw_version != MVPP21) {
if (mvpp2_read(priv, MVPP2_VER_ID_REG) == MVPP2_VER_PP23)
priv->hw_version = MVPP23;
}
if (mvpp2_read(priv, MVPP2_VER_ID_REG) == MVPP2_VER_PP23)
priv->hw_version = MVPP23;
/* Init mss lock */
spin_lock_init(&priv->mss_spinlock);
......@@ -7516,7 +7512,7 @@ static int mvpp2_probe(struct platform_device *pdev)
goto err_port_probe;
}
if (priv->global_tx_fc && priv->hw_version != MVPP21) {
if (priv->global_tx_fc && priv->hw_version >= MVPP22) {
err = mvpp2_enable_global_fc(priv);
if (err)
dev_warn(&pdev->dev, "Minimum of CM3 firmware 18.09 and chip revision B0 required for flow control\n");
......@@ -7538,10 +7534,10 @@ static int mvpp2_probe(struct platform_device *pdev)
clk_disable_unprepare(priv->axi_clk);
err_mg_core_clk:
if (priv->hw_version != MVPP21)
if (priv->hw_version >= MVPP22)
clk_disable_unprepare(priv->mg_core_clk);
err_mg_clk:
if (priv->hw_version != MVPP21)
if (priv->hw_version >= MVPP22)
clk_disable_unprepare(priv->mg_clk);
err_gop_clk:
clk_disable_unprepare(priv->gop_clk);
......
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