Skip to content

L
linux
Commit 7603a0c7 authored by Arınç ÜNAL's avatar Arınç ÜNAL Committed by David S. Miller
Browse files
Options

net: dsa: mt7530: rename mt753x_bpdu_port_fw enum to mt753x_to_cpu_fw 

The mt753x_bpdu_port_fw enum is globally used for manipulating the process
of deciding the forwardable ports, specifically concerning the CPU port(s).
Therefore, rename it and the values in it to mt753x_to_cpu_fw.

Change FOLLOW_MFC to SYSTEM_DEFAULT to be on par with the switch documents.
Signed-off-by: default avatarArınç ÜNAL <arinc.unal@arinc9.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent eeaf9acb
Hide whitespace changes
Inline Side-by-side
Showing with 56 additions and 64 deletions
drivers/net/dsa/mt7530.c
View file @ 7603a0c7
...@@ -1107,42 +1107,34 @@ mt753x_trap_frames(struct mt7530_priv *priv) ...@@ -1107,42 +1107,34 @@ mt753x_trap_frames(struct mt7530_priv *priv)
* VLAN-untagged. * VLAN-untagged.
*/ */
mt7530_rmw(priv, MT753X_BPC, mt7530_rmw(priv, MT753X_BPC,
MT753X_PAE_BPDU_FR | MT753X_PAE_EG_TAG_MASK | PAE_BPDU_FR | PAE_EG_TAG_MASK | PAE_PORT_FW_MASK |
MT753X_PAE_PORT_FW_MASK | MT753X_BPDU_EG_TAG_MASK | BPDU_EG_TAG_MASK | BPDU_PORT_FW_MASK,
MT753X_BPDU_PORT_FW_MASK, PAE_BPDU_FR | PAE_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |
MT753X_PAE_BPDU_FR | PAE_PORT_FW(TO_CPU_FW_CPU_ONLY) |
MT753X_PAE_EG_TAG(MT7530_VLAN_EG_UNTAGGED) | BPDU_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |
MT753X_PAE_PORT_FW(MT753X_BPDU_CPU_ONLY) | TO_CPU_FW_CPU_ONLY);
MT753X_BPDU_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |
MT753X_BPDU_CPU_ONLY);
/* Trap frames with :01 and :02 MAC DAs to the CPU port(s) and egress /* Trap frames with :01 and :02 MAC DAs to the CPU port(s) and egress
* them VLAN-untagged. * them VLAN-untagged.
*/ */
mt7530_rmw(priv, MT753X_RGAC1, mt7530_rmw(priv, MT753X_RGAC1,
MT753X_R02_BPDU_FR | MT753X_R02_EG_TAG_MASK | R02_BPDU_FR | R02_EG_TAG_MASK | R02_PORT_FW_MASK |
MT753X_R02_PORT_FW_MASK | MT753X_R01_BPDU_FR | R01_BPDU_FR | R01_EG_TAG_MASK | R01_PORT_FW_MASK,
MT753X_R01_EG_TAG_MASK | MT753X_R01_PORT_FW_MASK, R02_BPDU_FR | R02_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |
MT753X_R02_BPDU_FR | R02_PORT_FW(TO_CPU_FW_CPU_ONLY) | R01_BPDU_FR |
MT753X_R02_EG_TAG(MT7530_VLAN_EG_UNTAGGED) | R01_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |
MT753X_R02_PORT_FW(MT753X_BPDU_CPU_ONLY) | TO_CPU_FW_CPU_ONLY);
MT753X_R01_BPDU_FR |
MT753X_R01_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |
MT753X_BPDU_CPU_ONLY);
/* Trap frames with :03 and :0E MAC DAs to the CPU port(s) and egress /* Trap frames with :03 and :0E MAC DAs to the CPU port(s) and egress
* them VLAN-untagged. * them VLAN-untagged.
*/ */
mt7530_rmw(priv, MT753X_RGAC2, mt7530_rmw(priv, MT753X_RGAC2,
MT753X_R0E_BPDU_FR | MT753X_R0E_EG_TAG_MASK | R0E_BPDU_FR | R0E_EG_TAG_MASK | R0E_PORT_FW_MASK |
MT753X_R0E_PORT_FW_MASK | MT753X_R03_BPDU_FR | R03_BPDU_FR | R03_EG_TAG_MASK | R03_PORT_FW_MASK,
MT753X_R03_EG_TAG_MASK | MT753X_R03_PORT_FW_MASK, R0E_BPDU_FR | R0E_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |
MT753X_R0E_BPDU_FR | R0E_PORT_FW(TO_CPU_FW_CPU_ONLY) | R03_BPDU_FR |
MT753X_R0E_EG_TAG(MT7530_VLAN_EG_UNTAGGED) | R03_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |
MT753X_R0E_PORT_FW(MT753X_BPDU_CPU_ONLY) | TO_CPU_FW_CPU_ONLY);
MT753X_R03_BPDU_FR |
MT753X_R03_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |
MT753X_BPDU_CPU_ONLY);
} }
static void static void
......
drivers/net/dsa/mt7530.h
View file @ 7603a0c7
...@@ -67,47 +67,47 @@ enum mt753x_id { ...@@ -67,47 +67,47 @@ enum mt753x_id {
#define MT753X_MIRROR_MASK(id) ((((id) == ID_MT7531) || ((id) == ID_MT7988)) ? \ #define MT753X_MIRROR_MASK(id) ((((id) == ID_MT7531) || ((id) == ID_MT7988)) ? \
MT7531_MIRROR_MASK : MIRROR_MASK) MT7531_MIRROR_MASK : MIRROR_MASK)
/* Registers for BPDU and PAE frame control*/ /* Register for BPDU and PAE frame control */
#define MT753X_BPC 0x24 #define MT753X_BPC 0x24
#define MT753X_PAE_BPDU_FR BIT(25) #define PAE_BPDU_FR BIT(25)
#define MT753X_PAE_EG_TAG_MASK GENMASK(24, 22) #define PAE_EG_TAG_MASK GENMASK(24, 22)
#define MT753X_PAE_EG_TAG(x) FIELD_PREP(MT753X_PAE_EG_TAG_MASK, x) #define PAE_EG_TAG(x) FIELD_PREP(PAE_EG_TAG_MASK, x)
#define MT753X_PAE_PORT_FW_MASK GENMASK(18, 16) #define PAE_PORT_FW_MASK GENMASK(18, 16)
#define MT753X_PAE_PORT_FW(x) FIELD_PREP(MT753X_PAE_PORT_FW_MASK, x) #define PAE_PORT_FW(x) FIELD_PREP(PAE_PORT_FW_MASK, x)
#define MT753X_BPDU_EG_TAG_MASK GENMASK(8, 6) #define BPDU_EG_TAG_MASK GENMASK(8, 6)
#define MT753X_BPDU_EG_TAG(x) FIELD_PREP(MT753X_BPDU_EG_TAG_MASK, x) #define BPDU_EG_TAG(x) FIELD_PREP(BPDU_EG_TAG_MASK, x)
#define MT753X_BPDU_PORT_FW_MASK GENMASK(2, 0) #define BPDU_PORT_FW_MASK GENMASK(2, 0)
/* Register for :01 and :02 MAC DA frame control */ /* Register for 01-80-C2-00-00-[01,02] MAC DA frame control */
#define MT753X_RGAC1 0x28 #define MT753X_RGAC1 0x28
#define MT753X_R02_BPDU_FR BIT(25) #define R02_BPDU_FR BIT(25)
#define MT753X_R02_EG_TAG_MASK GENMASK(24, 22) #define R02_EG_TAG_MASK GENMASK(24, 22)
#define MT753X_R02_EG_TAG(x) FIELD_PREP(MT753X_R02_EG_TAG_MASK, x) #define R02_EG_TAG(x) FIELD_PREP(R02_EG_TAG_MASK, x)
#define MT753X_R02_PORT_FW_MASK GENMASK(18, 16) #define R02_PORT_FW_MASK GENMASK(18, 16)
#define MT753X_R02_PORT_FW(x) FIELD_PREP(MT753X_R02_PORT_FW_MASK, x) #define R02_PORT_FW(x) FIELD_PREP(R02_PORT_FW_MASK, x)
#define MT753X_R01_BPDU_FR BIT(9) #define R01_BPDU_FR BIT(9)
#define MT753X_R01_EG_TAG_MASK GENMASK(8, 6) #define R01_EG_TAG_MASK GENMASK(8, 6)
#define MT753X_R01_EG_TAG(x) FIELD_PREP(MT753X_R01_EG_TAG_MASK, x) #define R01_EG_TAG(x) FIELD_PREP(R01_EG_TAG_MASK, x)
#define MT753X_R01_PORT_FW_MASK GENMASK(2, 0) #define R01_PORT_FW_MASK GENMASK(2, 0)
/* Register for :03 and :0E MAC DA frame control */ /* Register for 01-80-C2-00-00-[03,0E] MAC DA frame control */
#define MT753X_RGAC2 0x2c #define MT753X_RGAC2 0x2c
#define MT753X_R0E_BPDU_FR BIT(25) #define R0E_BPDU_FR BIT(25)
#define MT753X_R0E_EG_TAG_MASK GENMASK(24, 22) #define R0E_EG_TAG_MASK GENMASK(24, 22)
#define MT753X_R0E_EG_TAG(x) FIELD_PREP(MT753X_R0E_EG_TAG_MASK, x) #define R0E_EG_TAG(x) FIELD_PREP(R0E_EG_TAG_MASK, x)
#define MT753X_R0E_PORT_FW_MASK GENMASK(18, 16) #define R0E_PORT_FW_MASK GENMASK(18, 16)
#define MT753X_R0E_PORT_FW(x) FIELD_PREP(MT753X_R0E_PORT_FW_MASK, x) #define R0E_PORT_FW(x) FIELD_PREP(R0E_PORT_FW_MASK, x)
#define MT753X_R03_BPDU_FR BIT(9) #define R03_BPDU_FR BIT(9)
#define MT753X_R03_EG_TAG_MASK GENMASK(8, 6) #define R03_EG_TAG_MASK GENMASK(8, 6)
#define MT753X_R03_EG_TAG(x) FIELD_PREP(MT753X_R03_EG_TAG_MASK, x) #define R03_EG_TAG(x) FIELD_PREP(R03_EG_TAG_MASK, x)
#define MT753X_R03_PORT_FW_MASK GENMASK(2, 0) #define R03_PORT_FW_MASK GENMASK(2, 0)
enum mt753x_bpdu_port_fw { enum mt753x_to_cpu_fw {
MT753X_BPDU_FOLLOW_MFC, TO_CPU_FW_SYSTEM_DEFAULT,
MT753X_BPDU_CPU_EXCLUDE = 4, TO_CPU_FW_CPU_EXCLUDE = 4,
MT753X_BPDU_CPU_INCLUDE = 5, TO_CPU_FW_CPU_INCLUDE = 5,
MT753X_BPDU_CPU_ONLY = 6, TO_CPU_FW_CPU_ONLY = 6,
MT753X_BPDU_DROP = 7, TO_CPU_FW_DROP = 7,
}; };
/* Registers for address table access */ /* Registers for address table access */
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment
GitLab Nexedi Edition | About GitLab | About Nexedi | 沪ICP备2021021310号-2 | 沪ICP备2021021310号-7