usb: dwc3: of-simple: reset host controller at suspend/resume
If we power off the SoC logic rail in S3, we can find that the Type-C PHY can't initialize correctly after system resume. We need to toggle the USB3-OTG reset before trying to initialize the PHY, or else it times out. phy phy-ff800000.phy.9: phy poweron failed --> -110 dwc3 fe900000.dwc3: failed to initialize core dwc3: probe of fe900000.dwc3 failed with error -110 Note that the RK3399 TRM suggests that we should keep the whole usb3 controller in reset for the duration of the Type-C PHY initialization. However, it's hard to assert the reset in the current framework of reset. We're still skeptical about that, and we haven't yet found a case where this seems to have mattered. This approach is much easier, it simply holds the USB3-OTG reset while device is supended. The dwc3 core is going to reinitialize the controller at suspend/resume anyway (including a "soft reset"), so it should be safe to do this. Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
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