Commit 76599a8d authored by Ping-Ke Shih's avatar Ping-Ke Shih Committed by Kalle Valo

rtw89: 8852c: rfk: add DACK

DACK (digital-to-analog converters calibration) is used to calibrate DAC
to output analog signals as expected.
Signed-off-by: default avatarPing-Ke Shih <pkshih@realtek.com>
Signed-off-by: default avatarKalle Valo <kvalo@kernel.org>
Link: https://lore.kernel.org/r/20220502235408.15052-3-pkshih@realtek.com
parent ec424639
...@@ -3484,9 +3484,12 @@ ...@@ -3484,9 +3484,12 @@
#define R_S0_HW_SI_DIS 0x1200 #define R_S0_HW_SI_DIS 0x1200
#define B_S0_HW_SI_DIS_W_R_TRIG GENMASK(30, 28) #define B_S0_HW_SI_DIS_W_R_TRIG GENMASK(30, 28)
#define R_P0_RXCK 0x12A0 #define R_P0_RXCK 0x12A0
#define B_P0_RXCK_VAL GENMASK(18, 16)
#define B_P0_RXCK_ON BIT(19)
#define B_P0_RXCK_BW3 BIT(30) #define B_P0_RXCK_BW3 BIT(30)
#define B_P0_TXCK_ALL GENMASK(19, 12)
#define B_P0_RXCK_ON BIT(19)
#define B_P0_RXCK_VAL GENMASK(18, 16)
#define B_P0_TXCK_ON BIT(15)
#define B_P0_TXCK_VAL GENMASK(14, 12)
#define R_P0_NRBW 0x12B8 #define R_P0_NRBW 0x12B8
#define B_P0_NRBW_DBG BIT(30) #define B_P0_NRBW_DBG BIT(30)
#define R_S0_RXDC 0x12D4 #define R_S0_RXDC 0x12D4
...@@ -4035,19 +4038,98 @@ ...@@ -4035,19 +4038,98 @@
#define R_IQKINF2 0x9FE8 #define R_IQKINF2 0x9FE8
#define B_IQKINF2_FCNT GENMASK(23, 16) #define B_IQKINF2_FCNT GENMASK(23, 16)
#define B_IQKINF2_KCNT GENMASK(15, 8) #define B_IQKINF2_KCNT GENMASK(15, 8)
#define B_IQKINF2_NCTLV GENMAKS(7, 0) #define B_IQKINF2_NCTLV GENMASK(7, 0)
#define R_DCOF0 0xC000
#define B_DCOF0_V GENMASK(4, 1)
#define R_DCOF1 0xC004
#define B_DCOF1_S BIT(0)
#define R_DCOF8 0xC020
#define B_DCOF8_V GENMASK(4, 1)
#define R_DACK_S0P0 0xC040
#define B_DACK_S0P0_OK BIT(31)
#define R_DACK_BIAS00 0xc048
#define B_DACK_BIAS00 GENMASK(11, 2)
#define R_DACK_S0P2 0xC05C
#define B_DACK_S0M0 GENMASK(31, 24)
#define B_DACK_S0P2_OK BIT(2)
#define R_DACK_DADCK00 0xC060
#define B_DACK_DADCK00 GENMASK(31, 24)
#define R_DACK_S0P1 0xC064
#define B_DACK_S0P1_OK BIT(31)
#define R_DACK_BIAS01 0xC06C
#define B_DACK_BIAS01 GENMASK(11, 2)
#define R_DACK_S0P3 0xC080
#define B_DACK_S0M1 GENMASK(31, 24)
#define B_DACK_S0P3_OK BIT(2)
#define R_DACK_DADCK01 0xC084
#define B_DACK_DADCK01 GENMASK(31, 24)
#define R_DRCK 0xC0C4
#define B_DRCK_IDLE BIT(9)
#define B_DRCK_EN BIT(6)
#define B_DRCK_VAL GENMASK(4, 0)
#define R_DRCK_RES 0xC0C8
#define B_DRCK_RES GENMASK(19, 15)
#define B_DRCK_POL BIT(3)
#define R_PATH0_SAMPL_DLY_T_V1 0xC0D4 #define R_PATH0_SAMPL_DLY_T_V1 0xC0D4
#define B_PATH0_SAMPL_DLY_T_MSK_V1 GENMASK(27, 26) #define B_PATH0_SAMPL_DLY_T_MSK_V1 GENMASK(27, 26)
#define R_P0_CFCH_BW0 0xC0D4
#define B_P0_CFCH_BW0 GENMASK(27, 26)
#define R_P0_CFCH_BW1 0xC0D8
#define B_P0_CFCH_BW1 GENMASK(8, 5)
#define R_ADDCK0 0xC0F4
#define B_ADDCK0 GENMASK(9, 8)
#define B_ADDCK0_EN BIT(4)
#define B_ADDCK0_RST BIT(2)
#define R_ADDCK0_RL 0xC0F8
#define B_ADDCK0_RLS GENMASK(29, 28)
#define B_ADDCK0_RL1 GENMASK(27, 18)
#define B_ADDCK0_RL0 GENMASK(17, 8)
#define R_ADDCKR0 0xC0FC
#define B_ADDCKR0_A0 GENMASK(19, 10)
#define B_ADDCKR0_A1 GENMASK(9, 0)
#define R_DACK10 0xC100
#define B_DACK10 GENMASK(4, 1)
#define R_DACK1_K 0xc104
#define B_DACK1_EN BIT(0)
#define R_DACK11 0xC120
#define B_DACK11 GENMASK(4, 1)
#define R_DACK_S1P0 0xC140
#define B_DACK_S1P0_OK BIT(31)
#define R_DACK_BIAS10 0xC148
#define B_DACK_BIAS10 GENMASK(11, 2)
#define R_DACK10S 0xC15C
#define B_DACK10S GENMASK(31, 24)
#define R_DACK_S1P2 0xC15C
#define B_DACK_S1P2_OK BIT(2)
#define R_DACK_DADCK10 0xC160
#define B_DACK_DADCK10 GENMASK(31, 24)
#define R_DACK_S1P1 0xC164
#define B_DACK_S1P1_OK BIT(31)
#define R_DACK_BIAS11 0xC16C
#define B_DACK_BIAS11 GENMASK(11, 2)
#define R_DACK11S 0xC180
#define B_DACK11S GENMASK(31, 24)
#define R_DACK_S1P3 0xC180
#define B_DACK_S1P3_OK BIT(2)
#define R_DACK_DADCK11 0xC184
#define B_DACK_DADCK11 GENMASK(31, 24)
#define R_PATH1_SAMPL_DLY_T_V1 0xC1D4 #define R_PATH1_SAMPL_DLY_T_V1 0xC1D4
#define B_PATH1_SAMPL_DLY_T_MSK_V1 GENMASK(27, 26) #define B_PATH1_SAMPL_DLY_T_MSK_V1 GENMASK(27, 26)
#define R_PATH0_BW_SEL_V1 0xC0D8 #define R_PATH0_BW_SEL_V1 0xC0D8
#define B_PATH0_BW_SEL_MSK_V1 GENMASK(8, 5) #define B_PATH0_BW_SEL_MSK_V1 GENMASK(8, 5)
#define R_PATH1_BW_SEL_V1 0xC1D8 #define R_PATH1_BW_SEL_V1 0xC1D8
#define B_PATH1_BW_SEL_MSK_V1 GENMASK(8, 5) #define B_PATH1_BW_SEL_MSK_V1 GENMASK(8, 5)
#define R_P0_CFCH_BW0 0xC0D4 #define R_ADDCK1 0xC1F4
#define B_P0_CFCH_BW0 GENMASK(27, 26) #define B_ADDCK1 GENMASK(9, 8)
#define R_P0_CFCH_BW1 0xC0D8 #define B_ADDCK1_EN BIT(4)
#define B_P0_CFCH_BW1 GENMASK(8, 5) #define B_ADDCK1_RST BIT(2)
#define R_ADDCK1_RL 0xC1F8
#define B_ADDCK1_RLS GENMASK(29, 28)
#define B_ADDCK1_RL1 GENMASK(27, 18)
#define B_ADDCK1_RL0 GENMASK(17, 8)
#define R_ADDCKR1 0xC1fC
#define B_ADDCKR1_A0 GENMASK(19, 10)
#define B_ADDCKR1_A1 GENMASK(9, 0)
/* WiFi CPU local domain */ /* WiFi CPU local domain */
#define R_AX_WDT_CTRL 0x0040 #define R_AX_WDT_CTRL 0x0040
......
...@@ -1771,6 +1771,8 @@ static void rtw8852c_rfk_init(struct rtw89_dev *rtwdev) ...@@ -1771,6 +1771,8 @@ static void rtw8852c_rfk_init(struct rtw89_dev *rtwdev)
struct rtw89_mcc_info *mcc_info = &rtwdev->mcc; struct rtw89_mcc_info *mcc_info = &rtwdev->mcc;
memset(mcc_info, 0, sizeof(*mcc_info)); memset(mcc_info, 0, sizeof(*mcc_info));
rtw8852c_dack(rtwdev);
} }
static void rtw8852c_rfk_channel(struct rtw89_dev *rtwdev) static void rtw8852c_rfk_channel(struct rtw89_dev *rtwdev)
......
...@@ -7,6 +7,7 @@ ...@@ -7,6 +7,7 @@
#include "core.h" #include "core.h"
void rtw8852c_dack(struct rtw89_dev *rtwdev);
void rtw8852c_set_channel_rf(struct rtw89_dev *rtwdev, void rtw8852c_set_channel_rf(struct rtw89_dev *rtwdev,
struct rtw89_channel_params *param, struct rtw89_channel_params *param,
enum rtw89_phy_idx phy_idx); enum rtw89_phy_idx phy_idx);
......
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