Commit 768fc661 authored by Linus Torvalds's avatar Linus Torvalds

Merge tag 'riscv/for-v5.5-rc5' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux

Pull RISC-V fixes from Paul Walmsley:
 "Several fixes for RISC-V:

   - Fix function graph trace support

   - Prefix the CSR IRQ_* macro names with "RV_", to avoid collisions
     with macros elsewhere in the Linux kernel tree named "IRQ_TIMER"

   - Use __pa_symbol() when computing the physical address of a kernel
     symbol, rather than __pa()

   - Mark the RISC-V port as supporting GCOV

  One DT addition:

   - Describe the L2 cache controller in the FU540 DT file

  One documentation update:

   - Add patch acceptance guideline documentation"

* tag 'riscv/for-v5.5-rc5' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux:
  Documentation: riscv: add patch acceptance guidelines
  riscv: prefix IRQ_ macro names with an RV_ namespace
  clocksource: riscv: add notrace to riscv_sched_clock
  riscv: ftrace: correct the condition logic in function graph tracer
  riscv: dts: Add DT support for SiFive L2 cache controller
  riscv: gcov: enable gcov for RISC-V
  riscv: mm: use __pa_symbol for kernel symbols
parents 36487907 0e194d9d
...@@ -23,7 +23,7 @@ ...@@ -23,7 +23,7 @@
| openrisc: | TODO | | openrisc: | TODO |
| parisc: | TODO | | parisc: | TODO |
| powerpc: | ok | | powerpc: | ok |
| riscv: | TODO | | riscv: | ok |
| s390: | ok | | s390: | ok |
| sh: | ok | | sh: | ok |
| sparc: | TODO | | sparc: | TODO |
......
...@@ -60,6 +60,7 @@ lack of a better place. ...@@ -60,6 +60,7 @@ lack of a better place.
volatile-considered-harmful volatile-considered-harmful
botching-up-ioctls botching-up-ioctls
clang-format clang-format
../riscv/patch-acceptance
.. only:: subproject and html .. only:: subproject and html
......
...@@ -7,6 +7,7 @@ RISC-V architecture ...@@ -7,6 +7,7 @@ RISC-V architecture
boot-image-header boot-image-header
pmu pmu
patch-acceptance
.. only:: subproject and html .. only:: subproject and html
......
.. SPDX-License-Identifier: GPL-2.0
arch/riscv maintenance guidelines for developers
================================================
Overview
--------
The RISC-V instruction set architecture is developed in the open:
in-progress drafts are available for all to review and to experiment
with implementations. New module or extension drafts can change
during the development process - sometimes in ways that are
incompatible with previous drafts. This flexibility can present a
challenge for RISC-V Linux maintenance. Linux maintainers disapprove
of churn, and the Linux development process prefers well-reviewed and
tested code over experimental code. We wish to extend these same
principles to the RISC-V-related code that will be accepted for
inclusion in the kernel.
Submit Checklist Addendum
-------------------------
We'll only accept patches for new modules or extensions if the
specifications for those modules or extensions are listed as being
"Frozen" or "Ratified" by the RISC-V Foundation. (Developers may, of
course, maintain their own Linux kernel trees that contain code for
any draft extensions that they wish.)
Additionally, the RISC-V specification allows implementors to create
their own custom extensions. These custom extensions aren't required
to go through any review or ratification process by the RISC-V
Foundation. To avoid the maintenance complexity and potential
performance impact of adding kernel code for implementor-specific
RISC-V extensions, we'll only to accept patches for extensions that
have been officially frozen or ratified by the RISC-V Foundation.
(Implementors, may, of course, maintain their own Linux kernel trees
containing code for any custom extensions that they wish.)
...@@ -14121,6 +14121,7 @@ M: Paul Walmsley <paul.walmsley@sifive.com> ...@@ -14121,6 +14121,7 @@ M: Paul Walmsley <paul.walmsley@sifive.com>
M: Palmer Dabbelt <palmer@dabbelt.com> M: Palmer Dabbelt <palmer@dabbelt.com>
M: Albert Ou <aou@eecs.berkeley.edu> M: Albert Ou <aou@eecs.berkeley.edu>
L: linux-riscv@lists.infradead.org L: linux-riscv@lists.infradead.org
P: Documentation/riscv/patch-acceptance.rst
T: git git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux.git T: git git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux.git
S: Supported S: Supported
F: arch/riscv/ F: arch/riscv/
......
...@@ -64,6 +64,7 @@ config RISCV ...@@ -64,6 +64,7 @@ config RISCV
select SPARSEMEM_STATIC if 32BIT select SPARSEMEM_STATIC if 32BIT
select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT if MMU select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT if MMU
select HAVE_ARCH_MMAP_RND_BITS if MMU select HAVE_ARCH_MMAP_RND_BITS if MMU
select ARCH_HAS_GCOV_PROFILE_ALL
config ARCH_MMAP_RND_BITS_MIN config ARCH_MMAP_RND_BITS_MIN
default 18 if 64BIT default 18 if 64BIT
......
...@@ -54,6 +54,7 @@ cpu1: cpu@1 { ...@@ -54,6 +54,7 @@ cpu1: cpu@1 {
reg = <1>; reg = <1>;
riscv,isa = "rv64imafdc"; riscv,isa = "rv64imafdc";
tlb-split; tlb-split;
next-level-cache = <&l2cache>;
cpu1_intc: interrupt-controller { cpu1_intc: interrupt-controller {
#interrupt-cells = <1>; #interrupt-cells = <1>;
compatible = "riscv,cpu-intc"; compatible = "riscv,cpu-intc";
...@@ -77,6 +78,7 @@ cpu2: cpu@2 { ...@@ -77,6 +78,7 @@ cpu2: cpu@2 {
reg = <2>; reg = <2>;
riscv,isa = "rv64imafdc"; riscv,isa = "rv64imafdc";
tlb-split; tlb-split;
next-level-cache = <&l2cache>;
cpu2_intc: interrupt-controller { cpu2_intc: interrupt-controller {
#interrupt-cells = <1>; #interrupt-cells = <1>;
compatible = "riscv,cpu-intc"; compatible = "riscv,cpu-intc";
...@@ -100,6 +102,7 @@ cpu3: cpu@3 { ...@@ -100,6 +102,7 @@ cpu3: cpu@3 {
reg = <3>; reg = <3>;
riscv,isa = "rv64imafdc"; riscv,isa = "rv64imafdc";
tlb-split; tlb-split;
next-level-cache = <&l2cache>;
cpu3_intc: interrupt-controller { cpu3_intc: interrupt-controller {
#interrupt-cells = <1>; #interrupt-cells = <1>;
compatible = "riscv,cpu-intc"; compatible = "riscv,cpu-intc";
...@@ -123,6 +126,7 @@ cpu4: cpu@4 { ...@@ -123,6 +126,7 @@ cpu4: cpu@4 {
reg = <4>; reg = <4>;
riscv,isa = "rv64imafdc"; riscv,isa = "rv64imafdc";
tlb-split; tlb-split;
next-level-cache = <&l2cache>;
cpu4_intc: interrupt-controller { cpu4_intc: interrupt-controller {
#interrupt-cells = <1>; #interrupt-cells = <1>;
compatible = "riscv,cpu-intc"; compatible = "riscv,cpu-intc";
...@@ -253,6 +257,17 @@ pwm1: pwm@10021000 { ...@@ -253,6 +257,17 @@ pwm1: pwm@10021000 {
#pwm-cells = <3>; #pwm-cells = <3>;
status = "disabled"; status = "disabled";
}; };
l2cache: cache-controller@2010000 {
compatible = "sifive,fu540-c000-ccache", "cache";
cache-block-size = <64>;
cache-level = <2>;
cache-sets = <1024>;
cache-size = <2097152>;
cache-unified;
interrupt-parent = <&plic0>;
interrupts = <1 2 3>;
reg = <0x0 0x2010000 0x0 0x1000>;
};
}; };
}; };
...@@ -116,9 +116,9 @@ ...@@ -116,9 +116,9 @@
# define SR_PIE SR_MPIE # define SR_PIE SR_MPIE
# define SR_PP SR_MPP # define SR_PP SR_MPP
# define IRQ_SOFT IRQ_M_SOFT # define RV_IRQ_SOFT IRQ_M_SOFT
# define IRQ_TIMER IRQ_M_TIMER # define RV_IRQ_TIMER IRQ_M_TIMER
# define IRQ_EXT IRQ_M_EXT # define RV_IRQ_EXT IRQ_M_EXT
#else /* CONFIG_RISCV_M_MODE */ #else /* CONFIG_RISCV_M_MODE */
# define CSR_STATUS CSR_SSTATUS # define CSR_STATUS CSR_SSTATUS
# define CSR_IE CSR_SIE # define CSR_IE CSR_SIE
...@@ -133,15 +133,15 @@ ...@@ -133,15 +133,15 @@
# define SR_PIE SR_SPIE # define SR_PIE SR_SPIE
# define SR_PP SR_SPP # define SR_PP SR_SPP
# define IRQ_SOFT IRQ_S_SOFT # define RV_IRQ_SOFT IRQ_S_SOFT
# define IRQ_TIMER IRQ_S_TIMER # define RV_IRQ_TIMER IRQ_S_TIMER
# define IRQ_EXT IRQ_S_EXT # define RV_IRQ_EXT IRQ_S_EXT
#endif /* CONFIG_RISCV_M_MODE */ #endif /* CONFIG_RISCV_M_MODE */
/* IE/IP (Supervisor/Machine Interrupt Enable/Pending) flags */ /* IE/IP (Supervisor/Machine Interrupt Enable/Pending) flags */
#define IE_SIE (_AC(0x1, UL) << IRQ_SOFT) #define IE_SIE (_AC(0x1, UL) << RV_IRQ_SOFT)
#define IE_TIE (_AC(0x1, UL) << IRQ_TIMER) #define IE_TIE (_AC(0x1, UL) << RV_IRQ_TIMER)
#define IE_EIE (_AC(0x1, UL) << IRQ_EXT) #define IE_EIE (_AC(0x1, UL) << RV_IRQ_EXT)
#ifndef __ASSEMBLY__ #ifndef __ASSEMBLY__
......
...@@ -142,7 +142,7 @@ void prepare_ftrace_return(unsigned long *parent, unsigned long self_addr, ...@@ -142,7 +142,7 @@ void prepare_ftrace_return(unsigned long *parent, unsigned long self_addr,
*/ */
old = *parent; old = *parent;
if (function_graph_enter(old, self_addr, frame_pointer, parent)) if (!function_graph_enter(old, self_addr, frame_pointer, parent))
*parent = return_hooker; *parent = return_hooker;
} }
......
...@@ -23,11 +23,11 @@ asmlinkage __visible void __irq_entry do_IRQ(struct pt_regs *regs) ...@@ -23,11 +23,11 @@ asmlinkage __visible void __irq_entry do_IRQ(struct pt_regs *regs)
irq_enter(); irq_enter();
switch (regs->cause & ~CAUSE_IRQ_FLAG) { switch (regs->cause & ~CAUSE_IRQ_FLAG) {
case IRQ_TIMER: case RV_IRQ_TIMER:
riscv_timer_interrupt(); riscv_timer_interrupt();
break; break;
#ifdef CONFIG_SMP #ifdef CONFIG_SMP
case IRQ_SOFT: case RV_IRQ_SOFT:
/* /*
* We only use software interrupts to pass IPIs, so if a non-SMP * We only use software interrupts to pass IPIs, so if a non-SMP
* system gets one, then we don't know what to do. * system gets one, then we don't know what to do.
...@@ -35,7 +35,7 @@ asmlinkage __visible void __irq_entry do_IRQ(struct pt_regs *regs) ...@@ -35,7 +35,7 @@ asmlinkage __visible void __irq_entry do_IRQ(struct pt_regs *regs)
riscv_software_interrupt(); riscv_software_interrupt();
break; break;
#endif #endif
case IRQ_EXT: case RV_IRQ_EXT:
handle_arch_irq(regs); handle_arch_irq(regs);
break; break;
default: default:
......
...@@ -99,13 +99,13 @@ static void __init setup_initrd(void) ...@@ -99,13 +99,13 @@ static void __init setup_initrd(void)
pr_info("initrd not found or empty"); pr_info("initrd not found or empty");
goto disable; goto disable;
} }
if (__pa(initrd_end) > PFN_PHYS(max_low_pfn)) { if (__pa_symbol(initrd_end) > PFN_PHYS(max_low_pfn)) {
pr_err("initrd extends beyond end of memory"); pr_err("initrd extends beyond end of memory");
goto disable; goto disable;
} }
size = initrd_end - initrd_start; size = initrd_end - initrd_start;
memblock_reserve(__pa(initrd_start), size); memblock_reserve(__pa_symbol(initrd_start), size);
initrd_below_start_ok = 1; initrd_below_start_ok = 1;
pr_info("Initial ramdisk at: 0x%p (%lu bytes)\n", pr_info("Initial ramdisk at: 0x%p (%lu bytes)\n",
...@@ -124,8 +124,8 @@ void __init setup_bootmem(void) ...@@ -124,8 +124,8 @@ void __init setup_bootmem(void)
{ {
struct memblock_region *reg; struct memblock_region *reg;
phys_addr_t mem_size = 0; phys_addr_t mem_size = 0;
phys_addr_t vmlinux_end = __pa(&_end); phys_addr_t vmlinux_end = __pa_symbol(&_end);
phys_addr_t vmlinux_start = __pa(&_start); phys_addr_t vmlinux_start = __pa_symbol(&_start);
/* Find the memory region containing the kernel */ /* Find the memory region containing the kernel */
for_each_memblock(memory, reg) { for_each_memblock(memory, reg) {
...@@ -445,7 +445,7 @@ static void __init setup_vm_final(void) ...@@ -445,7 +445,7 @@ static void __init setup_vm_final(void)
/* Setup swapper PGD for fixmap */ /* Setup swapper PGD for fixmap */
create_pgd_mapping(swapper_pg_dir, FIXADDR_START, create_pgd_mapping(swapper_pg_dir, FIXADDR_START,
__pa(fixmap_pgd_next), __pa_symbol(fixmap_pgd_next),
PGDIR_SIZE, PAGE_TABLE); PGDIR_SIZE, PAGE_TABLE);
/* Map all memory banks */ /* Map all memory banks */
...@@ -474,7 +474,7 @@ static void __init setup_vm_final(void) ...@@ -474,7 +474,7 @@ static void __init setup_vm_final(void)
clear_fixmap(FIX_PMD); clear_fixmap(FIX_PMD);
/* Move to swapper page table */ /* Move to swapper page table */
csr_write(CSR_SATP, PFN_DOWN(__pa(swapper_pg_dir)) | SATP_MODE); csr_write(CSR_SATP, PFN_DOWN(__pa_symbol(swapper_pg_dir)) | SATP_MODE);
local_flush_tlb_all(); local_flush_tlb_all();
} }
#else #else
......
...@@ -56,7 +56,7 @@ static unsigned long long riscv_clocksource_rdtime(struct clocksource *cs) ...@@ -56,7 +56,7 @@ static unsigned long long riscv_clocksource_rdtime(struct clocksource *cs)
return get_cycles64(); return get_cycles64();
} }
static u64 riscv_sched_clock(void) static u64 notrace riscv_sched_clock(void)
{ {
return get_cycles64(); return get_cycles64();
} }
......
...@@ -256,7 +256,7 @@ static int __init plic_init(struct device_node *node, ...@@ -256,7 +256,7 @@ static int __init plic_init(struct device_node *node,
* Skip contexts other than external interrupts for our * Skip contexts other than external interrupts for our
* privilege level. * privilege level.
*/ */
if (parent.args[0] != IRQ_EXT) if (parent.args[0] != RV_IRQ_EXT)
continue; continue;
hartid = plic_find_hart_id(parent.np); hartid = plic_find_hart_id(parent.np);
......
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