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Merge tag 'mtk-dts64-for-v6.8' of... 

Merge tag 'mtk-dts64-for-v6.8' of https://git.kernel.org/pub/scm/linux/kernel/git/mediatek/linux into soc/dt

MediaTek ARM64 DeviceTree updates for v6.8

This adds devicetree bindings and nodes for:
 - Media Data Path 3 (MDP3) bindings and enablement on MT8195
 - Smart Voltage Scaling (SVS) on MT8195
 - LVTS SoC thermal on MT8192
 - MT8188 SoC along with its resets, display bindings, and more
 - MT8183 hardware video decoder (mtk-vcodec-dec)

Adds the following new machines:
 - MT8188 Evaluation Board (EVB)
 - MT8183 Chromebooks: Kukui-Katsu, Jacuzzi-Makomo, Pico, Pico6

Performs cleanups for various MediaTek SoCs and PMICs, and also
includes some spare fixes.

* tag 'mtk-dts64-for-v6.8' of https://git.kernel.org/pub/scm/linux/kernel/git/mediatek/linux: (60 commits)
  arm64: dts: mediatek: mt8192: Add Smart Voltage Scaling node
  arm64: dts: mediatek: mt8195: Add SVS node and reduce LVTS_AP iospace
  arm64: dts: mediatek: mt8183: Change iospaces for thermal and svs
  arm64: dts: mediatek: mt8186: fix address warning for ADSP mailboxes
  arm64: dts: mediatek: mt8186: Fix alias prefix for ovl_2l0
  arm64: dts: mt6358: Drop bogus "regulator-fixed" compatible properties
  arm64: dts: mt8183: kukui-jacuzzi: Drop bogus anx7625 panel_flag property
  arm64: dts: Add MediaTek MT8188 dts and evaluation board and Makefile
  dt-bindings: soc: mediatek: pwrap: Modify compatible for MT8188
  dt-bindings: arm: mediatek: Add mt8188 pericfg compatible
  dt-bindings: arm: Add compatible for MediaTek MT8188
  arm64: dts: mediatek: mt8195: add DSI and MIPI DPHY nodes
  dt-bindings: display: mediatek: dsi: add compatible for MediaTek MT8195
  arm64: dts: mediatek: mt6358: Merge ldo_vcn33_* regulators
  dt-bindings: arm: mediatek: convert audsys and mt2701-afe-pcm to yaml
  arm64: dts: mediatek: mt8195: add MDP3 nodes
  arm64: dts: mediatek: mt8195: revise VDOSYS RDMA node name
  arm64: dts: mediatek: mt8183: correct MDP3 DMA-related nodes
  dt-bindings: display: mediatek: padding: add compatible for MT8195
  dt-bindings: display: mediatek: split: add compatible for MT8195
  ...

Link: https://lore.kernel.org/r/20231212114515.121695-1-angelogioacchino.delregno@collabora.comSigned-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents 9bc75fe5 5dc289e0
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Showing with 3826 additions and 392 deletions
Documentation/devicetree/bindings/arm/mediatek.yaml
View file @ 76955bc8
......@@ -174,6 +174,10 @@ properties:
- enum:
- mediatek,mt8186-evb
- const: mediatek,mt8186
- items:
- enum:
- mediatek,mt8188-evb
- const: mediatek,mt8188
- items:
- enum:
- mediatek,mt8192-evb
......@@ -235,6 +239,13 @@ properties:
items:
- const: google,kappa
- const: mediatek,mt8183
- description: Google Katsu (ASUS Chromebook Detachable CZ1)
items:
- enum:
- google,katsu-sku32
- google,katsu-sku38
- const: google,katsu
- const: mediatek,mt8183
- description: Google Kodama (Lenovo 10e Chromebook Tablet)
items:
- enum:
......@@ -244,6 +255,20 @@ properties:
- google,kodama-sku32
- const: google,kodama
- const: mediatek,mt8183
- description: Google Makomo (Lenovo 100e Chromebook 2nd Gen MTK 2)
items:
- enum:
- google,makomo-sku0
- google,makomo-sku1
- const: google,makomo
- const: mediatek,mt8183
- description: Google Pico (Acer Chromebook Spin 311)
items:
- enum:
- google,pico-sku1
- google,pico-sku2
- const: google,pico
- const: mediatek,mt8183
- description: Google Willow (Acer Chromebook 311 C722/C722T)
items:
- enum:
......
Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt deleted 100644 → 0
View file @ 9bc75fe5
MediaTek AUDSYS controller
============================
The MediaTek AUDSYS controller provides various clocks to the system.
Required Properties:
- compatible: Should be one of:
- "mediatek,mt2701-audsys", "syscon"
- "mediatek,mt6765-audsys", "syscon"
- "mediatek,mt6779-audio", "syscon"
- "mediatek,mt7622-audsys", "syscon"
- "mediatek,mt7623-audsys", "mediatek,mt2701-audsys", "syscon"
- "mediatek,mt8167-audiosys", "syscon"
- "mediatek,mt8183-audiosys", "syscon"
- "mediatek,mt8192-audsys", "syscon"
- "mediatek,mt8516-audsys", "syscon"
- #clock-cells: Must be 1
The AUDSYS controller uses the common clk binding from
Documentation/devicetree/bindings/clock/clock-bindings.txt
The available clocks are defined in dt-bindings/clock/mt*-clk.h.
Required sub-nodes:
-------
For common binding part and usage, refer to
../sonud/mt2701-afe-pcm.txt.
Example:
audsys: clock-controller@11220000 {
compatible = "mediatek,mt7622-audsys", "syscon";
reg = <0 0x11220000 0 0x2000>;
#clock-cells = <1>;
afe: audio-controller {
...
};
};
Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.yaml 0 → 100644
View file @ 76955bc8
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/mediatek/mediatek,audsys.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: MediaTek AUDSYS controller
maintainers:
- Eugen Hristev <eugen.hristev@collabora.com>
description:
The MediaTek AUDSYS controller provides various clocks to the system.
properties:
compatible:
oneOf:
- items:
- enum:
- mediatek,mt2701-audsys
- mediatek,mt6765-audsys
- mediatek,mt6779-audsys
- mediatek,mt7622-audsys
- mediatek,mt8167-audsys
- mediatek,mt8173-audsys
- mediatek,mt8183-audsys
- mediatek,mt8186-audsys
- mediatek,mt8192-audsys
- mediatek,mt8516-audsys
- const: syscon
- items:
# Special case for mt7623 for backward compatibility
- const: mediatek,mt7623-audsys
- const: mediatek,mt2701-audsys
- const: syscon
reg:
maxItems: 1
'#clock-cells':
const: 1
audio-controller:
$ref: /schemas/sound/mediatek,mt2701-audio.yaml#
type: object
required:
- compatible
- '#clock-cells'
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/power/mt2701-power.h>
#include <dt-bindings/clock/mt2701-clk.h>
soc {
#address-cells = <2>;
#size-cells = <2>;
audsys: clock-controller@11220000 {
compatible = "mediatek,mt7622-audsys", "syscon";
reg = <0 0x11220000 0 0x2000>;
#clock-cells = <1>;
afe: audio-controller {
compatible = "mediatek,mt2701-audio";
interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>,
<GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>;
interrupt-names = "afe", "asys";
power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
clocks = <&infracfg CLK_INFRA_AUDIO>,
<&topckgen CLK_TOP_AUD_MUX1_SEL>,
<&topckgen CLK_TOP_AUD_MUX2_SEL>,
<&topckgen CLK_TOP_AUD_48K_TIMING>,
<&topckgen CLK_TOP_AUD_44K_TIMING>,
<&topckgen CLK_TOP_AUD_K1_SRC_SEL>,
<&topckgen CLK_TOP_AUD_K2_SRC_SEL>,
<&topckgen CLK_TOP_AUD_K3_SRC_SEL>,
<&topckgen CLK_TOP_AUD_K4_SRC_SEL>,
<&topckgen CLK_TOP_AUD_K1_SRC_DIV>,
<&topckgen CLK_TOP_AUD_K2_SRC_DIV>,
<&topckgen CLK_TOP_AUD_K3_SRC_DIV>,
<&topckgen CLK_TOP_AUD_K4_SRC_DIV>,
<&topckgen CLK_TOP_AUD_I2S1_MCLK>,
<&topckgen CLK_TOP_AUD_I2S2_MCLK>,
<&topckgen CLK_TOP_AUD_I2S3_MCLK>,
<&topckgen CLK_TOP_AUD_I2S4_MCLK>,
<&audsys CLK_AUD_I2SO1>,
<&audsys CLK_AUD_I2SO2>,
<&audsys CLK_AUD_I2SO3>,
<&audsys CLK_AUD_I2SO4>,
<&audsys CLK_AUD_I2SIN1>,
<&audsys CLK_AUD_I2SIN2>,
<&audsys CLK_AUD_I2SIN3>,
<&audsys CLK_AUD_I2SIN4>,
<&audsys CLK_AUD_ASRCO1>,
<&audsys CLK_AUD_ASRCO2>,
<&audsys CLK_AUD_ASRCO3>,
<&audsys CLK_AUD_ASRCO4>,
<&audsys CLK_AUD_AFE>,
<&audsys CLK_AUD_AFE_CONN>,
<&audsys CLK_AUD_A1SYS>,
<&audsys CLK_AUD_A2SYS>,
<&audsys CLK_AUD_AFE_MRGIF>;
clock-names = "infra_sys_audio_clk",
"top_audio_mux1_sel",
"top_audio_mux2_sel",
"top_audio_a1sys_hp",
"top_audio_a2sys_hp",
"i2s0_src_sel",
"i2s1_src_sel",
"i2s2_src_sel",
"i2s3_src_sel",
"i2s0_src_div",
"i2s1_src_div",
"i2s2_src_div",
"i2s3_src_div",
"i2s0_mclk_en",
"i2s1_mclk_en",
"i2s2_mclk_en",
"i2s3_mclk_en",
"i2so0_hop_ck",
"i2so1_hop_ck",
"i2so2_hop_ck",
"i2so3_hop_ck",
"i2si0_hop_ck",
"i2si1_hop_ck",
"i2si2_hop_ck",
"i2si3_hop_ck",
"asrc0_out_ck",
"asrc1_out_ck",
"asrc2_out_ck",
"asrc3_out_ck",
"audio_afe_pd",
"audio_afe_conn_pd",
"audio_a1sys_pd",
"audio_a2sys_pd",
"audio_mrgif_pd";
assigned-clocks = <&topckgen CLK_TOP_AUD_MUX1_SEL>,
<&topckgen CLK_TOP_AUD_MUX2_SEL>,
<&topckgen CLK_TOP_AUD_MUX1_DIV>,
<&topckgen CLK_TOP_AUD_MUX2_DIV>;
assigned-clock-parents = <&topckgen CLK_TOP_AUD1PLL_98M>,
<&topckgen CLK_TOP_AUD2PLL_90M>;
assigned-clock-rates = <0>, <0>, <49152000>, <45158400>;
};
};
};
Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
View file @ 76955bc8
......@@ -32,6 +32,9 @@ properties:
- mediatek,mt8183-mmsys
- mediatek,mt8186-mmsys
- mediatek,mt8188-vdosys0
- mediatek,mt8188-vdosys1
- mediatek,mt8188-vppsys0
- mediatek,mt8188-vppsys1
- mediatek,mt8192-mmsys
- mediatek,mt8195-vdosys1
- mediatek,mt8195-vppsys0
......
Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.yaml
View file @ 76955bc8
......@@ -28,6 +28,7 @@ properties:
- mediatek,mt8173-pericfg
- mediatek,mt8183-pericfg
- mediatek,mt8186-pericfg
- mediatek,mt8188-pericfg
- mediatek,mt8195-pericfg
- mediatek,mt8516-pericfg
- const: syscon
......
Documentation/devicetree/bindings/clock/mediatek,mt8188-clock.yaml
View file @ 76955bc8
......@@ -43,8 +43,6 @@ properties:
- mediatek,mt8188-vdecsys
- mediatek,mt8188-vdecsys-soc
- mediatek,mt8188-vencsys
- mediatek,mt8188-vppsys0
- mediatek,mt8188-vppsys1
- mediatek,mt8188-wpesys
- mediatek,mt8188-wpesys-vpp0
......
Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml
View file @ 76955bc8
......@@ -24,6 +24,7 @@ properties:
- enum:
- mediatek,mt8173-disp-aal
- mediatek,mt8183-disp-aal
- mediatek,mt8195-mdp3-aal
- items:
- enum:
- mediatek,mt2712-disp-aal
......
Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml
View file @ 76955bc8
......@@ -26,6 +26,7 @@ properties:
- mediatek,mt2701-disp-color
- mediatek,mt8167-disp-color
- mediatek,mt8173-disp-color
- mediatek,mt8195-mdp3-color
- items:
- enum:
- mediatek,mt7623-disp-color
......
Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.yaml
View file @ 76955bc8
......@@ -35,6 +35,10 @@ properties:
- enum:
- mediatek,mt6795-dsi
- const: mediatek,mt8173-dsi
- items:
- enum:
- mediatek,mt8195-dsi
- const: mediatek,mt8183-dsi
reg:
maxItems: 1
......
Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml
View file @ 76955bc8
......@@ -23,7 +23,11 @@ description:
properties:
compatible:
const: mediatek,mt8195-disp-ethdr
oneOf:
- const: mediatek,mt8195-disp-ethdr
- items:
- const: mediatek,mt8188-disp-ethdr
- const: mediatek,mt8195-disp-ethdr
reg:
maxItems: 7
......
Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml
View file @ 76955bc8
......@@ -24,9 +24,13 @@ properties:
- enum:
- mediatek,mt8173-disp-merge
- mediatek,mt8195-disp-merge
- mediatek,mt8195-mdp3-merge
- items:
- const: mediatek,mt6795-disp-merge
- const: mediatek,mt8173-disp-merge
- items:
- const: mediatek,mt8188-disp-merge
- const: mediatek,mt8195-disp-merge
reg:
maxItems: 1
......
Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml
View file @ 76955bc8
......@@ -26,6 +26,7 @@ properties:
- mediatek,mt8173-disp-ovl
- mediatek,mt8183-disp-ovl
- mediatek,mt8192-disp-ovl
- mediatek,mt8195-mdp3-ovl
- items:
- enum:
- mediatek,mt7623-disp-ovl
......
Documentation/devicetree/bindings/display/mediatek/mediatek,padding.yaml 0 → 100644
View file @ 76955bc8
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/mediatek/mediatek,padding.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: MediaTek Display Padding
maintainers:
- Chun-Kuang Hu <chunkuang.hu@kernel.org>
- Philipp Zabel <p.zabel@pengutronix.de>
description:
Padding provides ability to add pixels to width and height of a layer with
specified colors. Due to hardware design, Mixer in VDOSYS1 requires
width of a layer to be 2-pixel-align, or 4-pixel-align when ETHDR is enabled,
we need Padding to deal with odd width.
Please notice that even if the Padding is in bypass mode, settings in
register must be cleared to 0, or undefined behaviors could happen.
properties:
compatible:
enum:
- mediatek,mt8188-disp-padding
- mediatek,mt8195-mdp3-padding
reg:
maxItems: 1
power-domains:
maxItems: 1
clocks:
items:
- description: Padding's clocks
mediatek,gce-client-reg:
description:
GCE (Global Command Engine) is a multi-core micro processor that helps
its clients to execute commands without interrupting CPU. This property
describes GCE client's information that is composed by 4 fields.
1. Phandle of the GCE (there may be several GCE processors)
2. Sub-system ID defined in the dt-binding like a user ID
(Please refer to include/dt-bindings/gce/<chip>-gce.h)
3. Offset from base address of the subsys you are at
4. Size of the register the client needs
$ref: /schemas/types.yaml#/definitions/phandle-array
items:
items:
- description: Phandle of the GCE
- description: Subsys ID defined in the dt-binding
- description: Offset from base address of the subsys
- description: Size of register
maxItems: 1
required:
- compatible
- reg
- power-domains
- clocks
- mediatek,gce-client-reg
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/mediatek,mt8188-clk.h>
#include <dt-bindings/power/mediatek,mt8188-power.h>
#include <dt-bindings/gce/mt8195-gce.h>
soc {
#address-cells = <2>;
#size-cells = <2>;
padding0: padding@1c11d000 {
compatible = "mediatek,mt8188-disp-padding";
reg = <0 0x1c11d000 0 0x1000>;
clocks = <&vdosys1 CLK_VDO1_PADDING0>;
power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>;
mediatek,gce-client-reg = <&gce0 SUBSYS_1c11XXXX 0xd000 0x1000>;
};
};
Documentation/devicetree/bindings/display/mediatek/mediatek,split.yaml
View file @ 76955bc8
......@@ -23,6 +23,7 @@ properties:
oneOf:
- enum:
- mediatek,mt8173-disp-split
- mediatek,mt8195-mdp3-split
- items:
- const: mediatek,mt6795-disp-split
- const: mediatek,mt8173-disp-split
......@@ -38,6 +39,21 @@ properties:
the power controller specified by phandle. See
Documentation/devicetree/bindings/power/power-domain.yaml for details.
mediatek,gce-client-reg:
description:
The register of display function block to be set by gce. There are 4 arguments,
such as gce node, subsys id, offset and register size. The subsys id that is
mapping to the register of display function blocks is defined in the gce header
include/dt-bindings/gce/<chip>-gce.h of each chips.
$ref: /schemas/types.yaml#/definitions/phandle-array
items:
items:
- description: phandle of GCE
- description: GCE subsys id
- description: register offset
- description: register size
maxItems: 1
clocks:
items:
- description: SPLIT Clock
......@@ -48,6 +64,17 @@ required:
- power-domains
- clocks
allOf:
- if:
properties:
compatible:
contains:
const: mediatek,mt8195-mdp3-split
then:
required:
- mediatek,gce-client-reg
additionalProperties: false
examples:
......
Documentation/devicetree/bindings/display/mediatek/mediatek,mdp-rdma.yaml → Documentation/devicetree/bindings/media/mediatek,mdp3-fg.yaml
View file @ 76955bc8
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/mediatek/mediatek,mdp-rdma.yaml#
$id: http://devicetree.org/schemas/media/mediatek,mdp3-fg.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: MediaTek MDP RDMA
title: MediaTek Media Data Path 3 Film Grain
maintainers:
- Chun-Kuang Hu <chunkuang.hu@kernel.org>
- Philipp Zabel <p.zabel@pengutronix.de>
- Matthias Brugger <matthias.bgg@gmail.com>
- Moudy Ho <moudy.ho@mediatek.com>
description:
The MediaTek MDP RDMA stands for Read Direct Memory Access.
It provides real time data to the back-end panel driver, such as DSI,
DPI and DP_INTF.
It contains one line buffer to store the sufficient pixel data.
RDMA device node must be siblings to the central MMSYS_CONFIG node.
For a description of the MMSYS_CONFIG binding, see
Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml for details.
Film Grain (FG) is a Media Data Path 3 (MDP3) component used to add
the film grain according to the AOMedia Video 1 (AV1) standard.
properties:
compatible:
const: mediatek,mt8195-vdo1-rdma
enum:
- mediatek,mt8195-mdp3-fg
reg:
maxItems: 1
interrupts:
maxItems: 1
power-domains:
maxItems: 1
clocks:
items:
- description: RDMA Clock
iommus:
maxItems: 1
mediatek,gce-client-reg:
description:
The register of display function block to be set by gce. There are 4 arguments,
......@@ -54,35 +37,25 @@ properties:
- description: register size
maxItems: 1
clocks:
maxItems: 1
required:
- compatible
- reg
- power-domains
- clocks
- iommus
- mediatek,gce-client-reg
- clocks
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/mt8195-clk.h>
#include <dt-bindings/power/mt8195-power.h>
#include <dt-bindings/gce/mt8195-gce.h>
#include <dt-bindings/memory/mt8195-memory-port.h>
soc {
#address-cells = <2>;
#size-cells = <2>;
rdma@1c104000 {
compatible = "mediatek,mt8195-vdo1-rdma";
reg = <0 0x1c104000 0 0x1000>;
interrupts = <GIC_SPI 495 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&vdosys1 CLK_VDO1_MDP_RDMA0>;
power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA0>;
mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x4000 0x1000>;
};
display@14002000 {
compatible = "mediatek,mt8195-mdp3-fg";
reg = <0x14002000 0x1000>;
mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x2000 0x1000>;
clocks = <&vppsys0 CLK_VPP0_MDP_FG>;
};
Documentation/devicetree/bindings/media/mediatek,mdp3-hdr.yaml 0 → 100644
View file @ 76955bc8
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/media/mediatek,mdp3-hdr.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: MediaTek Media Data Path 3 HDR
maintainers:
- Matthias Brugger <matthias.bgg@gmail.com>
- Moudy Ho <moudy.ho@mediatek.com>
description:
A Media Data Path 3 (MDP3) component used to perform conversion from
High Dynamic Range (HDR) to Standard Dynamic Range (SDR).
properties:
compatible:
enum:
- mediatek,mt8195-mdp3-hdr
reg:
maxItems: 1
mediatek,gce-client-reg:
description:
The register of display function block to be set by gce. There are 4 arguments,
such as gce node, subsys id, offset and register size. The subsys id that is
mapping to the register of display function blocks is defined in the gce header
include/dt-bindings/gce/<chip>-gce.h of each chips.
$ref: /schemas/types.yaml#/definitions/phandle-array
items:
items:
- description: phandle of GCE
- description: GCE subsys id
- description: register offset
- description: register size
maxItems: 1
clocks:
maxItems: 1
required:
- compatible
- reg
- mediatek,gce-client-reg
- clocks
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/mt8195-clk.h>
#include <dt-bindings/gce/mt8195-gce.h>
display@14004000 {
compatible = "mediatek,mt8195-mdp3-hdr";
reg = <0x14004000 0x1000>;
mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x4000 0x1000>;
clocks = <&vppsys0 CLK_VPP0_MDP_HDR>;
};
Documentation/devicetree/bindings/media/mediatek,mdp3-rdma.yaml
View file @ 76955bc8
......@@ -20,8 +20,14 @@ description: |
properties:
compatible:
items:
- const: mediatek,mt8183-mdp3-rdma
oneOf:
- enum:
- mediatek,mt8183-mdp3-rdma
- mediatek,mt8195-mdp3-rdma
- mediatek,mt8195-vdo1-rdma
- items:
- const: mediatek,mt8188-vdo1-rdma
- const: mediatek,mt8195-vdo1-rdma
reg:
maxItems: 1
......@@ -45,6 +51,14 @@ properties:
include/dt-bindings/gce/<chip>-gce.h of each chips.
$ref: /schemas/types.yaml#/definitions/uint32-array
mediatek,scp:
$ref: /schemas/types.yaml#/definitions/phandle
description:
Phandle to the System Control Processor (SCP) used for initializing
and stopping the MDP3, for sending frame data locations to the MDP3's
VPU and to install Inter-Processor Interrupt handlers to control
processing states.
power-domains:
maxItems: 1
......@@ -52,6 +66,7 @@ properties:
items:
- description: RDMA clock
- description: RSZ clock
minItems: 1
iommus:
maxItems: 1
......@@ -60,16 +75,72 @@ properties:
items:
- description: used for 1st data pipe from RDMA
- description: used for 2nd data pipe from RDMA
- description: used for 3rd data pipe from RDMA
- description: used for 4th data pipe from RDMA
- description: used for the data pipe from SPLIT
minItems: 1
interrupts:
maxItems: 1
'#dma-cells':
const: 1
required:
- compatible
- reg
- mediatek,gce-client-reg
- mediatek,gce-events
- power-domains
- clocks
- iommus
- mboxes
- '#dma-cells'
allOf:
- if:
properties:
compatible:
contains:
const: mediatek,mt8183-mdp3-rdma
then:
properties:
clocks:
minItems: 2
mboxes:
minItems: 2
required:
- mboxes
- mediatek,gce-events
- if:
properties:
compatible:
contains:
const: mediatek,mt8195-mdp3-rdma
then:
properties:
clocks:
maxItems: 1
mboxes:
minItems: 5
required:
- mediatek,gce-events
- if:
properties:
compatible:
contains:
const: mediatek,mt8195-vdo1-rdma
then:
properties:
clocks:
maxItems: 1
additionalProperties: false
......@@ -80,16 +151,17 @@ examples:
#include <dt-bindings/power/mt8183-power.h>
#include <dt-bindings/memory/mt8183-larb-port.h>
mdp3_rdma0: mdp3-rdma0@14001000 {
compatible = "mediatek,mt8183-mdp3-rdma";
reg = <0x14001000 0x1000>;
mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x1000 0x1000>;
mediatek,gce-events = <CMDQ_EVENT_MDP_RDMA0_SOF>,
<CMDQ_EVENT_MDP_RDMA0_EOF>;
power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
clocks = <&mmsys CLK_MM_MDP_RDMA0>,
<&mmsys CLK_MM_MDP_RSZ1>;
iommus = <&iommu>;
mboxes = <&gce 20 CMDQ_THR_PRIO_LOWEST>,
<&gce 21 CMDQ_THR_PRIO_LOWEST>;
dma-controller@14001000 {
compatible = "mediatek,mt8183-mdp3-rdma";
reg = <0x14001000 0x1000>;
mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x1000 0x1000>;
mediatek,gce-events = <CMDQ_EVENT_MDP_RDMA0_SOF>,
<CMDQ_EVENT_MDP_RDMA0_EOF>;
power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
clocks = <&mmsys CLK_MM_MDP_RDMA0>,
<&mmsys CLK_MM_MDP_RSZ1>;
iommus = <&iommu>;
mboxes = <&gce 20 CMDQ_THR_PRIO_LOWEST>,
<&gce 21 CMDQ_THR_PRIO_LOWEST>;
#dma-cells = <1>;
};
Documentation/devicetree/bindings/media/mediatek,mdp3-rsz.yaml
View file @ 76955bc8
......@@ -15,9 +15,13 @@ description: |
properties:
compatible:
items:
oneOf:
- enum:
- mediatek,mt8183-mdp3-rsz
- items:
- enum:
- mediatek,mt8195-mdp3-rsz
- const: mediatek,mt8183-mdp3-rsz
reg:
maxItems: 1
......
Documentation/devicetree/bindings/media/mediatek,mdp3-stitch.yaml 0 → 100644
View file @ 76955bc8
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/media/mediatek,mdp3-stitch.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: MediaTek Media Data Path 3 STITCH
maintainers:
- Matthias Brugger <matthias.bgg@gmail.com>
- Moudy Ho <moudy.ho@mediatek.com>
description:
One of Media Data Path 3 (MDP3) components used to combine multiple video frame
with overlapping fields of view to produce a segmented panorame.
properties:
compatible:
enum:
- mediatek,mt8195-mdp3-stitch
reg:
maxItems: 1
mediatek,gce-client-reg:
description:
The register of display function block to be set by gce. There are 4 arguments,
such as gce node, subsys id, offset and register size. The subsys id that is
mapping to the register of display function blocks is defined in the gce header
include/dt-bindings/gce/<chip>-gce.h of each chips.
$ref: /schemas/types.yaml#/definitions/phandle-array
items:
items:
- description: phandle of GCE
- description: GCE subsys id
- description: register offset
- description: register size
maxItems: 1
clocks:
maxItems: 1
required:
- compatible
- reg
- mediatek,gce-client-reg
- clocks
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/mt8195-clk.h>
#include <dt-bindings/gce/mt8195-gce.h>
display@14003000 {
compatible = "mediatek,mt8195-mdp3-stitch";
reg = <0x14003000 0x1000>;
mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x3000 0x1000>;
clocks = <&vppsys0 CLK_VPP0_STITCH>;
};
Documentation/devicetree/bindings/media/mediatek,mdp3-tcc.yaml 0 → 100644
View file @ 76955bc8
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/media/mediatek,mdp3-tcc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: MediaTek Media Data Path 3 Tone Curve Conversion
maintainers:
- Matthias Brugger <matthias.bgg@gmail.com>
description:
Tone Curve Conversion (TCC) is one of Media Profile Path 3 (MDP3) components.
It is used to handle the tone mapping of various gamma curves in order to
achieve HDR10 effects. This helps adapt the content to the color and
brightness range that standard display devices typically support.
properties:
compatible:
enum:
- mediatek,mt8195-mdp3-tcc
reg:
maxItems: 1
mediatek,gce-client-reg:
description:
The register of display function block to be set by gce. There are 4 arguments,
such as gce node, subsys id, offset and register size. The subsys id that is
mapping to the register of display function blocks is defined in the gce header
include/dt-bindings/gce/<chip>-gce.h of each chips.
$ref: /schemas/types.yaml#/definitions/phandle-array
items:
items:
- description: phandle of GCE
- description: GCE subsys id
- description: register offset
- description: register size
maxItems: 1
clocks:
maxItems: 1
required:
- compatible
- reg
- mediatek,gce-client-reg
- clocks
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/mt8195-clk.h>
#include <dt-bindings/gce/mt8195-gce.h>
display@1400b000 {
compatible = "mediatek,mt8195-mdp3-tcc";
reg = <0x1400b000 0x1000>;
mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0xb000 0x1000>;
clocks = <&vppsys0 CLK_VPP0_MDP_TCC>;
};
Documentation/devicetree/bindings/media/mediatek,mdp3-tdshp.yaml 0 → 100644
View file @ 76955bc8
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/media/mediatek,mdp3-tdshp.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: MediaTek Media Data Path 3 Two-Dimensional Sharpness
maintainers:
- Matthias Brugger <matthias.bgg@gmail.com>
- Moudy Ho <moudy.ho@mediatek.com>
description:
Two-Dimensional Sharpness (TDSHP) is a Media Profile Path 3 (MDP3) component
used to perform image edge sharpening and enhance vividness and contrast.
properties:
compatible:
enum:
- mediatek,mt8195-mdp3-tdshp
reg:
maxItems: 1
mediatek,gce-client-reg:
description:
The register of display function block to be set by gce. There are 4 arguments,
such as gce node, subsys id, offset and register size. The subsys id that is
mapping to the register of display function blocks is defined in the gce header
include/dt-bindings/gce/<chip>-gce.h of each chips.
$ref: /schemas/types.yaml#/definitions/phandle-array
items:
items:
- description: phandle of GCE
- description: GCE subsys id
- description: register offset
- description: register size
maxItems: 1
clocks:
maxItems: 1
required:
- compatible
- reg
- mediatek,gce-client-reg
- clocks
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/mt8195-clk.h>
#include <dt-bindings/gce/mt8195-gce.h>
display@14007000 {
compatible = "mediatek,mt8195-mdp3-tdshp";
reg = <0x14007000 0x1000>;
mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x7000 0x1000>;
clocks = <&vppsys0 CLK_VPP0_MDP_TDSHP>;
};
Documentation/devicetree/bindings/media/mediatek,mdp3-wrot.yaml
View file @ 76955bc8
......@@ -15,9 +15,13 @@ description: |
properties:
compatible:
items:
oneOf:
- enum:
- mediatek,mt8183-mdp3-wrot
- items:
- enum:
- mediatek,mt8195-mdp3-wrot
- const: mediatek,mt8183-mdp3-wrot
reg:
maxItems: 1
......@@ -50,6 +54,9 @@ properties:
iommus:
maxItems: 1
'#dma-cells':
const: 1
required:
- compatible
- reg
......@@ -58,6 +65,7 @@ required:
- power-domains
- clocks
- iommus
- '#dma-cells'
additionalProperties: false
......@@ -68,13 +76,14 @@ examples:
#include <dt-bindings/power/mt8183-power.h>
#include <dt-bindings/memory/mt8183-larb-port.h>
mdp3_wrot0: mdp3-wrot0@14005000 {
compatible = "mediatek,mt8183-mdp3-wrot";
reg = <0x14005000 0x1000>;
mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x5000 0x1000>;
mediatek,gce-events = <CMDQ_EVENT_MDP_WROT0_SOF>,
<CMDQ_EVENT_MDP_WROT0_EOF>;
power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
clocks = <&mmsys CLK_MM_MDP_WROT0>;
iommus = <&iommu>;
dma-controller@14005000 {
compatible = "mediatek,mt8183-mdp3-wrot";
reg = <0x14005000 0x1000>;
mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x5000 0x1000>;
mediatek,gce-events = <CMDQ_EVENT_MDP_WROT0_SOF>,
<CMDQ_EVENT_MDP_WROT0_EOF>;
power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
clocks = <&mmsys CLK_MM_MDP_WROT0>;
iommus = <&iommu>;
#dma-cells = <1>;
};
Documentation/devicetree/bindings/soc/mediatek/mediatek,pwrap.yaml
View file @ 76955bc8
......@@ -41,7 +41,6 @@ properties:
- mediatek,mt8173-pwrap
- mediatek,mt8183-pwrap
- mediatek,mt8186-pwrap
- mediatek,mt8188-pwrap
- mediatek,mt8195-pwrap
- mediatek,mt8365-pwrap
- mediatek,mt8516-pwrap
......@@ -50,6 +49,11 @@ properties:
- mediatek,mt8186-pwrap
- mediatek,mt8195-pwrap
- const: syscon
- items:
- enum:
- mediatek,mt8188-pwrap
- const: mediatek,mt8195-pwrap
- const: syscon
reg:
minItems: 1
......
Documentation/devicetree/bindings/soc/mediatek/mtk-svs.yaml
View file @ 76955bc8
......@@ -22,8 +22,10 @@ properties:
compatible:
enum:
- mediatek,mt8183-svs
- mediatek,mt8186-svs
- mediatek,mt8188-svs
- mediatek,mt8192-svs
- mediatek,mt8195-svs
reg:
maxItems: 1
......
Documentation/devicetree/bindings/sound/mediatek,mt2701-audio.yaml 0 → 100644
View file @ 76955bc8
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/sound/mediatek,mt2701-audio.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: MediaTek Audio Front End (AFE) PCM controller for mt2701
description:
The AFE PCM node must be a subnode of the MediaTek audsys device tree node.
maintainers:
- Eugen Hristev <eugen.hristev@collabora.com>
properties:
compatible:
enum:
- mediatek,mt2701-audio
- mediatek,mt7622-audio
interrupts:
items:
- description: AFE interrupt
- description: ASYS interrupt
interrupt-names:
items:
- const: afe
- const: asys
power-domains:
maxItems: 1
clocks:
items:
- description: audio infra sys clock
- description: top audio mux 1
- description: top audio mux 2
- description: top audio sys a1 clock
- description: top audio sys a2 clock
- description: i2s0 source selection
- description: i2s1 source selection
- description: i2s2 source selection
- description: i2s3 source selection
- description: i2s0 source divider
- description: i2s1 source divider
- description: i2s2 source divider
- description: i2s3 source divider
- description: i2s0 master clock
- description: i2s1 master clock
- description: i2s2 master clock
- description: i2s3 master clock
- description: i2so0 hopping clock
- description: i2so1 hopping clock
- description: i2so2 hopping clock
- description: i2so3 hopping clock
- description: i2si0 hopping clock
- description: i2si1 hopping clock
- description: i2si2 hopping clock
- description: i2si3 hopping clock
- description: asrc0 output clock
- description: asrc1 output clock
- description: asrc2 output clock
- description: asrc3 output clock
- description: audio front end pd clock
- description: audio front end conn pd clock
- description: top audio a1 sys pd
- description: top audio a2 sys pd
- description: audio merge interface pd
clock-names:
items:
- const: infra_sys_audio_clk
- const: top_audio_mux1_sel
- const: top_audio_mux2_sel
- const: top_audio_a1sys_hp
- const: top_audio_a2sys_hp
- const: i2s0_src_sel
- const: i2s1_src_sel
- const: i2s2_src_sel
- const: i2s3_src_sel
- const: i2s0_src_div
- const: i2s1_src_div
- const: i2s2_src_div
- const: i2s3_src_div
- const: i2s0_mclk_en
- const: i2s1_mclk_en
- const: i2s2_mclk_en
- const: i2s3_mclk_en
- const: i2so0_hop_ck
- const: i2so1_hop_ck
- const: i2so2_hop_ck
- const: i2so3_hop_ck
- const: i2si0_hop_ck
- const: i2si1_hop_ck
- const: i2si2_hop_ck
- const: i2si3_hop_ck
- const: asrc0_out_ck
- const: asrc1_out_ck
- const: asrc2_out_ck
- const: asrc3_out_ck
- const: audio_afe_pd
- const: audio_afe_conn_pd
- const: audio_a1sys_pd
- const: audio_a2sys_pd
- const: audio_mrgif_pd
required:
- compatible
- interrupts
- interrupt-names
- power-domains
- clocks
- clock-names
additionalProperties: false
Documentation/devicetree/bindings/sound/mt2701-afe-pcm.txt deleted 100644 → 0
View file @ 9bc75fe5
Mediatek AFE PCM controller for mt2701
Required properties:
- compatible: should be one of the following.
- "mediatek,mt2701-audio"
- "mediatek,mt7622-audio"
- interrupts: should contain AFE and ASYS interrupts
- interrupt-names: should be "afe" and "asys"
- power-domains: should define the power domain
- clocks: Must contain an entry for each entry in clock-names
See ../clocks/clock-bindings.txt for details
- clock-names: should have these clock names:
"infra_sys_audio_clk",
"top_audio_mux1_sel",
"top_audio_mux2_sel",
"top_audio_a1sys_hp",
"top_audio_a2sys_hp",
"i2s0_src_sel",
"i2s1_src_sel",
"i2s2_src_sel",
"i2s3_src_sel",
"i2s0_src_div",
"i2s1_src_div",
"i2s2_src_div",
"i2s3_src_div",
"i2s0_mclk_en",
"i2s1_mclk_en",
"i2s2_mclk_en",
"i2s3_mclk_en",
"i2so0_hop_ck",
"i2so1_hop_ck",
"i2so2_hop_ck",
"i2so3_hop_ck",
"i2si0_hop_ck",
"i2si1_hop_ck",
"i2si2_hop_ck",
"i2si3_hop_ck",
"asrc0_out_ck",
"asrc1_out_ck",
"asrc2_out_ck",
"asrc3_out_ck",
"audio_afe_pd",
"audio_afe_conn_pd",
"audio_a1sys_pd",
"audio_a2sys_pd",
"audio_mrgif_pd";
- assigned-clocks: list of input clocks and dividers for the audio system.
See ../clocks/clock-bindings.txt for details.
- assigned-clocks-parents: parent of input clocks of assigned clocks.
- assigned-clock-rates: list of clock frequencies of assigned clocks.
Must be a subnode of MediaTek audsys device tree node.
See ../arm/mediatek/mediatek,audsys.txt for details about the parent node.
Example:
audsys: audio-subsystem@11220000 {
compatible = "mediatek,mt2701-audsys", "syscon";
...
afe: audio-controller {
compatible = "mediatek,mt2701-audio";
interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>,
<GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>;
interrupt-names = "afe", "asys";
power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
clocks = <&infracfg CLK_INFRA_AUDIO>,
<&topckgen CLK_TOP_AUD_MUX1_SEL>,
<&topckgen CLK_TOP_AUD_MUX2_SEL>,
<&topckgen CLK_TOP_AUD_48K_TIMING>,
<&topckgen CLK_TOP_AUD_44K_TIMING>,
<&topckgen CLK_TOP_AUD_K1_SRC_SEL>,
<&topckgen CLK_TOP_AUD_K2_SRC_SEL>,
<&topckgen CLK_TOP_AUD_K3_SRC_SEL>,
<&topckgen CLK_TOP_AUD_K4_SRC_SEL>,
<&topckgen CLK_TOP_AUD_K1_SRC_DIV>,
<&topckgen CLK_TOP_AUD_K2_SRC_DIV>,
<&topckgen CLK_TOP_AUD_K3_SRC_DIV>,
<&topckgen CLK_TOP_AUD_K4_SRC_DIV>,
<&topckgen CLK_TOP_AUD_I2S1_MCLK>,
<&topckgen CLK_TOP_AUD_I2S2_MCLK>,
<&topckgen CLK_TOP_AUD_I2S3_MCLK>,
<&topckgen CLK_TOP_AUD_I2S4_MCLK>,
<&audsys CLK_AUD_I2SO1>,
<&audsys CLK_AUD_I2SO2>,
<&audsys CLK_AUD_I2SO3>,
<&audsys CLK_AUD_I2SO4>,
<&audsys CLK_AUD_I2SIN1>,
<&audsys CLK_AUD_I2SIN2>,
<&audsys CLK_AUD_I2SIN3>,
<&audsys CLK_AUD_I2SIN4>,
<&audsys CLK_AUD_ASRCO1>,
<&audsys CLK_AUD_ASRCO2>,
<&audsys CLK_AUD_ASRCO3>,
<&audsys CLK_AUD_ASRCO4>,
<&audsys CLK_AUD_AFE>,
<&audsys CLK_AUD_AFE_CONN>,
<&audsys CLK_AUD_A1SYS>,
<&audsys CLK_AUD_A2SYS>,
<&audsys CLK_AUD_AFE_MRGIF>;
clock-names = "infra_sys_audio_clk",
"top_audio_mux1_sel",
"top_audio_mux2_sel",
"top_audio_a1sys_hp",
"top_audio_a2sys_hp",
"i2s0_src_sel",
"i2s1_src_sel",
"i2s2_src_sel",
"i2s3_src_sel",
"i2s0_src_div",
"i2s1_src_div",
"i2s2_src_div",
"i2s3_src_div",
"i2s0_mclk_en",
"i2s1_mclk_en",
"i2s2_mclk_en",
"i2s3_mclk_en",
"i2so0_hop_ck",
"i2so1_hop_ck",
"i2so2_hop_ck",
"i2so3_hop_ck",
"i2si0_hop_ck",
"i2si1_hop_ck",
"i2si2_hop_ck",
"i2si3_hop_ck",
"asrc0_out_ck",
"asrc1_out_ck",
"asrc2_out_ck",
"asrc3_out_ck",
"audio_afe_pd",
"audio_afe_conn_pd",
"audio_a1sys_pd",
"audio_a2sys_pd",
"audio_mrgif_pd";
assigned-clocks = <&topckgen CLK_TOP_AUD_MUX1_SEL>,
<&topckgen CLK_TOP_AUD_MUX2_SEL>,
<&topckgen CLK_TOP_AUD_MUX1_DIV>,
<&topckgen CLK_TOP_AUD_MUX2_DIV>;
assigned-clock-parents = <&topckgen CLK_TOP_AUD1PLL_98M>,
<&topckgen CLK_TOP_AUD2PLL_90M>;
assigned-clock-rates = <0>, <0>, <49152000>, <45158400>;
};
};
Documentation/devicetree/bindings/thermal/mediatek,thermal.yaml 0 → 100644
View file @ 76955bc8
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/thermal/mediatek,thermal.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Mediatek thermal controller for on-SoC temperatures
maintainers:
- Sascha Hauer <s.hauer@pengutronix.de>
description:
This device does not have its own ADC, instead it directly controls the AUXADC
via AHB bus accesses. For this reason it needs phandles to the AUXADC. Also it
controls a mux in the apmixedsys register space via AHB bus accesses, so a
phandle to the APMIXEDSYS is also needed.
allOf:
- $ref: thermal-sensor.yaml#
properties:
compatible:
enum:
- mediatek,mt2701-thermal
- mediatek,mt2712-thermal
- mediatek,mt7622-thermal
- mediatek,mt7981-thermal
- mediatek,mt7986-thermal
- mediatek,mt8173-thermal
- mediatek,mt8183-thermal
- mediatek,mt8365-thermal
- mediatek,mt8516-thermal
reg:
maxItems: 1
interrupts:
maxItems: 1
clocks:
items:
- description: Main clock needed for register access
- description: The AUXADC clock
clock-names:
items:
- const: therm
- const: auxadc
mediatek,auxadc:
$ref: /schemas/types.yaml#/definitions/phandle
description: A phandle to the AUXADC which the thermal controller uses
mediatek,apmixedsys:
$ref: /schemas/types.yaml#/definitions/phandle
description: A phandle to the APMIXEDSYS controller
resets:
description: Reset controller controlling the thermal controller
nvmem-cells:
items:
- description:
NVMEM cell with EEPROMA phandle to the calibration data provided by an
NVMEM device. If unspecified default values shall be used.
nvmem-cell-names:
items:
- const: calibration-data
required:
- reg
- interrupts
- clocks
- clock-names
- mediatek,auxadc
- mediatek,apmixedsys
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/clock/mt8173-clk.h>
#include <dt-bindings/reset/mt8173-resets.h>
thermal@1100b000 {
compatible = "mediatek,mt8173-thermal";
reg = <0x1100b000 0x1000>;
interrupts = <0 70 IRQ_TYPE_LEVEL_LOW>;
clocks = <&pericfg CLK_PERI_THERM>, <&pericfg CLK_PERI_AUXADC>;
clock-names = "therm", "auxadc";
resets = <&pericfg MT8173_PERI_THERM_SW_RST>;
mediatek,auxadc = <&auxadc>;
mediatek,apmixedsys = <&apmixedsys>;
nvmem-cells = <&thermal_calibration_data>;
nvmem-cell-names = "calibration-data";
#thermal-sensor-cells = <1>;
};
Documentation/devicetree/bindings/thermal/mediatek-thermal.txt deleted 100644 → 0
View file @ 9bc75fe5
* Mediatek Thermal
This describes the device tree binding for the Mediatek thermal controller
which measures the on-SoC temperatures. This device does not have its own ADC,
instead it directly controls the AUXADC via AHB bus accesses. For this reason
this device needs phandles to the AUXADC. Also it controls a mux in the
apmixedsys register space via AHB bus accesses, so a phandle to the APMIXEDSYS
is also needed.
Required properties:
- compatible:
- "mediatek,mt8173-thermal" : For MT8173 family of SoCs
- "mediatek,mt2701-thermal" : For MT2701 family of SoCs
- "mediatek,mt2712-thermal" : For MT2712 family of SoCs
- "mediatek,mt7622-thermal" : For MT7622 SoC
- "mediatek,mt7981-thermal", "mediatek,mt7986-thermal" : For MT7981 SoC
- "mediatek,mt7986-thermal" : For MT7986 SoC
- "mediatek,mt8183-thermal" : For MT8183 family of SoCs
- "mediatek,mt8365-thermal" : For MT8365 family of SoCs
- "mediatek,mt8516-thermal", "mediatek,mt2701-thermal : For MT8516 family of SoCs
- reg: Address range of the thermal controller
- interrupts: IRQ for the thermal controller
- clocks, clock-names: Clocks needed for the thermal controller. required
clocks are:
"therm": Main clock needed for register access
"auxadc": The AUXADC clock
- mediatek,auxadc: A phandle to the AUXADC which the thermal controller uses
- mediatek,apmixedsys: A phandle to the APMIXEDSYS controller.
- #thermal-sensor-cells : Should be 0. See Documentation/devicetree/bindings/thermal/thermal-sensor.yaml for a description.
Optional properties:
- resets: Reference to the reset controller controlling the thermal controller.
- nvmem-cells: A phandle to the calibration data provided by a nvmem device. If
unspecified default values shall be used.
- nvmem-cell-names: Should be "calibration-data"
Example:
thermal: thermal@1100b000 {
#thermal-sensor-cells = <1>;
compatible = "mediatek,mt8173-thermal";
reg = <0 0x1100b000 0 0x1000>;
interrupts = <0 70 IRQ_TYPE_LEVEL_LOW>;
clocks = <&pericfg CLK_PERI_THERM>, <&pericfg CLK_PERI_AUXADC>;
clock-names = "therm", "auxadc";
resets = <&pericfg MT8173_PERI_THERM_SW_RST>;
reset-names = "therm";
mediatek,auxadc = <&auxadc>;
mediatek,apmixedsys = <&apmixedsys>;
nvmem-cells = <&thermal_calibration_data>;
nvmem-cell-names = "calibration-data";
};
arch/arm64/boot/dts/mediatek/Makefile
View file @ 76955bc8
......@@ -32,10 +32,16 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-fennel14-sku2.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-juniper-sku16.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-kappa.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-kenzo.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-makomo-sku0.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-makomo-sku1.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-pico.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-pico6.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-willow-sku0.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-willow-sku1.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-kakadu.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-kakadu-sku22.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-katsu-sku32.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-katsu-sku38.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-kodama-sku16.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-kodama-sku272.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-kodama-sku288.dtb
......@@ -44,6 +50,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-krane-sku0.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-krane-sku176.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-pumpkin.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-evb.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8188-evb.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8192-asurada-hayato-r1.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8192-asurada-hayato-r5-sku2.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8192-asurada-spherion-r0.dtb
......
arch/arm64/boot/dts/mediatek/mt6358.dtsi
View file @ 76955bc8
......@@ -8,8 +8,6 @@ &pwrap {
pmic: pmic {
compatible = "mediatek,mt6358";
interrupt-controller;
interrupt-parent = <&pio>;
interrupts = <182 IRQ_TYPE_LEVEL_HIGH>;
#interrupt-cells = <2>;
mt6358codec: mt6358codec {
......@@ -128,7 +126,6 @@ mt6358_vibr_reg: ldo_vibr {
};
mt6358_vrf12_reg: ldo_vrf12 {
compatible = "regulator-fixed";
regulator-name = "vrf12";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
......@@ -136,7 +133,6 @@ mt6358_vrf12_reg: ldo_vrf12 {
};
mt6358_vio18_reg: ldo_vio18 {
compatible = "regulator-fixed";
regulator-name = "vio18";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
......@@ -153,7 +149,6 @@ mt6358_vusb_reg: ldo_vusb {
};
mt6358_vcamio_reg: ldo_vcamio {
compatible = "regulator-fixed";
regulator-name = "vcamio";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
......@@ -168,7 +163,6 @@ mt6358_vcamd_reg: ldo_vcamd {
};
mt6358_vcn18_reg: ldo_vcn18 {
compatible = "regulator-fixed";
regulator-name = "vcn18";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
......@@ -176,7 +170,6 @@ mt6358_vcn18_reg: ldo_vcn18 {
};
mt6358_vfe28_reg: ldo_vfe28 {
compatible = "regulator-fixed";
regulator-name = "vfe28";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
......@@ -193,7 +186,6 @@ mt6358_vsram_proc11_reg: ldo_vsram_proc11 {
};
mt6358_vcn28_reg: ldo_vcn28 {
compatible = "regulator-fixed";
regulator-name = "vcn28";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
......@@ -218,7 +210,6 @@ mt6358_vsram_gpu_reg: ldo_vsram_gpu {
};
mt6358_vxo22_reg: ldo_vxo22 {
compatible = "regulator-fixed";
regulator-name = "vxo22";
regulator-min-microvolt = <2200000>;
regulator-max-microvolt = <2200000>;
......@@ -234,7 +225,6 @@ mt6358_vefuse_reg: ldo_vefuse {
};
mt6358_vaux18_reg: ldo_vaux18 {
compatible = "regulator-fixed";
regulator-name = "vaux18";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
......@@ -249,7 +239,6 @@ mt6358_vmch_reg: ldo_vmch {
};
mt6358_vbif28_reg: ldo_vbif28 {
compatible = "regulator-fixed";
regulator-name = "vbif28";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
......@@ -280,7 +269,6 @@ mt6358_vemc_reg: ldo_vemc {
};
mt6358_vio28_reg: ldo_vio28 {
compatible = "regulator-fixed";
regulator-name = "vio28";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
......@@ -288,7 +276,6 @@ mt6358_vio28_reg: ldo_vio28 {
};
mt6358_va12_reg: ldo_va12 {
compatible = "regulator-fixed";
regulator-name = "va12";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
......@@ -297,22 +284,14 @@ mt6358_va12_reg: ldo_va12 {
};
mt6358_vrf18_reg: ldo_vrf18 {
compatible = "regulator-fixed";
regulator-name = "vrf18";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-enable-ramp-delay = <120>;
};
mt6358_vcn33_bt_reg: ldo_vcn33_bt {
regulator-name = "vcn33_bt";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3500000>;
regulator-enable-ramp-delay = <270>;
};
mt6358_vcn33_wifi_reg: ldo_vcn33_wifi {
regulator-name = "vcn33_wifi";
mt6358_vcn33_reg: ldo_vcn33 {
regulator-name = "vcn33";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3500000>;
regulator-enable-ramp-delay = <270>;
......@@ -340,7 +319,6 @@ mt6358_vldo28_reg: ldo_vldo28 {
};
mt6358_vaud28_reg: ldo_vaud28 {
compatible = "regulator-fixed";
regulator-name = "vaud28";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
......
arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
View file @ 76955bc8
......@@ -153,8 +153,7 @@ switch@0 {
reg = <0>;
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&pio>;
interrupts = <53 IRQ_TYPE_LEVEL_HIGH>;
interrupts-extended = <&pio 53 IRQ_TYPE_LEVEL_HIGH>;
reset-gpios = <&pio 54 0>;
ports {
......
arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts
View file @ 76955bc8
......@@ -203,8 +203,7 @@ switch: switch@31 {
reg = <31>;
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&pio>;
interrupts = <66 IRQ_TYPE_LEVEL_HIGH>;
interrupts-extended = <&pio 66 IRQ_TYPE_LEVEL_HIGH>;
reset-gpios = <&pio 5 GPIO_ACTIVE_HIGH>;
};
};
......
arch/arm64/boot/dts/mediatek/mt8173-elm-hana.dtsi
View file @ 76955bc8
......@@ -13,8 +13,7 @@ &i2c3 {
touchscreen2: touchscreen@34 {
compatible = "melfas,mip4_ts";
reg = <0x34>;
interrupt-parent = <&pio>;
interrupts = <88 IRQ_TYPE_LEVEL_LOW>;
interrupts-extended = <&pio 88 IRQ_TYPE_LEVEL_LOW>;
};
/*
......@@ -26,8 +25,7 @@ touchscreen3: touchscreen@20 {
compatible = "hid-over-i2c";
reg = <0x20>;
hid-descr-addr = <0x0020>;
interrupt-parent = <&pio>;
interrupts = <88 IRQ_TYPE_LEVEL_LOW>;
interrupts-extended = <&pio 88 IRQ_TYPE_LEVEL_LOW>;
};
};
......@@ -39,8 +37,7 @@ &i2c4 {
*/
trackpad2: trackpad@2c {
compatible = "hid-over-i2c";
interrupt-parent = <&pio>;
interrupts = <117 IRQ_TYPE_LEVEL_LOW>;
interrupts-extended = <&pio 117 IRQ_TYPE_LEVEL_LOW>;
reg = <0x2c>;
hid-descr-addr = <0x0020>;
wakeup-source;
......
arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi
View file @ 76955bc8
......@@ -245,8 +245,7 @@ rt5650: audio-codec@1a {
reg = <0x1a>;
avdd-supply = <&mt6397_vgp1_reg>;
cpvdd-supply = <&mt6397_vcama_reg>;
interrupt-parent = <&pio>;
interrupts = <3 IRQ_TYPE_EDGE_BOTH>;
interrupts-extended = <&pio 3 IRQ_TYPE_EDGE_BOTH>;
pinctrl-names = "default";
pinctrl-0 = <&rt5650_irq>;
#sound-dai-cells = <1>;
......@@ -308,8 +307,7 @@ &i2c1 {
da9211: da9211@68 {
compatible = "dlg,da9211";
reg = <0x68>;
interrupt-parent = <&pio>;
interrupts = <15 IRQ_TYPE_LEVEL_LOW>;
interrupts-extended = <&pio 15 IRQ_TYPE_LEVEL_LOW>;
regulators {
da9211_vcpu_reg: BUCKA {
......@@ -353,8 +351,7 @@ &i2c3 {
touchscreen: touchscreen@10 {
compatible = "elan,ekth3500";
reg = <0x10>;
interrupt-parent = <&pio>;
interrupts = <88 IRQ_TYPE_LEVEL_LOW>;
interrupts-extended = <&pio 88 IRQ_TYPE_LEVEL_LOW>;
};
};
......@@ -366,8 +363,7 @@ &i2c4 {
trackpad: trackpad@15 {
compatible = "elan,ekth3000";
interrupt-parent = <&pio>;
interrupts = <117 IRQ_TYPE_LEVEL_LOW>;
interrupts-extended = <&pio 117 IRQ_TYPE_LEVEL_LOW>;
reg = <0x15>;
vcc-supply = <&mt6397_vgp6_reg>;
wakeup-source;
......@@ -439,8 +435,7 @@ &mmc3 {
btmrvl: btmrvl@2 {
compatible = "marvell,sd8897-bt";
reg = <2>;
interrupt-parent = <&pio>;
interrupts = <119 IRQ_TYPE_LEVEL_LOW>;
interrupts-extended = <&pio 119 IRQ_TYPE_LEVEL_LOW>;
marvell,wakeup-pin = /bits/ 16 <0x0d>;
marvell,wakeup-gap-ms = /bits/ 16 <0x64>;
};
......@@ -448,8 +443,7 @@ btmrvl: btmrvl@2 {
mwifiex: mwifiex@1 {
compatible = "marvell,sd8897";
reg = <1>;
interrupt-parent = <&pio>;
interrupts = <38 IRQ_TYPE_LEVEL_LOW>;
interrupts-extended = <&pio 38 IRQ_TYPE_LEVEL_LOW>;
marvell,wakeup-pin = <3>;
};
};
......@@ -933,8 +927,7 @@ pmic: pmic {
compatible = "mediatek,mt6397";
#address-cells = <1>;
#size-cells = <1>;
interrupt-parent = <&pio>;
interrupts = <11 IRQ_TYPE_LEVEL_HIGH>;
interrupts-extended = <&pio 11 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <2>;
......@@ -1160,8 +1153,7 @@ cros_ec: ec@0 {
compatible = "google,cros-ec-spi";
reg = <0x0>;
spi-max-frequency = <12000000>;
interrupt-parent = <&pio>;
interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
interrupts-extended = <&pio 0 IRQ_TYPE_LEVEL_LOW>;
google,cros-ec-spi-msg-delay = <500>;
i2c_tunnel: i2c-tunnel0 {
......
arch/arm64/boot/dts/mediatek/mt8173-evb.dts
View file @ 76955bc8
......@@ -303,8 +303,7 @@ &pwrap {
pmic: pmic {
compatible = "mediatek,mt6397";
interrupt-parent = <&pio>;
interrupts = <11 IRQ_TYPE_LEVEL_HIGH>;
interrupts-extended = <&pio 11 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <2>;
......
arch/arm64/boot/dts/mediatek/mt8173.dtsi
View file @ 76955bc8
......@@ -1368,10 +1368,9 @@ vdecsys: clock-controller@16000000 {
#clock-cells = <1>;
};
vcodec_dec: vcodec@16000000 {
vcodec_dec: vcodec@16020000 {
compatible = "mediatek,mt8173-vcodec-dec";
reg = <0 0x16000000 0 0x100>, /* VDEC_SYS */
<0 0x16020000 0 0x1000>, /* VDEC_MISC */
reg = <0 0x16020000 0 0x1000>, /* VDEC_MISC */
<0 0x16021000 0 0x800>, /* VDEC_LD */
<0 0x16021800 0 0x800>, /* VDEC_TOP */
<0 0x16022000 0 0x1000>, /* VDEC_CM */
......@@ -1382,6 +1381,8 @@ vcodec_dec: vcodec@16000000 {
<0 0x16027000 0 0x800>, /* VDEC_HWQ */
<0 0x16027800 0 0x800>, /* VDEC_HWB */
<0 0x16028400 0 0x400>; /* VDEC_HWG */
reg-names = "misc", "ld", "top", "cm", "ad", "av", "pp",
"hwd", "hwq", "hwb", "hwg";
interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_LOW>;
iommus = <&iommu M4U_PORT_HW_VDEC_MC_EXT>,
<&iommu M4U_PORT_HW_VDEC_PP_EXT>,
......@@ -1392,6 +1393,7 @@ vcodec_dec: vcodec@16000000 {
<&iommu M4U_PORT_HW_VDEC_VLD_EXT>,
<&iommu M4U_PORT_HW_VDEC_VLD2_EXT>;
mediatek,vpu = <&vpu>;
mediatek,vdecsys = <&vdecsys>;
power-domains = <&spm MT8173_POWER_DOMAIN_VDEC>;
clocks = <&apmixedsys CLK_APMIXED_VCODECPLL>,
<&topckgen CLK_TOP_UNIVPLL_D2>,
......
arch/arm64/boot/dts/mediatek/mt8183-evb.dts
View file @ 76955bc8
......@@ -381,6 +381,10 @@ pins_pwm {
};
};
&pmic {
interrupts-extended = <&pio 182 IRQ_TYPE_LEVEL_HIGH>;
};
&mfg {
domain-supply = <&mt6358_vgpu_reg>;
};
......
arch/arm64/boot/dts/mediatek/mt8183-kukui-audio-da7219.dtsi
View file @ 76955bc8
......@@ -11,8 +11,7 @@ da7219: da7219@1a {
pinctrl-0 = <&da7219_pins>;
compatible = "dlg,da7219";
reg = <0x1a>;
interrupt-parent = <&pio>;
interrupts = <165 IRQ_TYPE_LEVEL_LOW 165 0>;
interrupts-extended = <&pio 165 IRQ_TYPE_LEVEL_LOW>;
dlg,micbias-lvl = <2600>;
dlg,mic-amp-in-sel = "diff";
......
arch/arm64/boot/dts/mediatek/mt8183-kukui-audio-ts3a227e.dtsi
View file @ 76955bc8
......@@ -11,8 +11,7 @@ ts3a227e: ts3a227e@3b {
pinctrl-0 = <&ts3a227e_pins>;
compatible = "ti,ts3a227e";
reg = <0x3b>;
interrupt-parent = <&pio>;
interrupts = <157 IRQ_TYPE_LEVEL_LOW>;
interrupts-extended = <&pio 157 IRQ_TYPE_LEVEL_LOW>;
status = "okay";
};
};
......
arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-damu.dts
View file @ 76955bc8
......@@ -18,8 +18,7 @@ &touchscreen {
compatible = "hid-over-i2c";
reg = <0x10>;
interrupt-parent = <&pio>;
interrupts = <155 IRQ_TYPE_LEVEL_LOW>;
interrupts-extended = <&pio 155 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&touchscreen_pins>;
......
arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel-sku1.dts
View file @ 76955bc8
......@@ -30,8 +30,7 @@ &touchscreen {
compatible = "hid-over-i2c";
reg = <0x10>;
interrupt-parent = <&pio>;
interrupts = <155 IRQ_TYPE_LEVEL_LOW>;
interrupts-extended = <&pio 155 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&touchscreen_pins>;
......
arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel-sku6.dts
View file @ 76955bc8
......@@ -17,8 +17,7 @@ &touchscreen {
compatible = "hid-over-i2c";
reg = <0x10>;
interrupt-parent = <&pio>;
interrupts = <155 IRQ_TYPE_LEVEL_LOW>;
interrupts-extended = <&pio 155 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&touchscreen_pins>;
......
arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel-sku7.dts
View file @ 76955bc8
......@@ -17,8 +17,7 @@ &touchscreen {
compatible = "hid-over-i2c";
reg = <0x10>;
interrupt-parent = <&pio>;
interrupts = <155 IRQ_TYPE_LEVEL_LOW>;
interrupts-extended = <&pio 155 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&touchscreen_pins>;
......
arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-makomo-sku0.dts 0 → 100644
View file @ 76955bc8
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright 2023 Google LLC
*/
/dts-v1/;
#include "mt8183-kukui-jacuzzi-fennel.dtsi"
#include "mt8183-kukui-audio-da7219-rt1015p.dtsi"
/ {
model = "Google makomo sku0 board";
chassis-type = "laptop";
compatible = "google,makomo-sku0", "google,makomo", "mediatek,mt8183";
};
&qca_wifi {
qcom,ath10k-calibration-variant = "GO_FENNEL14";
};
&mmc1_pins_uhs {
pins-clk {
drive-strength = <MTK_DRIVE_6mA>;
};
};
arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-makomo-sku1.dts 0 → 100644
View file @ 76955bc8
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright 2023 Google LLC
*/
/dts-v1/;
#include "mt8183-kukui-jacuzzi-fennel.dtsi"
#include "mt8183-kukui-audio-ts3a227e-rt1015p.dtsi"
/ {
model = "Google makomo sku1 board";
chassis-type = "laptop";
compatible = "google,makomo-sku1", "google,makomo", "mediatek,mt8183";
};
&qca_wifi {
qcom,ath10k-calibration-variant = "GO_FENNEL14";
};
&mmc1_pins_uhs {
pins-clk {
drive-strength = <MTK_DRIVE_6mA>;
};
};
arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-pico.dts 0 → 100644
View file @ 76955bc8
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright 2023 Google LLC
*/
/dts-v1/;
#include "mt8183-kukui-jacuzzi.dtsi"
#include "mt8183-kukui-audio-ts3a227e-max98357a.dtsi"
/ {
model = "Google pico board";
chassis-type = "convertible";
compatible = "google,pico-sku1", "google,pico", "mediatek,mt8183";
};
&i2c_tunnel {
google,remote-bus = <0>;
};
&i2c2 {
i2c-scl-internal-delay-ns = <25000>;
trackpad@2c {
compatible = "hid-over-i2c";
reg = <0x2c>;
hid-descr-addr = <0x20>;
pinctrl-names = "default";
pinctrl-0 = <&trackpad_pins>;
interrupts-extended = <&pio 7 IRQ_TYPE_LEVEL_LOW>;
wakeup-source;
};
};
arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-pico6.dts 0 → 100644
View file @ 76955bc8
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright 2023 Google LLC
*/
/dts-v1/;
#include "mt8183-kukui-jacuzzi.dtsi"
#include "mt8183-kukui-audio-ts3a227e-max98357a.dtsi"
/ {
model = "Google pico6 board";
chassis-type = "convertible";
compatible = "google,pico-sku2", "google,pico", "mediatek,mt8183";
bt_wakeup: bt-wakeup {
compatible = "gpio-keys";
pinctrl-names = "default";
pinctrl-0 = <&bt_pins_wakeup>;
wobt {
label = "Wake on BT";
gpios = <&pio 42 GPIO_ACTIVE_HIGH>;
linux,code = <KEY_WAKEUP>;
wakeup-source;
};
};
};
&i2c_tunnel {
google,remote-bus = <0>;
};
&i2c2 {
i2c-scl-internal-delay-ns = <25000>;
trackpad@2c {
compatible = "hid-over-i2c";
reg = <0x2c>;
hid-descr-addr = <0x20>;
pinctrl-names = "default";
pinctrl-0 = <&trackpad_pins>;
interrupts-extended = <&pio 7 IRQ_TYPE_LEVEL_LOW>;
wakeup-source;
};
};
&wifi_wakeup {
wowlan {
gpios = <&pio 113 GPIO_ACTIVE_LOW>;
};
};
&wifi_pwrseq {
post-power-on-delay-ms = <50>;
/* Toggle WIFI_ENABLE to reset the chip. */
reset-gpios = <&pio 8 GPIO_ACTIVE_LOW>;
};
&wifi_pins_pwrseq {
pins-wifi-enable {
pinmux = <PINMUX_GPIO8__FUNC_GPIO8>;
};
};
&mmc1_pins_default {
pins-cmd-dat {
drive-strength = <MTK_DRIVE_6mA>;
};
pins-clk {
drive-strength = <MTK_DRIVE_6mA>;
};
};
&mmc1_pins_uhs {
pins-clk {
drive-strength = <MTK_DRIVE_6mA>;
};
};
&mmc1 {
bt_reset: bt-reset {
compatible = "mediatek,mt7921s-bluetooth";
pinctrl-names = "default";
pinctrl-0 = <&bt_pins_reset>;
reset-gpios = <&pio 120 GPIO_ACTIVE_LOW>;
};
};
&pio {
bt_pins_wakeup: bt-pins-wakeup {
piins-bt-wakeup {
pinmux = <PINMUX_GPIO42__FUNC_GPIO42>;
input-enable;
};
};
bt_pins_reset: bt-pins-reset {
pins-bt-reset {
pinmux = <PINMUX_GPIO120__FUNC_GPIO120>;
output-high;
};
};
};
/delete-node/ &bluetooth;
/delete-node/ &bt_pins;
arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi.dtsi
View file @ 76955bc8
......@@ -147,7 +147,6 @@ anx_bridge: anx7625@58 {
reg = <0x58>;
pinctrl-names = "default";
pinctrl-0 = <&anx7625_pins>;
panel_flags = <1>;
enable-gpios = <&pio 45 GPIO_ACTIVE_HIGH>;
reset-gpios = <&pio 73 GPIO_ACTIVE_HIGH>;
vdd10-supply = <&pp1200_mipibrdg>;
......
arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu-sku22.dts
View file @ 76955bc8
......@@ -14,6 +14,24 @@ / {
"google,kakadu", "mediatek,mt8183";
};
&i2c0 {
touchscreen: touchscreen@10 {
compatible = "hid-over-i2c";
reg = <0x10>;
pinctrl-names = "default";
pinctrl-0 = <&open_touch>;
interrupts-extended = <&pio 155 IRQ_TYPE_EDGE_FALLING>;
post-power-on-delay-ms = <10>;
hid-descr-addr = <0x0001>;
};
};
&panel {
compatible = "boe,tv105wum-nw0";
};
&sound {
compatible = "mediatek,mt8183_mt6358_ts3a227_rt1015p";
};
......
arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu.dts
View file @ 76955bc8
......@@ -13,3 +13,21 @@ / {
compatible = "google,kakadu-rev3", "google,kakadu-rev2",
"google,kakadu", "mediatek,mt8183";
};
&i2c0 {
touchscreen: touchscreen@10 {
compatible = "hid-over-i2c";
reg = <0x10>;
pinctrl-names = "default";
pinctrl-0 = <&open_touch>;
interrupts-extended = <&pio 155 IRQ_TYPE_EDGE_FALLING>;
post-power-on-delay-ms = <10>;
hid-descr-addr = <0x0001>;
};
};
&panel {
compatible = "boe,tv105wum-nw0";
};
arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu.dtsi
View file @ 76955bc8
......@@ -63,19 +63,6 @@ &bluetooth {
&i2c0 {
status = "okay";
touchscreen: touchscreen@10 {
compatible = "hid-over-i2c";
reg = <0x10>;
pinctrl-names = "default";
pinctrl-0 = <&open_touch>;
interrupt-parent = <&pio>;
interrupts = <155 IRQ_TYPE_EDGE_FALLING>;
post-power-on-delay-ms = <10>;
hid-descr-addr = <0x0001>;
};
};
&mt6358_vcama2_reg {
......@@ -384,5 +371,5 @@ &qca_wifi {
&panel {
status = "okay";
compatible = "boe,tv105wum-nw0";
/* compatible will be set in board dts */
};
arch/arm64/boot/dts/mediatek/mt8183-kukui-katsu-sku32.dts 0 → 100644
View file @ 76955bc8
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright 2023 Google LLC
*/
/dts-v1/;
#include "mt8183-kukui-kakadu.dtsi"
#include "mt8183-kukui-audio-da7219-rt1015p.dtsi"
/ {
model = "Google katsu board";
chassis-type = "tablet";
compatible = "google,katsu-sku32", "google,katsu", "mediatek,mt8183";
};
&i2c0 {
touchscreen1: touchscreen@5d {
compatible = "goodix,gt7375p";
reg = <0x5d>;
pinctrl-names = "default";
pinctrl-0 = <&open_touch>;
interrupts-extended = <&pio 155 IRQ_TYPE_LEVEL_LOW>;
reset-gpios = <&pio 156 GPIO_ACTIVE_LOW>;
vdd-supply = <&lcd_pp3300>;
};
};
&panel {
compatible = "starry,2081101qfh032011-53g";
};
&qca_wifi {
qcom,ath10k-calibration-variant = "GO_KATSU";
};
arch/arm64/boot/dts/mediatek/mt8183-kukui-katsu-sku38.dts 0 → 100644
View file @ 76955bc8
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright 2023 Google LLC
*/
/dts-v1/;
#include "mt8183-kukui-kakadu.dtsi"
#include "mt8183-kukui-audio-rt1015p.dtsi"
/ {
model = "Google katsu sku38 board";
chassis-type = "tablet";
compatible = "google,katsu-sku38", "google,katsu", "mediatek,mt8183";
};
&i2c0 {
touchscreen1: touchscreen@5d {
compatible = "goodix,gt7375p";
reg = <0x5d>;
pinctrl-names = "default";
pinctrl-0 = <&open_touch>;
interrupts-extended = <&pio 155 IRQ_TYPE_LEVEL_LOW>;
reset-gpios = <&pio 156 GPIO_ACTIVE_LOW>;
vdd-supply = <&lcd_pp3300>;
};
};
&panel {
compatible = "starry,2081101qfh032011-53g";
};
&qca_wifi {
qcom,ath10k-calibration-variant = "GO_KATSU";
};
&sound {
compatible = "mediatek,mt8183_mt6358_ts3a227_rt1015p";
};
arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama.dtsi
View file @ 76955bc8
......@@ -48,8 +48,7 @@ &i2c0 {
touchscreen: touchscreen@10 {
compatible = "hid-over-i2c";
reg = <0x10>;
interrupt-parent = <&pio>;
interrupts = <155 IRQ_TYPE_LEVEL_LOW>;
interrupts-extended = <&pio 155 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&touch_default>;
......
arch/arm64/boot/dts/mediatek/mt8183-kukui-krane.dtsi
View file @ 76955bc8
......@@ -54,8 +54,7 @@ touchscreen4: touchscreen@5d {
pinctrl-names = "default";
pinctrl-0 = <&open_touch>;
interrupt-parent = <&pio>;
interrupts = <155 IRQ_TYPE_EDGE_FALLING>;
interrupts-extended = <&pio 155 IRQ_TYPE_EDGE_FALLING>;
post-power-on-delay-ms = <10>;
hid-descr-addr = <0x0001>;
......
arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi
View file @ 76955bc8
......@@ -846,6 +846,10 @@ pins_wifi_wakeup {
};
};
&pmic {
interrupts-extended = <&pio 182 IRQ_TYPE_LEVEL_HIGH>;
};
&pwm0 {
status = "okay";
pinctrl-names = "default";
......@@ -890,8 +894,7 @@ cr50@0 {
spi-max-frequency = <1000000>;
pinctrl-names = "default";
pinctrl-0 = <&h1_int_od_l>;
interrupt-parent = <&pio>;
interrupts = <153 IRQ_TYPE_EDGE_RISING>;
interrupts-extended = <&pio 153 IRQ_TYPE_EDGE_RISING>;
};
};
......@@ -918,8 +921,7 @@ cros_ec: cros-ec@0 {
compatible = "google,cros-ec-spi";
reg = <0>;
spi-max-frequency = <3000000>;
interrupt-parent = <&pio>;
interrupts = <151 IRQ_TYPE_LEVEL_LOW>;
interrupts-extended = <&pio 151 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&ec_ap_int_odl>;
......
arch/arm64/boot/dts/mediatek/mt8183-pumpkin.dts
View file @ 76955bc8
......@@ -370,6 +370,10 @@ pins_clk {
};
};
&pmic {
interrupts-extended = <&pio 182 IRQ_TYPE_LEVEL_HIGH>;
};
&mfg {
domain-supply = <&mt6358_vgpu_reg>;
};
......
arch/arm64/boot/dts/mediatek/mt8183.dtsi
View file @ 76955bc8
......@@ -1183,22 +1183,10 @@ spi0: spi@1100a000 {
status = "disabled";
};
svs: svs@1100b000 {
compatible = "mediatek,mt8183-svs";
reg = <0 0x1100b000 0 0x1000>;
interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_LOW>;
clocks = <&infracfg CLK_INFRA_THERM>;
clock-names = "main";
nvmem-cells = <&svs_calibration>,
<&thermal_calibration>;
nvmem-cell-names = "svs-calibration-data",
"t-calibration-data";
};
thermal: thermal@1100b000 {
#thermal-sensor-cells = <1>;
compatible = "mediatek,mt8183-thermal";
reg = <0 0x1100b000 0 0x1000>;
reg = <0 0x1100b000 0 0xc00>;
clocks = <&infracfg CLK_INFRA_THERM>,
<&infracfg CLK_INFRA_AUXADC>;
clock-names = "therm", "auxadc";
......@@ -1210,6 +1198,18 @@ thermal: thermal@1100b000 {
nvmem-cell-names = "calibration-data";
};
svs: svs@1100bc00 {
compatible = "mediatek,mt8183-svs";
reg = <0 0x1100bc00 0 0x400>;
interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_LOW>;
clocks = <&infracfg CLK_INFRA_THERM>;
clock-names = "main";
nvmem-cells = <&svs_calibration>,
<&thermal_calibration>;
nvmem-cell-names = "svs-calibration-data",
"t-calibration-data";
};
thermal_zones: thermal-zones {
cpu_thermal: cpu-thermal {
polling-delay-passive = <100>;
......@@ -1781,7 +1781,7 @@ mmsys: syscon@14000000 {
mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
};
mdp3-rdma0@14001000 {
dma-controller0@14001000 {
compatible = "mediatek,mt8183-mdp3-rdma";
reg = <0 0x14001000 0 0x1000>;
mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x1000 0x1000>;
......@@ -1793,6 +1793,7 @@ mdp3-rdma0@14001000 {
iommus = <&iommu M4U_PORT_MDP_RDMA0>;
mboxes = <&gce 20 CMDQ_THR_PRIO_LOWEST 0>,
<&gce 21 CMDQ_THR_PRIO_LOWEST 0>;
#dma-cells = <1>;
};
mdp3-rsz0@14003000 {
......@@ -1813,7 +1814,7 @@ mdp3-rsz1@14004000 {
clocks = <&mmsys CLK_MM_MDP_RSZ1>;
};
mdp3-wrot0@14005000 {
dma-controller@14005000 {
compatible = "mediatek,mt8183-mdp3-wrot";
reg = <0 0x14005000 0 0x1000>;
mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x5000 0x1000>;
......@@ -1822,6 +1823,7 @@ mdp3-wrot0@14005000 {
power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
clocks = <&mmsys CLK_MM_MDP_WROT0>;
iommus = <&iommu M4U_PORT_MDP_WROT0>;
#dma-cells = <1>;
};
mdp3-wdma@14006000 {
......@@ -2019,6 +2021,36 @@ vdecsys: syscon@16000000 {
#clock-cells = <1>;
};
vcodec_dec: video-codec@16020000 {
compatible = "mediatek,mt8183-vcodec-dec";
reg = <0 0x16020000 0 0x1000>, /* VDEC_MISC */
<0 0x16021000 0 0x800>, /* VDEC_VLD */
<0 0x16021800 0 0x800>, /* VDEC_TOP */
<0 0x16022000 0 0x1000>, /* VDEC_MC */
<0 0x16023000 0 0x1000>, /* VDEC_AVCVLD */
<0 0x16024000 0 0x1000>, /* VDEC_AVCMV */
<0 0x16025000 0 0x1000>, /* VDEC_PP */
<0 0x16026800 0 0x800>, /* VP8_VD */
<0 0x16027000 0 0x800>, /* VP6_VD */
<0 0x16027800 0 0x800>, /* VP8_VL */
<0 0x16028400 0 0x400>; /* VP9_VD */
reg-names = "misc", "ld", "top", "cm", "ad", "av", "pp",
"hwd", "hwq", "hwb", "hwg";
interrupts = <GIC_SPI 250 IRQ_TYPE_LEVEL_LOW>;
iommus = <&iommu M4U_PORT_HW_VDEC_MC_EXT>,
<&iommu M4U_PORT_HW_VDEC_PP_EXT>,
<&iommu M4U_PORT_HW_VDEC_VLD_EXT>,
<&iommu M4U_PORT_HW_VDEC_AVC_MV_EXT>,
<&iommu M4U_PORT_HW_VDEC_PRED_RD_EXT>,
<&iommu M4U_PORT_HW_VDEC_PRED_WR_EXT>,
<&iommu M4U_PORT_HW_VDEC_PPWRAP_EXT>;
mediatek,scp = <&scp>;
mediatek,vdecsys = <&vdecsys>;
power-domains = <&spm MT8183_POWER_DOMAIN_VDEC>;
clocks = <&vdecsys CLK_VDEC_VDEC>;
clock-names = "vdec";
};
larb1: larb@16010000 {
compatible = "mediatek,mt8183-smi-larb";
reg = <0 0x16010000 0 0x1000>;
......
arch/arm64/boot/dts/mediatek/mt8186.dtsi
View file @ 76955bc8
......@@ -22,7 +22,7 @@ / {
aliases {
ovl0 = &ovl0;
ovl_2l0 = &ovl_2l0;
ovl-2l0 = &ovl_2l0;
rdma0 = &rdma0;
rdma1 = &rdma1;
};
......@@ -1148,14 +1148,14 @@ adsp: adsp@10680000 {
status = "disabled";
};
adsp_mailbox0: mailbox@10686000 {
adsp_mailbox0: mailbox@10686100 {
compatible = "mediatek,mt8186-adsp-mbox";
#mbox-cells = <0>;
reg = <0 0x10686100 0 0x1000>;
interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH 0>;
};
adsp_mailbox1: mailbox@10687000 {
adsp_mailbox1: mailbox@10687100 {
compatible = "mediatek,mt8186-adsp-mbox";
#mbox-cells = <0>;
reg = <0 0x10687100 0 0x1000>;
......
arch/arm64/boot/dts/mediatek/mt8188-evb.dts 0 → 100644
View file @ 76955bc8
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright (C) 2023 MediaTek Inc.
*/
/dts-v1/;
#include "mt8188.dtsi"
#include "mt6359.dtsi"
/ {
model = "MediaTek MT8188 evaluation board";
compatible = "mediatek,mt8188-evb", "mediatek,mt8188";
aliases {
serial0 = &uart0;
i2c0 = &i2c0;
i2c1 = &i2c1;
i2c2 = &i2c2;
i2c3 = &i2c3;
i2c4 = &i2c4;
i2c5 = &i2c5;
i2c6 = &i2c6;
mmc0 = &mmc0;
};
chosen: chosen {
stdout-path = "serial0:115200n8";
};
memory@40000000 {
device_type = "memory";
reg = <0 0x40000000 0 0x80000000>;
};
reserved_memory: reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
scp_mem_reserved: memory@50000000 {
compatible = "shared-dma-pool";
reg = <0 0x50000000 0 0x2900000>;
no-map;
};
};
};
&auxadc {
status = "okay";
};
&i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins>;
clock-frequency = <400000>;
status = "okay";
};
&i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&i2c1_pins>;
clock-frequency = <400000>;
status = "okay";
};
&i2c2 {
pinctrl-names = "default";
pinctrl-0 = <&i2c2_pins>;
clock-frequency = <400000>;
status = "okay";
};
&i2c3 {
pinctrl-names = "default";
pinctrl-0 = <&i2c3_pins>;
clock-frequency = <400000>;
status = "okay";
};
&i2c4 {
pinctrl-names = "default";
pinctrl-0 = <&i2c4_pins>;
clock-frequency = <400000>;
status = "okay";
};
&i2c5 {
pinctrl-names = "default";
pinctrl-0 = <&i2c5_pins>;
clock-frequency = <400000>;
status = "okay";
};
&i2c6 {
pinctrl-names = "default";
pinctrl-0 = <&i2c6_pins>;
clock-frequency = <400000>;
status = "okay";
};
&mmc0 {
bus-width = <8>;
hs400-ds-delay = <0x1481b>;
max-frequency = <200000000>;
cap-mmc-highspeed;
mmc-hs200-1_8v;
mmc-hs400-1_8v;
supports-cqe;
cap-mmc-hw-reset;
no-sdio;
no-sd;
non-removable;
vmmc-supply = <&mt6359_vemc_1_ldo_reg>;
vqmmc-supply = <&mt6359_vufs_ldo_reg>;
pinctrl-names = "default", "state_uhs";
pinctrl-0 = <&mmc0_default_pins>;
pinctrl-1 = <&mmc0_uhs_pins>;
status = "okay";
};
&mt6359_vcore_buck_reg {
regulator-always-on;
};
&mt6359_vgpu11_buck_reg {
regulator-always-on;
};
&mt6359_vpu_buck_reg {
regulator-always-on;
};
&mt6359_vrf12_ldo_reg {
regulator-always-on;
};
&nor_flash {
pinctrl-names = "default";
pinctrl-0 = <&nor_pins_default>;
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <52000000>;
};
};
&pio {
adsp_uart_pins: adsp-uart-pins {
pins-tx-rx {
pinmux = <PINMUX_GPIO35__FUNC_O_ADSP_UTXD0>,
<PINMUX_GPIO36__FUNC_I1_ADSP_URXD0>;
};
};
i2c0_pins: i2c0-pins {
pins-bus {
pinmux = <PINMUX_GPIO56__FUNC_B1_SDA0>,
<PINMUX_GPIO55__FUNC_B1_SCL0>;
bias-pull-up = <MTK_PULL_SET_RSEL_011>;
};
};
i2c1_pins: i2c1-pins {
pins-bus {
pinmux = <PINMUX_GPIO58__FUNC_B1_SDA1>,
<PINMUX_GPIO57__FUNC_B1_SCL1>;
bias-pull-up = <MTK_PULL_SET_RSEL_011>;
};
};
i2c2_pins: i2c2-pins {
pins-bus {
pinmux = <PINMUX_GPIO60__FUNC_B1_SDA2>,
<PINMUX_GPIO59__FUNC_B1_SCL2>;
bias-pull-up = <MTK_PULL_SET_RSEL_011>;
};
};
i2c3_pins: i2c3-pins {
pins-bus {
pinmux = <PINMUX_GPIO62__FUNC_B1_SDA3>,
<PINMUX_GPIO61__FUNC_B1_SCL3>;
bias-pull-up = <MTK_PULL_SET_RSEL_011>;
};
};
i2c4_pins: i2c4-pins {
pins-bus {
pinmux = <PINMUX_GPIO64__FUNC_B1_SDA4>,
<PINMUX_GPIO63__FUNC_B1_SCL4>;
bias-pull-up = <MTK_PULL_SET_RSEL_011>;
};
};
i2c5_pins: i2c5-pins {
pins-bus {
pinmux = <PINMUX_GPIO66__FUNC_B1_SDA5>,
<PINMUX_GPIO65__FUNC_B1_SCL5>;
bias-pull-up = <MTK_PULL_SET_RSEL_011>;
};
};
i2c6_pins: i2c6-pins {
pins-bus {
pinmux = <PINMUX_GPIO68__FUNC_B1_SDA6>,
<PINMUX_GPIO67__FUNC_B1_SCL6>;
bias-pull-up = <MTK_PULL_SET_RSEL_011>;
};
};
mmc0_default_pins: mmc0-default-pins {
pins-cmd-dat {
pinmux = <PINMUX_GPIO161__FUNC_B1_MSDC0_DAT0>,
<PINMUX_GPIO160__FUNC_B1_MSDC0_DAT1>,
<PINMUX_GPIO159__FUNC_B1_MSDC0_DAT2>,
<PINMUX_GPIO158__FUNC_B1_MSDC0_DAT3>,
<PINMUX_GPIO154__FUNC_B1_MSDC0_DAT4>,
<PINMUX_GPIO153__FUNC_B1_MSDC0_DAT5>,
<PINMUX_GPIO152__FUNC_B1_MSDC0_DAT6>,
<PINMUX_GPIO151__FUNC_B1_MSDC0_DAT7>,
<PINMUX_GPIO156__FUNC_B1_MSDC0_CMD>;
input-enable;
drive-strength = <6>;
bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
};
pins-clk {
pinmux = <PINMUX_GPIO157__FUNC_B1_MSDC0_CLK>;
drive-strength = <6>;
bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
};
pins-rst {
pinmux = <PINMUX_GPIO155__FUNC_O_MSDC0_RSTB>;
drive-strength = <6>;
bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
};
};
mmc0_uhs_pins: mmc0-uhs-pins {
pins-cmd-dat {
pinmux = <PINMUX_GPIO161__FUNC_B1_MSDC0_DAT0>,
<PINMUX_GPIO160__FUNC_B1_MSDC0_DAT1>,
<PINMUX_GPIO159__FUNC_B1_MSDC0_DAT2>,
<PINMUX_GPIO158__FUNC_B1_MSDC0_DAT3>,
<PINMUX_GPIO154__FUNC_B1_MSDC0_DAT4>,
<PINMUX_GPIO153__FUNC_B1_MSDC0_DAT5>,
<PINMUX_GPIO152__FUNC_B1_MSDC0_DAT6>,
<PINMUX_GPIO151__FUNC_B1_MSDC0_DAT7>,
<PINMUX_GPIO156__FUNC_B1_MSDC0_CMD>;
input-enable;
drive-strength = <8>;
bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
};
pins-clk-ds {
pinmux = <PINMUX_GPIO157__FUNC_B1_MSDC0_CLK>,
<PINMUX_GPIO162__FUNC_B0_MSDC0_DSL>;
drive-strength = <8>;
bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
};
pins-rst {
pinmux = <PINMUX_GPIO155__FUNC_O_MSDC0_RSTB>;
drive-strength = <8>;
bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
};
};
nor_pins_default: nor-pins {
pins-io-ck {
pinmux = <PINMUX_GPIO127__FUNC_B0_SPINOR_IO0>,
<PINMUX_GPIO125__FUNC_O_SPINOR_CK>,
<PINMUX_GPIO128__FUNC_B0_SPINOR_IO1>;
bias-pull-down;
};
pins-io-cs {
pinmux = <PINMUX_GPIO126__FUNC_O_SPINOR_CS>,
<PINMUX_GPIO129__FUNC_B0_SPINOR_IO2>,
<PINMUX_GPIO130__FUNC_B0_SPINOR_IO3>;
bias-pull-up;
};
};
spi0_pins: spi0-pins {
pins-spi {
pinmux = <PINMUX_GPIO69__FUNC_O_SPIM0_CSB>,
<PINMUX_GPIO70__FUNC_O_SPIM0_CLK>,
<PINMUX_GPIO71__FUNC_B0_SPIM0_MOSI>,
<PINMUX_GPIO72__FUNC_B0_SPIM0_MISO>;
bias-disable;
};
};
spi1_pins: spi1-pins {
pins-spi {
pinmux = <PINMUX_GPIO75__FUNC_O_SPIM1_CSB>,
<PINMUX_GPIO76__FUNC_O_SPIM1_CLK>,
<PINMUX_GPIO77__FUNC_B0_SPIM1_MOSI>,
<PINMUX_GPIO78__FUNC_B0_SPIM1_MISO>;
bias-disable;
};
};
spi2_pins: spi2-pins {
pins-spi {
pinmux = <PINMUX_GPIO79__FUNC_O_SPIM2_CSB>,
<PINMUX_GPIO80__FUNC_O_SPIM2_CLK>,
<PINMUX_GPIO81__FUNC_B0_SPIM2_MOSI>,
<PINMUX_GPIO82__FUNC_B0_SPIM2_MISO>;
bias-disable;
};
};
uart0_pins: uart0-pins {
pins-rx-tx {
pinmux = <PINMUX_GPIO31__FUNC_O_UTXD0>,
<PINMUX_GPIO32__FUNC_I1_URXD0>;
bias-pull-up;
};
};
};
&pmic {
interrupts-extended = <&pio 222 IRQ_TYPE_LEVEL_HIGH>;
};
&scp {
memory-region = <&scp_mem_reserved>;
status = "okay";
};
&spi0 {
pinctrl-names = "default";
pinctrl-0 = <&spi0_pins>;
status = "okay";
};
&spi1 {
pinctrl-names = "default";
pinctrl-0 = <&spi1_pins>;
status = "okay";
};
&spi2 {
pinctrl-names = "default";
pinctrl-0 = <&spi2_pins>;
status = "okay";
};
&u3phy0 {
status = "okay";
};
&u3phy1 {
status = "okay";
};
&u3phy2 {
status = "okay";
};
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins>;
status = "okay";
};
&xhci0 {
status = "okay";
};
&xhci1 {
status = "okay";
};
&xhci2 {
status = "okay";
};
arch/arm64/boot/dts/mediatek/mt8188.dtsi 0 → 100644
View file @ 76955bc8
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arch/arm64/boot/dts/mediatek/mt8192.dtsi
View file @ 76955bc8
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arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi
View file @ 76955bc8
......@@ -127,6 +127,77 @@ ppvar_sys: regulator-ppvar-sys {
regulator-boot-on;
};
/* Murata NCP03WF104F05RL */
tboard_thermistor1: thermal-sensor-t1 {
compatible = "generic-adc-thermal";
#thermal-sensor-cells = <0>;
io-channels = <&auxadc 0>;
io-channel-names = "sensor-channel";
temperature-lookup-table = < (-10000) 1553
(-5000) 1485
0 1406
5000 1317
10000 1219
15000 1115
20000 1007
25000 900
30000 796
35000 697
40000 605
45000 523
50000 449
55000 384
60000 327
65000 279
70000 237
75000 202
80000 172
85000 147
90000 125
95000 107
100000 92
105000 79
110000 68
115000 59
120000 51
125000 44>;
};
tboard_thermistor2: thermal-sensor-t2 {
compatible = "generic-adc-thermal";
#thermal-sensor-cells = <0>;
io-channels = <&auxadc 1>;
io-channel-names = "sensor-channel";
temperature-lookup-table = < (-10000) 1553
(-5000) 1485
0 1406
5000 1317
10000 1219
15000 1115
20000 1007
25000 900
30000 796
35000 697
40000 605
45000 523
50000 449
55000 384
60000 327
65000 279
70000 237
75000 202
80000 172
85000 147
90000 125
95000 107
100000 92
105000 79
110000 68
115000 59
120000 51
125000 44>;
};
usb_vbus: regulator-5v0-usb-vbus {
compatible = "regulator-fixed";
regulator-name = "usb-vbus";
......@@ -189,6 +260,10 @@ &afe {
memory-region = <&afe_mem>;
};
&auxadc {
status = "okay";
};
&dp_intf0 {
status = "okay";
......@@ -401,6 +476,14 @@ pmic@34 {
};
};
&mfg0 {
domain-supply = <&mt6315_7_vbuck1>;
};
&mfg1 {
domain-supply = <&mt6359_vsram_others_ldo_reg>;
};
&mmc0 {
status = "okay";
......@@ -471,7 +554,6 @@ &mt6359_vrf12_ldo_reg {
/* for GPU SRAM */
&mt6359_vsram_others_ldo_reg {
regulator-always-on;
regulator-min-microvolt = <750000>;
regulator-max-microvolt = <750000>;
};
......@@ -1154,7 +1236,36 @@ mt6315_7_vbuck1: vbuck1 {
regulator-enable-ramp-delay = <256>;
regulator-ramp-delay = <6250>;
regulator-allowed-modes = <0 1 2>;
regulator-always-on;
};
};
};
};
&thermal_zones {
soc-area-thermal {
polling-delay = <1000>;
polling-delay-passive = <250>;
thermal-sensors = <&tboard_thermistor1>;
trips {
trip-crit {
temperature = <84000>;
hysteresis = <1000>;
type = "critical";
};
};
};
pmic-area-thermal {
polling-delay = <1000>;
polling-delay-passive = <0>;
thermal-sensors = <&tboard_thermistor2>;
trips {
trip-crit {
temperature = <84000>;
hysteresis = <1000>;
type = "critical";
};
};
};
......
arch/arm64/boot/dts/mediatek/mt8195.dtsi
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arch/arm64/boot/dts/mediatek/mt8395-genio-1200-evk.dts
View file @ 76955bc8
......@@ -210,8 +210,7 @@ &i2c1 {
touchscreen@5d {
compatible = "goodix,gt9271";
reg = <0x5d>;
interrupt-parent = <&pio>;
interrupts = <132 IRQ_TYPE_EDGE_RISING>;
interrupts-extended = <&pio 132 IRQ_TYPE_EDGE_RISING>;
irq-gpios = <&pio 132 GPIO_ACTIVE_HIGH>;
reset-gpios = <&pio 133 GPIO_ACTIVE_HIGH>;
AVDD28-supply = <&mt6360_ldo1>;
......@@ -773,8 +772,7 @@ pins {
};
&pmic {
interrupt-parent = <&pio>;
interrupts = <222 IRQ_TYPE_LEVEL_HIGH>;
interrupts-extended = <&pio 222 IRQ_TYPE_LEVEL_HIGH>;
};
&scp {
......
include/dt-bindings/reset/mt8188-resets.h
View file @ 76955bc8
This diff is collapsed.
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