drm/i915: Handle dbuf bypass path allocation earlier

We always reserve the same 4 dbuf blocks for the bypass path
allocation, so might as well do that when declaring the dbuf
size.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210416171011.19012-3-ville.syrjala@linux.intel.comReviewed-by: Jani Nikula <jani.nikula@intel.com>

drivers/gpu/drm/i915/i915_pci.c

@@ -647,7 +647,7 @@ static const struct intel_device_info chv_info = {
 	.has_gt_uc = 1, \
 	.display.has_hdcp = 1, \
 	.display.has_ipc = 1, \
-	.dbuf.size = 896, \
+	.dbuf.size = 896 - 4, /* 4 blocks for bypass path allocation */ \
 	.dbuf.num_slices = 1
 
 #define SKL_PLATFORM \
@@ -720,14 +720,14 @@ static const struct intel_device_info skl_gt4_info = {
 static const struct intel_device_info bxt_info = {
 	GEN9_LP_FEATURES,
 	PLATFORM(INTEL_BROXTON),
-	.dbuf.size = 512,
+	.dbuf.size = 512 - 4, /* 4 blocks for bypass path allocation */
 };
 
 static const struct intel_device_info glk_info = {
 	GEN9_LP_FEATURES,
 	PLATFORM(INTEL_GEMINILAKE),
 	.display.ver = 10,
-	.dbuf.size = 1024,
+	.dbuf.size = 1024 - 4, /* 4 blocks for bypass path allocation */
 	GLK_COLORS,
 };
 
@@ -790,7 +790,7 @@ static const struct intel_device_info cml_gt2_info = {
 #define GEN10_FEATURES \
 	GEN9_FEATURES, \
 	GEN(10), \
-	.dbuf.size = 1024, \
+	.dbuf.size = 1024 - 4, /* 4 blocks for bypass path allocation */ \
 	.display.has_dsc = 1, \
 	.has_coherent_ggtt = false, \
 	GLK_COLORS

drivers/gpu/drm/i915/intel_pm.c

@@ -4030,14 +4030,7 @@ static int intel_compute_sagv_mask(struct intel_atomic_state *state)
 
 static int intel_dbuf_size(struct drm_i915_private *dev_priv)
 {
-	int ddb_size = INTEL_INFO(dev_priv)->dbuf.size;
-
-	drm_WARN_ON(&dev_priv->drm, ddb_size == 0);
-
-	if (DISPLAY_VER(dev_priv) < 11)
-		return ddb_size - 4; /* 4 blocks for bypass path allocation */
-
-	return ddb_size;
+	return INTEL_INFO(dev_priv)->dbuf.size;
 }
 
 static int intel_dbuf_slice_size(struct drm_i915_private *dev_priv)