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Commit 79e7739f authored by Rob Clark's avatar Rob Clark Committed by Andy Gross
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arm64: dts: qcom: sdm845-cheza: add initial cheza dt 

This is essentialy a squash of a bunch of history of cheza dt updates
from chromium kernel, some of which were themselves squashes of history
from older chromium kernels.

I don't claim any credit other than wanting to more easily boot upstream
kernel on cheza to have an easier way to test upstream driver work ;-)

I've added below in Cc tags all the original actual authors (apologies
if I missed any).

Cc: Douglas Anderson <dianders@chromium.org>
Cc: Sibi Sankar <sibis@codeaurora.org>
Cc: Evan Green <evgreen@chromium.org>
Cc: Matthias Kaehlcke <mka@chromium.org>
Cc: Abhinav Kumar <abhinavk@codeaurora.org>
Cc: Brian Norris <briannorris@chromium.org>
Cc: Venkat Gopalakrishnan <venkatg@codeaurora.org>
Cc: Rajendra Nayak <rnayak@codeaurora.org>
Signed-off-by: default avatarRob Clark <robdclark@chromium.org>
Reviewed-by: default avatarDouglas Anderson <dianders@chromium.org>
Signed-off-by: default avatarAndy Gross <agross@kernel.org>
parent f48cee32
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arch/arm64/boot/dts/qcom/Makefile
View file @ 79e7739f
......@@ -7,6 +7,9 @@ dtb-$(CONFIG_ARCH_QCOM) += msm8992-bullhead-rev-101.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8994-angler-rev-101.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8996-mtp.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8998-mtp.dtb
dtb-$(CONFIG_ARCH_QCOM) += sdm845-cheza-r1.dtb
dtb-$(CONFIG_ARCH_QCOM) += sdm845-cheza-r2.dtb
dtb-$(CONFIG_ARCH_QCOM) += sdm845-cheza-r3.dtb
dtb-$(CONFIG_ARCH_QCOM) += sdm845-db845c.dtb
dtb-$(CONFIG_ARCH_QCOM) += sdm845-mtp.dtb
dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-1000.dtb
......
arch/arm64/boot/dts/qcom/sdm845-cheza-r1.dts 0 → 100644
View file @ 79e7739f
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Google Cheza board device tree source
*
* Copyright 2018 Google LLC.
*/
/dts-v1/;
#include "sdm845-cheza.dtsi"
/ {
model = "Google Cheza (rev1)";
compatible = "google,cheza-rev1", "qcom,sdm845";
/*
* FIXED REGULATORS (not in sdm845-cheza.dtsi) - parents above children
*/
/*
* NOTE: Technically pp3500_a is not the exact same signal as
* pp3500_a_vbob (there's a load switch between them and the EC can
* control pp3500_a via "en_pp3300_a"), but from the AP's point of
* view they are the same.
*/
pp3500_a:
pp3500_a_vbob: pp3500-a-vbob-regulator {
compatible = "regulator-fixed";
regulator-name = "vreg_bob";
/*
* Comes on automatically when pp5000_ldo comes on, which
* comes on automatically when ppvar_sys comes on
*/
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3500000>;
regulator-max-microvolt = <3500000>;
vin-supply = <&ppvar_sys>;
};
pp3300_dx_edp: pp3300-dx-edp-regulator {
/* Yes, it's really 3.5 despite the name of the signal */
regulator-min-microvolt = <3500000>;
regulator-max-microvolt = <3500000>;
vin-supply = <&pp3500_a>;
};
};
/* FIXED REGULATOR OVERRIDES (modifications to sdm845-cheza.dtsi) */
/*
* L19 and L28 technically go to 3.3V, but most boards have old AOP firmware
* that limits them to 3.0, and trying to run at 3.3V with that old firmware
* prevents the system from booting.
*/
&src_pp3000_l19a {
regulator-min-microvolt = <3008000>;
regulator-max-microvolt = <3008000>;
};
&src_pp3300_l22a {
/delete-property/regulator-boot-on;
/delete-property/regulator-always-on;
};
&src_pp3300_l28a {
regulator-min-microvolt = <3008000>;
regulator-max-microvolt = <3008000>;
};
&src_vreg_bob {
regulator-min-microvolt = <3500000>;
regulator-max-microvolt = <3500000>;
vin-supply = <&pp3500_a_vbob>;
};
/*
* NON-REGULATOR OVERRIDES
* (modifications to sdm845-cheza.dtsi) - alphabetized by dtsi label
*/
/* PINCTRL - board-specific pinctrl */
&tlmm {
gpio-line-names = "AP_SPI_FP_MISO",
"AP_SPI_FP_MOSI",
"AP_SPI_FP_CLK",
"AP_SPI_FP_CS_L",
"UART_AP_TX_DBG_RX",
"UART_DBG_TX_AP_RX",
"",
"FP_RST_L",
"FCAM_EN",
"",
"EDP_BRIJ_IRQ",
"EC_IN_RW_ODL",
"",
"RCAM_MCLK",
"FCAM_MCLK",
"",
"RCAM_EN",
"CCI0_SDA",
"CCI0_SCL",
"CCI1_SDA",
"CCI1_SCL",
"FCAM_RST_L",
"",
"PEN_RST_L",
"PEN_IRQ_L",
"",
"RCAM_VSYNC",
"ESIM_MISO",
"ESIM_MOSI",
"ESIM_CLK",
"ESIM_CS_L",
"AP_PEN_1V8_SDA",
"AP_PEN_1V8_SCL",
"AP_TS_I2C_SDA",
"AP_TS_I2C_SCL",
"RCAM_RST_L",
"",
"AP_EDP_BKLTEN",
"AP_BRD_ID1",
"BOOT_CONFIG_4",
"AMP_IRQ_L",
"EDP_BRIJ_I2C_SDA",
"EDP_BRIJ_I2C_SCL",
"EN_PP3300_DX_EDP",
"SD_CD_ODL",
"BT_UART_RTS",
"BT_UART_CTS",
"BT_UART_RXD",
"BT_UART_TXD",
"AMP_I2C_SDA",
"AMP_I2C_SCL",
"AP_BRD_ID3",
"",
"AP_EC_SPI_CLK",
"AP_EC_SPI_CS_L",
"AP_EC_SPI_MISO",
"AP_EC_SPI_MOSI",
"FORCED_USB_BOOT",
"AMP_BCLK",
"AMP_LRCLK",
"AMP_DOUT",
"AMP_DIN",
"AP_BRD_ID2",
"PEN_PDCT_L",
"HP_MCLK",
"HP_BCLK",
"HP_LRCLK",
"HP_DOUT",
"HP_DIN",
"",
"",
"",
"",
"BT_SLIMBUS_DATA",
"BT_SLIMBUS_CLK",
"AMP_RESET_L",
"",
"FCAM_VSYNC",
"",
"AP_SKU_ID1",
"EC_WOV_BCLK",
"EC_WOV_LRCLK",
"EC_WOV_DOUT",
"",
"",
"AP_H1_SPI_MISO",
"AP_H1_SPI_MOSI",
"AP_H1_SPI_CLK",
"AP_H1_SPI_CS_L",
"",
"AP_SPI_CS0_L",
"AP_SPI_MOSI",
"AP_SPI_MISO",
"",
"",
"AP_SPI_CLK",
"",
"RFFE6_CLK",
"RFFE6_DATA",
"BOOT_CONFIG_1",
"BOOT_CONFIG_2",
"BOOT_CONFIG_0",
"EDP_BRIJ_EN",
"",
"USB_HS_TX_EN",
"UIM2_DATA",
"UIM2_CLK",
"UIM2_RST",
"UIM2_PRESENT",
"UIM1_DATA",
"UIM1_CLK",
"UIM1_RST",
"",
"AP_SKU_ID2",
"SDM_GRFC_8",
"SDM_GRFC_9",
"AP_RST_REQ",
"HP_IRQ",
"TS_RESET_L",
"PEN_EJECT_ODL",
"HUB_RST_L",
"FP_TO_AP_IRQ",
"AP_EC_INT_L",
"",
"",
"TS_INT_L",
"AP_SUSPEND_L",
"SDM_GRFC_3",
"",
"H1_AP_INT_ODL",
"QLINK_REQ",
"QLINK_EN",
"SDM_GRFC_2",
"BOOT_CONFIG_3",
"WMSS_RESET_L",
"SDM_GRFC_0",
"SDM_GRFC_1",
"RFFE3_DATA",
"RFFE3_CLK",
"RFFE4_DATA",
"RFFE4_CLK",
"RFFE5_DATA",
"RFFE5_CLK",
"GNSS_EN",
"WCI2_LTE_COEX_RXD",
"WCI2_LTE_COEX_TXD",
"AP_RAM_ID1",
"AP_RAM_ID2",
"RFFE1_DATA",
"RFFE1_CLK";
};
arch/arm64/boot/dts/qcom/sdm845-cheza-r2.dts 0 → 100644
View file @ 79e7739f
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Google Cheza board device tree source
*
* Copyright 2018 Google LLC.
*/
/dts-v1/;
#include "sdm845-cheza.dtsi"
/ {
model = "Google Cheza (rev2)";
compatible = "google,cheza-rev2", "qcom,sdm845";
/*
* FIXED REGULATORS (not in sdm845-cheza.dtsi) - parents above children
*/
/*
* NOTE: Technically pp3500_a is not the exact same signal as
* pp3500_a_vbob (there's a load switch between them and the EC can
* control pp3500_a via "en_pp3300_a"), but from the AP's point of
* view they are the same.
*/
pp3500_a:
pp3500_a_vbob: pp3500-a-vbob-regulator {
compatible = "regulator-fixed";
regulator-name = "vreg_bob";
/*
* Comes on automatically when pp5000_ldo comes on, which
* comes on automatically when ppvar_sys comes on
*/
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3500000>;
regulator-max-microvolt = <3500000>;
vin-supply = <&ppvar_sys>;
};
pp3300_dx_edp: pp3300-dx-edp-regulator {
/* Yes, it's really 3.5 despite the name of the signal */
regulator-min-microvolt = <3500000>;
regulator-max-microvolt = <3500000>;
vin-supply = <&pp3500_a>;
};
};
/* FIXED REGULATOR OVERRIDES (modifications to sdm845-cheza.dtsi) */
/*
* L19 and L28 technically go to 3.3V, but most boards have old AOP firmware
* that limits them to 3.0, and trying to run at 3.3V with that old firmware
* prevents the system from booting.
*/
&src_pp3000_l19a {
regulator-min-microvolt = <3008000>;
regulator-max-microvolt = <3008000>;
};
&src_pp3300_l22a {
/delete-property/regulator-boot-on;
/delete-property/regulator-always-on;
};
&src_pp3300_l28a {
regulator-min-microvolt = <3008000>;
regulator-max-microvolt = <3008000>;
};
&src_vreg_bob {
regulator-min-microvolt = <3500000>;
regulator-max-microvolt = <3500000>;
vin-supply = <&pp3500_a_vbob>;
};
/*
* NON-REGULATOR OVERRIDES
* (modifications to sdm845-cheza.dtsi) - alphabetized by dtsi label
*/
/* PINCTRL - board-specific pinctrl */
&tlmm {
gpio-line-names = "AP_SPI_FP_MISO",
"AP_SPI_FP_MOSI",
"AP_SPI_FP_CLK",
"AP_SPI_FP_CS_L",
"UART_AP_TX_DBG_RX",
"UART_DBG_TX_AP_RX",
"BRIJ_SUSPEND",
"FP_RST_L",
"FCAM_EN",
"",
"EDP_BRIJ_IRQ",
"EC_IN_RW_ODL",
"",
"RCAM_MCLK",
"FCAM_MCLK",
"",
"RCAM_EN",
"CCI0_SDA",
"CCI0_SCL",
"CCI1_SDA",
"CCI1_SCL",
"FCAM_RST_L",
"FPMCU_BOOT0",
"PEN_RST_L",
"PEN_IRQ_L",
"FPMCU_SEL_OD",
"RCAM_VSYNC",
"ESIM_MISO",
"ESIM_MOSI",
"ESIM_CLK",
"ESIM_CS_L",
"AP_PEN_1V8_SDA",
"AP_PEN_1V8_SCL",
"AP_TS_I2C_SDA",
"AP_TS_I2C_SCL",
"RCAM_RST_L",
"",
"AP_EDP_BKLTEN",
"AP_BRD_ID1",
"BOOT_CONFIG_4",
"AMP_IRQ_L",
"EDP_BRIJ_I2C_SDA",
"EDP_BRIJ_I2C_SCL",
"EN_PP3300_DX_EDP",
"SD_CD_ODL",
"BT_UART_RTS",
"BT_UART_CTS",
"BT_UART_RXD",
"BT_UART_TXD",
"AMP_I2C_SDA",
"AMP_I2C_SCL",
"AP_BRD_ID3",
"",
"AP_EC_SPI_CLK",
"AP_EC_SPI_CS_L",
"AP_EC_SPI_MISO",
"AP_EC_SPI_MOSI",
"FORCED_USB_BOOT",
"AMP_BCLK",
"AMP_LRCLK",
"AMP_DOUT",
"AMP_DIN",
"AP_BRD_ID2",
"PEN_PDCT_L",
"HP_MCLK",
"HP_BCLK",
"HP_LRCLK",
"HP_DOUT",
"HP_DIN",
"",
"",
"",
"",
"BT_SLIMBUS_DATA",
"BT_SLIMBUS_CLK",
"AMP_RESET_L",
"",
"FCAM_VSYNC",
"",
"AP_SKU_ID1",
"EC_WOV_BCLK",
"EC_WOV_LRCLK",
"EC_WOV_DOUT",
"",
"",
"AP_H1_SPI_MISO",
"AP_H1_SPI_MOSI",
"AP_H1_SPI_CLK",
"AP_H1_SPI_CS_L",
"",
"AP_SPI_CS0_L",
"AP_SPI_MOSI",
"AP_SPI_MISO",
"",
"",
"AP_SPI_CLK",
"",
"RFFE6_CLK",
"RFFE6_DATA",
"BOOT_CONFIG_1",
"BOOT_CONFIG_2",
"BOOT_CONFIG_0",
"EDP_BRIJ_EN",
"",
"USB_HS_TX_EN",
"UIM2_DATA",
"UIM2_CLK",
"UIM2_RST",
"UIM2_PRESENT",
"UIM1_DATA",
"UIM1_CLK",
"UIM1_RST",
"",
"AP_SKU_ID2",
"SDM_GRFC_8",
"SDM_GRFC_9",
"AP_RST_REQ",
"HP_IRQ",
"TS_RESET_L",
"PEN_EJECT_ODL",
"HUB_RST_L",
"FP_TO_AP_IRQ",
"AP_EC_INT_L",
"",
"",
"TS_INT_L",
"AP_SUSPEND_L",
"SDM_GRFC_3",
"",
"H1_AP_INT_ODL",
"QLINK_REQ",
"QLINK_EN",
"SDM_GRFC_2",
"BOOT_CONFIG_3",
"WMSS_RESET_L",
"SDM_GRFC_0",
"SDM_GRFC_1",
"RFFE3_DATA",
"RFFE3_CLK",
"RFFE4_DATA",
"RFFE4_CLK",
"RFFE5_DATA",
"RFFE5_CLK",
"GNSS_EN",
"WCI2_LTE_COEX_RXD",
"WCI2_LTE_COEX_TXD",
"AP_RAM_ID1",
"AP_RAM_ID2",
"RFFE1_DATA",
"RFFE1_CLK";
};
arch/arm64/boot/dts/qcom/sdm845-cheza-r3.dts 0 → 100644
View file @ 79e7739f
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Google Cheza board device tree source
*
* Copyright 2018 Google LLC.
*/
/dts-v1/;
#include "sdm845-cheza.dtsi"
/ {
model = "Google Cheza (rev3+)";
compatible = "google,cheza", "qcom,sdm845";
};
/* PINCTRL - board-specific pinctrl */
&tlmm {
gpio-line-names = "AP_SPI_FP_MISO",
"AP_SPI_FP_MOSI",
"AP_SPI_FP_CLK",
"AP_SPI_FP_CS_L",
"UART_AP_TX_DBG_RX",
"UART_DBG_TX_AP_RX",
"BRIJ_SUSPEND",
"FP_RST_L",
"FCAM_EN",
"",
"EDP_BRIJ_IRQ",
"EC_IN_RW_ODL",
"",
"RCAM_MCLK",
"FCAM_MCLK",
"",
"RCAM_EN",
"CCI0_SDA",
"CCI0_SCL",
"CCI1_SDA",
"CCI1_SCL",
"FCAM_RST_L",
"FPMCU_BOOT0",
"PEN_RST_L",
"PEN_IRQ_L",
"FPMCU_SEL_OD",
"RCAM_VSYNC",
"ESIM_MISO",
"ESIM_MOSI",
"ESIM_CLK",
"ESIM_CS_L",
"AP_PEN_1V8_SDA",
"AP_PEN_1V8_SCL",
"AP_TS_I2C_SDA",
"AP_TS_I2C_SCL",
"RCAM_RST_L",
"",
"AP_EDP_BKLTEN",
"AP_BRD_ID0",
"BOOT_CONFIG_4",
"AMP_IRQ_L",
"EDP_BRIJ_I2C_SDA",
"EDP_BRIJ_I2C_SCL",
"EN_PP3300_DX_EDP",
"SD_CD_ODL",
"BT_UART_RTS",
"BT_UART_CTS",
"BT_UART_RXD",
"BT_UART_TXD",
"AMP_I2C_SDA",
"AMP_I2C_SCL",
"AP_BRD_ID2",
"",
"AP_EC_SPI_CLK",
"AP_EC_SPI_CS_L",
"AP_EC_SPI_MISO",
"AP_EC_SPI_MOSI",
"FORCED_USB_BOOT",
"AMP_BCLK",
"AMP_LRCLK",
"AMP_DOUT",
"AMP_DIN",
"AP_BRD_ID1",
"PEN_PDCT_L",
"HP_MCLK",
"HP_BCLK",
"HP_LRCLK",
"HP_DOUT",
"HP_DIN",
"",
"",
"",
"",
"BT_SLIMBUS_DATA",
"BT_SLIMBUS_CLK",
"AMP_RESET_L",
"",
"FCAM_VSYNC",
"",
"AP_SKU_ID0",
"EC_WOV_BCLK",
"EC_WOV_LRCLK",
"EC_WOV_DOUT",
"",
"",
"AP_H1_SPI_MISO",
"AP_H1_SPI_MOSI",
"AP_H1_SPI_CLK",
"AP_H1_SPI_CS_L",
"",
"AP_SPI_CS0_L",
"AP_SPI_MOSI",
"AP_SPI_MISO",
"",
"",
"AP_SPI_CLK",
"",
"RFFE6_CLK",
"RFFE6_DATA",
"BOOT_CONFIG_1",
"BOOT_CONFIG_2",
"BOOT_CONFIG_0",
"EDP_BRIJ_EN",
"",
"USB_HS_TX_EN",
"UIM2_DATA",
"UIM2_CLK",
"UIM2_RST",
"UIM2_PRESENT",
"UIM1_DATA",
"UIM1_CLK",
"UIM1_RST",
"",
"AP_SKU_ID1",
"SDM_GRFC_8",
"SDM_GRFC_9",
"AP_RST_REQ",
"HP_IRQ",
"TS_RESET_L",
"PEN_EJECT_ODL",
"HUB_RST_L",
"FP_TO_AP_IRQ",
"AP_EC_INT_L",
"",
"",
"TS_INT_L",
"AP_SUSPEND_L",
"SDM_GRFC_3",
/*
* AP_FLASH_WP_L is crossystem ABI. Rev3 schematics
* call it BIOS_FLASH_WP_R_L.
*/
"AP_FLASH_WP_L",
"H1_AP_INT_ODL",
"QLINK_REQ",
"QLINK_EN",
"SDM_GRFC_2",
"BOOT_CONFIG_3",
"WMSS_RESET_L",
"SDM_GRFC_0",
"SDM_GRFC_1",
"RFFE3_DATA",
"RFFE3_CLK",
"RFFE4_DATA",
"RFFE4_CLK",
"RFFE5_DATA",
"RFFE5_CLK",
"GNSS_EN",
"WCI2_LTE_COEX_RXD",
"WCI2_LTE_COEX_TXD",
"AP_RAM_ID0",
"AP_RAM_ID1",
"RFFE1_DATA",
"RFFE1_CLK";
};
arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi 0 → 100644
View file @ 79e7739f
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