platform/x86: intel_pmc_core: Add debugfs support to access live status registers
Just like status registers, Tiger Lake has another set of 6 registers that help with status of the low power mode requirements. They are latched on every PC10 entry/exit and S0ix.y entry/exit as well. Though status and live status registers show the status of same list of requirements, live status registers show the status of the low power mode requirements at the time of reading. Cc: Srinivas Pandruvada <srinivas.pandruvada@intel.com> Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Cc: David E. Box <david.e.box@intel.com> Signed-off-by: Gayatri Kammela <gayatri.kammela@intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
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