Commit 7b0b0ec1 authored by Peter Meerwald-Stadler's avatar Peter Meerwald-Stadler Committed by Jonathan Cameron

iio: health: max30102: Fix mode config values

Table 4 of the datasheet specifies the mode control, these are not
individual bits; add multi LED mode

Add multi-LED mode and fix MODE_MASK (3 bits wide, not 2)
Signed-off-by: default avatarPeter Meerwald-Stadler <pmeerw@pmeerw.net>
Acked-by: default avatarMatt Ranostay <matt.ranostay@konsulko.com>
Signed-off-by: default avatarJonathan Cameron <Jonathan.Cameron@huawei.com>
parent c31c946a
...@@ -60,9 +60,10 @@ ...@@ -60,9 +60,10 @@
#define MAX30102_REG_FIFO_CONFIG_AFULL BIT(0) #define MAX30102_REG_FIFO_CONFIG_AFULL BIT(0)
#define MAX30102_REG_MODE_CONFIG 0x09 #define MAX30102_REG_MODE_CONFIG 0x09
#define MAX30102_REG_MODE_CONFIG_MODE_SPO2_EN BIT(0) #define MAX30102_REG_MODE_CONFIG_MODE_HR 0x02 /* red LED */
#define MAX30102_REG_MODE_CONFIG_MODE_HR_EN BIT(1) #define MAX30102_REG_MODE_CONFIG_MODE_HR_SPO2 0x03 /* red + IR LED */
#define MAX30102_REG_MODE_CONFIG_MODE_MASK 0x03 #define MAX30102_REG_MODE_CONFIG_MODE_MULTI 0x07 /* multi-LED mode */
#define MAX30102_REG_MODE_CONFIG_MODE_MASK GENMASK(2, 0)
#define MAX30102_REG_MODE_CONFIG_PWR BIT(7) #define MAX30102_REG_MODE_CONFIG_PWR BIT(7)
#define MAX30102_REG_SPO2_CONFIG 0x0a #define MAX30102_REG_SPO2_CONFIG 0x0a
...@@ -287,11 +288,10 @@ static int max30102_chip_init(struct max30102_data *data) ...@@ -287,11 +288,10 @@ static int max30102_chip_init(struct max30102_data *data)
if (ret) if (ret)
return ret; return ret;
/* enable SPO2 mode */ /* enable HR + SPO2 mode */
ret = regmap_update_bits(data->regmap, MAX30102_REG_MODE_CONFIG, ret = regmap_update_bits(data->regmap, MAX30102_REG_MODE_CONFIG,
MAX30102_REG_MODE_CONFIG_MODE_MASK, MAX30102_REG_MODE_CONFIG_MODE_MASK,
MAX30102_REG_MODE_CONFIG_MODE_HR_EN | MAX30102_REG_MODE_CONFIG_MODE_HR_SPO2);
MAX30102_REG_MODE_CONFIG_MODE_SPO2_EN);
if (ret) if (ret)
return ret; return ret;
......
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