Commit 7b76ab83 authored by Jiaxun Yang's avatar Jiaxun Yang Committed by Thomas Bogendoerfer

MIPS: Loongson64: Opt-out war_io_reorder_wmb

It is clearly stated on "Loongson 3A3000/3B3000 processor
user manual vol 2" that

"All access requests using a non-cached algorithm are executed in a
blocking order. That is, before the current read request data is
returned to the processor, all subsequent requests are blocked and issued;
All subsequent requests are blocked until the write request data has been
sent or the issued write request has not received a write reply from the
final receiver."

Which means uncached read/write is strongly ordered. So we won't need this
workaround.

This option was introduced when we add initial support for GS464E, it looks
like a misinterpretation of another section in the manual saying we need
barriers to ensure MMIO order against DMA requests.
Signed-off-by: default avatarJiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: default avatarThomas Bogendoerfer <tsbogend@alpha.franken.de>
parent 162e134a
...@@ -210,7 +210,7 @@ void iounmap(const volatile void __iomem *addr); ...@@ -210,7 +210,7 @@ void iounmap(const volatile void __iomem *addr);
#define ioremap_wc(offset, size) \ #define ioremap_wc(offset, size) \
ioremap_prot((offset), (size), boot_cpu_data.writecombine) ioremap_prot((offset), (size), boot_cpu_data.writecombine)
#if defined(CONFIG_CPU_CAVIUM_OCTEON) || defined(CONFIG_CPU_LOONGSON64) #if defined(CONFIG_CPU_CAVIUM_OCTEON)
#define war_io_reorder_wmb() wmb() #define war_io_reorder_wmb() wmb()
#else #else
#define war_io_reorder_wmb() barrier() #define war_io_reorder_wmb() barrier()
......
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