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Commit 7ba51aa2 authored by Alex Elder's avatar Alex Elder Committed by David S. Miller
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net: ipa: define IPA v3.1 GSI interrupt register offsets 

Add definitions of the offsets for IRQ-related GSI registers.  Use
gsi_reg() rather than the corresponding GSI_CNTXT_*_OFFSET() macros
to get the offsets for these registers, and get rid of the macros.
Signed-off-by: default avatarAlex Elder <elder@linaro.org>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent d1ce6395
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Showing with 195 additions and 102 deletions
drivers/net/ipa/gsi.c
View file @ 7ba51aa2
This diff is collapsed.
drivers/net/ipa/gsi_reg.h
View file @ 7ba51aa2
......@@ -95,16 +95,6 @@ enum gsi_reg_id {
GSI_REG_ID_COUNT, /* Last; not an ID */
};
/* The inter-EE IRQ registers are relative to gsi->virt_raw (IPA v3.5+) */
#define GSI_INTER_EE_SRC_CH_IRQ_MSK_OFFSET \
(0x0000c020 + 0x1000 * GSI_EE_AP)
#define GSI_INTER_EE_SRC_EV_CH_IRQ_MSK_OFFSET \
(0x0000c024 + 0x1000 * GSI_EE_AP)
/* All other register offsets are relative to gsi->virt */
/* CH_C_CNTXT_0 register */
#define CHTYPE_PROTOCOL_FMASK GENMASK(2, 0)
#define CHTYPE_DIR_FMASK GENMASK(3, 3)
......@@ -240,12 +230,6 @@ enum gsi_iram_size {
IRAM_SIZE_FOUR_KB = 0x5,
};
/* IRQ condition for each type is cleared by writing type-specific register */
#define GSI_CNTXT_TYPE_IRQ_OFFSET \
(0x0001f080 + 0x4000 * GSI_EE_AP)
#define GSI_CNTXT_TYPE_IRQ_MSK_OFFSET \
(0x0001f088 + 0x4000 * GSI_EE_AP)
/**
* enum gsi_irq_type_id: GSI IRQ types
* @GSI_CH_CTRL: Channel allocation, deallocation, etc.
......@@ -267,40 +251,6 @@ enum gsi_irq_type_id {
/* IRQ types 7-31 (and their bit values) are reserved */
};
#define GSI_CNTXT_SRC_CH_IRQ_OFFSET \
(0x0001f090 + 0x4000 * GSI_EE_AP)
#define GSI_CNTXT_SRC_EV_CH_IRQ_OFFSET \
(0x0001f094 + 0x4000 * GSI_EE_AP)
#define GSI_CNTXT_SRC_CH_IRQ_MSK_OFFSET \
(0x0001f098 + 0x4000 * GSI_EE_AP)
#define GSI_CNTXT_SRC_EV_CH_IRQ_MSK_OFFSET \
(0x0001f09c + 0x4000 * GSI_EE_AP)
#define GSI_CNTXT_SRC_CH_IRQ_CLR_OFFSET \
(0x0001f0a0 + 0x4000 * GSI_EE_AP)
#define GSI_CNTXT_SRC_EV_CH_IRQ_CLR_OFFSET \
(0x0001f0a4 + 0x4000 * GSI_EE_AP)
#define GSI_CNTXT_SRC_IEOB_IRQ_OFFSET \
(0x0001f0b0 + 0x4000 * GSI_EE_AP)
#define GSI_CNTXT_SRC_IEOB_IRQ_MSK_OFFSET \
(0x0001f0b8 + 0x4000 * GSI_EE_AP)
#define GSI_CNTXT_SRC_IEOB_IRQ_CLR_OFFSET \
(0x0001f0c0 + 0x4000 * GSI_EE_AP)
#define GSI_CNTXT_GLOB_IRQ_STTS_OFFSET \
(0x0001f100 + 0x4000 * GSI_EE_AP)
#define GSI_CNTXT_GLOB_IRQ_EN_OFFSET \
(0x0001f108 + 0x4000 * GSI_EE_AP)
#define GSI_CNTXT_GLOB_IRQ_CLR_OFFSET \
(0x0001f110 + 0x4000 * GSI_EE_AP)
/** enum gsi_global_irq_id: Global GSI interrupt events */
enum gsi_global_irq_id {
ERROR_INT = BIT(0),
......@@ -310,13 +260,6 @@ enum gsi_global_irq_id {
/* Global IRQ types 4-31 (and their bit values) are reserved */
};
#define GSI_CNTXT_GSI_IRQ_STTS_OFFSET \
(0x0001f118 + 0x4000 * GSI_EE_AP)
#define GSI_CNTXT_GSI_IRQ_EN_OFFSET \
(0x0001f120 + 0x4000 * GSI_EE_AP)
#define GSI_CNTXT_GSI_IRQ_CLR_OFFSET \
(0x0001f128 + 0x4000 * GSI_EE_AP)
/** enum gsi_general_irq_id: GSI general IRQ conditions */
enum gsi_general_irq_id {
BREAK_POINT = BIT(0),
......@@ -326,8 +269,7 @@ enum gsi_general_irq_id {
/* General IRQ types 4-31 (and their bit values) are reserved */
};
#define GSI_CNTXT_INTSET_OFFSET \
(0x0001f180 + 0x4000 * GSI_EE_AP)
/* CNTXT_INTSET register */
#define INTYPE_FMASK GENMASK(0, 0)
#define GSI_ERROR_LOG_OFFSET \
......@@ -363,8 +305,6 @@ enum gsi_err_type {
#define GSI_ERROR_LOG_CLR_OFFSET \
(0x0001f210 + 0x4000 * GSI_EE_AP)
#define GSI_CNTXT_SCRATCH_0_OFFSET \
(0x0001f400 + 0x4000 * GSI_EE_AP)
#define INTER_EE_RESULT_FMASK GENMASK(2, 0)
#define GENERIC_EE_RESULT_FMASK GENMASK(7, 5)
......
drivers/net/ipa/reg/gsi_reg-v3.1.c
View file @ 7ba51aa2
......@@ -8,6 +8,16 @@
#include "../reg.h"
#include "../gsi_reg.h"
/* The inter-EE IRQ registers are relative to gsi->virt_raw (IPA v3.5+) */
REG(INTER_EE_SRC_CH_IRQ_MSK, inter_ee_src_ch_irq_msk,
0x0000c020 + 0x1000 * GSI_EE_AP);
REG(INTER_EE_SRC_EV_CH_IRQ_MSK, inter_ee_src_ev_ch_irq_msk,
0x0000c024 + 0x1000 * GSI_EE_AP);
/* All other register offsets are relative to gsi->virt */
REG_STRIDE(CH_C_CNTXT_0, ch_c_cntxt_0, 0x0001c000 + 0x4000 * GSI_EE_AP, 0x80);
REG_STRIDE(CH_C_CNTXT_1, ch_c_cntxt_1, 0x0001c004 + 0x4000 * GSI_EE_AP, 0x80);
......@@ -75,7 +85,53 @@ REG_STRIDE(CH_C_DOORBELL_0, ch_c_doorbell_0,
REG_STRIDE(EV_CH_E_DOORBELL_0, ev_ch_e_doorbell_0,
0x0001e100 + 0x4000 * GSI_EE_AP, 0x08);
REG(CNTXT_TYPE_IRQ, cntxt_type_irq, 0x0001f080 + 0x4000 * GSI_EE_AP);
REG(CNTXT_TYPE_IRQ_MSK, cntxt_type_irq_msk, 0x0001f088 + 0x4000 * GSI_EE_AP);
REG(CNTXT_SRC_CH_IRQ, cntxt_src_ch_irq, 0x0001f090 + 0x4000 * GSI_EE_AP);
REG(CNTXT_SRC_EV_CH_IRQ, cntxt_src_ev_ch_irq, 0x0001f094 + 0x4000 * GSI_EE_AP);
REG(CNTXT_SRC_CH_IRQ_MSK, cntxt_src_ch_irq_msk,
0x0001f098 + 0x4000 * GSI_EE_AP);
REG(CNTXT_SRC_EV_CH_IRQ_MSK, cntxt_src_ev_ch_irq_msk,
0x0001f09c + 0x4000 * GSI_EE_AP);
REG(CNTXT_SRC_CH_IRQ_CLR, cntxt_src_ch_irq_clr,
0x0001f0a0 + 0x4000 * GSI_EE_AP);
REG(CNTXT_SRC_EV_CH_IRQ_CLR, cntxt_src_ev_ch_irq_clr,
0x0001f0a4 + 0x4000 * GSI_EE_AP);
REG(CNTXT_SRC_IEOB_IRQ, cntxt_src_ieob_irq, 0x0001f0b0 + 0x4000 * GSI_EE_AP);
REG(CNTXT_SRC_IEOB_IRQ_MSK, cntxt_src_ieob_irq_msk,
0x0001f0b8 + 0x4000 * GSI_EE_AP);
REG(CNTXT_SRC_IEOB_IRQ_CLR, cntxt_src_ieob_irq_clr,
0x0001f0c0 + 0x4000 * GSI_EE_AP);
REG(CNTXT_GLOB_IRQ_STTS, cntxt_glob_irq_stts, 0x0001f100 + 0x4000 * GSI_EE_AP);
REG(CNTXT_GLOB_IRQ_EN, cntxt_glob_irq_en, 0x0001f108 + 0x4000 * GSI_EE_AP);
REG(CNTXT_GLOB_IRQ_CLR, cntxt_glob_irq_clr, 0x0001f110 + 0x4000 * GSI_EE_AP);
REG(CNTXT_GSI_IRQ_STTS, cntxt_gsi_irq_stts, 0x0001f118 + 0x4000 * GSI_EE_AP);
REG(CNTXT_GSI_IRQ_EN, cntxt_gsi_irq_en, 0x0001f120 + 0x4000 * GSI_EE_AP);
REG(CNTXT_GSI_IRQ_CLR, cntxt_gsi_irq_clr, 0x0001f128 + 0x4000 * GSI_EE_AP);
REG(CNTXT_INTSET, cntxt_intset, 0x0001f180 + 0x4000 * GSI_EE_AP);
REG(CNTXT_SCRATCH_0, cntxt_scratch_0, 0x0001f400 + 0x4000 * GSI_EE_AP);
static const struct reg *reg_array[] = {
[INTER_EE_SRC_CH_IRQ_MSK] = &reg_inter_ee_src_ch_irq_msk,
[INTER_EE_SRC_EV_CH_IRQ_MSK] = &reg_inter_ee_src_ev_ch_irq_msk,
[CH_C_CNTXT_0] = &reg_ch_c_cntxt_0,
[CH_C_CNTXT_1] = &reg_ch_c_cntxt_1,
[CH_C_CNTXT_2] = &reg_ch_c_cntxt_2,
......@@ -100,6 +156,25 @@ static const struct reg *reg_array[] = {
[EV_CH_E_SCRATCH_1] = &reg_ev_ch_e_scratch_1,
[CH_C_DOORBELL_0] = &reg_ch_c_doorbell_0,
[EV_CH_E_DOORBELL_0] = &reg_ev_ch_e_doorbell_0,
[CNTXT_TYPE_IRQ] = &reg_cntxt_type_irq,
[CNTXT_TYPE_IRQ_MSK] = &reg_cntxt_type_irq_msk,
[CNTXT_SRC_CH_IRQ] = &reg_cntxt_src_ch_irq,
[CNTXT_SRC_EV_CH_IRQ] = &reg_cntxt_src_ev_ch_irq,
[CNTXT_SRC_CH_IRQ_MSK] = &reg_cntxt_src_ch_irq_msk,
[CNTXT_SRC_EV_CH_IRQ_MSK] = &reg_cntxt_src_ev_ch_irq_msk,
[CNTXT_SRC_CH_IRQ_CLR] = &reg_cntxt_src_ch_irq_clr,
[CNTXT_SRC_EV_CH_IRQ_CLR] = &reg_cntxt_src_ev_ch_irq_clr,
[CNTXT_SRC_IEOB_IRQ] = &reg_cntxt_src_ieob_irq,
[CNTXT_SRC_IEOB_IRQ_MSK] = &reg_cntxt_src_ieob_irq_msk,
[CNTXT_SRC_IEOB_IRQ_CLR] = &reg_cntxt_src_ieob_irq_clr,
[CNTXT_GLOB_IRQ_STTS] = &reg_cntxt_glob_irq_stts,
[CNTXT_GLOB_IRQ_EN] = &reg_cntxt_glob_irq_en,
[CNTXT_GLOB_IRQ_CLR] = &reg_cntxt_glob_irq_clr,
[CNTXT_GSI_IRQ_STTS] = &reg_cntxt_gsi_irq_stts,
[CNTXT_GSI_IRQ_EN] = &reg_cntxt_gsi_irq_en,
[CNTXT_GSI_IRQ_CLR] = &reg_cntxt_gsi_irq_clr,
[CNTXT_INTSET] = &reg_cntxt_intset,
[CNTXT_SCRATCH_0] = &reg_cntxt_scratch_0,
};
const struct regs gsi_regs_v3_1 = {
......
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