Commit 7bbe59dd authored by Jaedon Shin's avatar Jaedon Shin Committed by Ralf Baechle

MIPS: BMIPS: Add support PWM device nodes

Adds PWM device nodes to BCM7xxx MIPS based SoCs.
Signed-off-by: default avatarJaedon Shin <jaedon.shin@gmail.com>
Reviewed-by: default avatarFlorian Fainelli <f.fainelli@gmail.com>
Cc: Jonas Gorski <jonas.gorski@gmail.com>
Cc: Kevin Cernekee <cernekee@gmail.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: MIPS Mailing List <linux-mips@linux-mips.org>
Cc: devicetree@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/14000/Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent c834469b
...@@ -40,6 +40,12 @@ uart_clk: uart_clk { ...@@ -40,6 +40,12 @@ uart_clk: uart_clk {
#clock-cells = <0>; #clock-cells = <0>;
clock-frequency = <81000000>; clock-frequency = <81000000>;
}; };
upg_clk: upg_clk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <27000000>;
};
}; };
rdb { rdb {
...@@ -183,6 +189,14 @@ bscd: i2c@406380 { ...@@ -183,6 +189,14 @@ bscd: i2c@406380 {
status = "disabled"; status = "disabled";
}; };
pwma: pwm@406580 {
compatible = "brcm,bcm7038-pwm";
reg = <0x406580 0x28>;
#pwm-cells = <2>;
clocks = <&upg_clk>;
status = "disabled";
};
ehci0: usb@488300 { ehci0: usb@488300 {
compatible = "brcm,bcm7125-ehci", "generic-ehci"; compatible = "brcm,bcm7125-ehci", "generic-ehci";
reg = <0x488300 0x100>; reg = <0x488300 0x100>;
......
...@@ -40,6 +40,12 @@ uart_clk: uart_clk { ...@@ -40,6 +40,12 @@ uart_clk: uart_clk {
#clock-cells = <0>; #clock-cells = <0>;
clock-frequency = <81000000>; clock-frequency = <81000000>;
}; };
upg_clk: upg_clk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <27000000>;
};
}; };
rdb { rdb {
...@@ -210,6 +216,22 @@ bsce: i2c@408980 { ...@@ -210,6 +216,22 @@ bsce: i2c@408980 {
status = "disabled"; status = "disabled";
}; };
pwma: pwm@406580 {
compatible = "brcm,bcm7038-pwm";
reg = <0x406580 0x28>;
#pwm-cells = <2>;
clocks = <&upg_clk>;
status = "disabled";
};
pwmb: pwm@406800 {
compatible = "brcm,bcm7038-pwm";
reg = <0x406800 0x28>;
#pwm-cells = <2>;
clocks = <&upg_clk>;
status = "disabled";
};
enet0: ethernet@430000 { enet0: ethernet@430000 {
phy-mode = "internal"; phy-mode = "internal";
phy-handle = <&phy1>; phy-handle = <&phy1>;
......
...@@ -34,6 +34,12 @@ uart_clk: uart_clk { ...@@ -34,6 +34,12 @@ uart_clk: uart_clk {
#clock-cells = <0>; #clock-cells = <0>;
clock-frequency = <81000000>; clock-frequency = <81000000>;
}; };
upg_clk: upg_clk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <27000000>;
};
}; };
rdb { rdb {
...@@ -194,6 +200,22 @@ bscd: i2c@408980 { ...@@ -194,6 +200,22 @@ bscd: i2c@408980 {
status = "disabled"; status = "disabled";
}; };
pwma: pwm@406400 {
compatible = "brcm,bcm7038-pwm";
reg = <0x406400 0x28>;
#pwm-cells = <2>;
clocks = <&upg_clk>;
status = "disabled";
};
pwmb: pwm@406700 {
compatible = "brcm,bcm7038-pwm";
reg = <0x406700 0x28>;
#pwm-cells = <2>;
clocks = <&upg_clk>;
status = "disabled";
};
enet0: ethernet@430000 { enet0: ethernet@430000 {
phy-mode = "internal"; phy-mode = "internal";
phy-handle = <&phy1>; phy-handle = <&phy1>;
......
...@@ -34,6 +34,12 @@ uart_clk: uart_clk { ...@@ -34,6 +34,12 @@ uart_clk: uart_clk {
#clock-cells = <0>; #clock-cells = <0>;
clock-frequency = <81000000>; clock-frequency = <81000000>;
}; };
upg_clk: upg_clk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <27000000>;
};
}; };
rdb { rdb {
...@@ -194,6 +200,14 @@ bscd: i2c@408980 { ...@@ -194,6 +200,14 @@ bscd: i2c@408980 {
status = "disabled"; status = "disabled";
}; };
pwma: pwm@406400 {
compatible = "brcm,bcm7038-pwm";
reg = <0x406400 0x28>;
#pwm-cells = <2>;
clocks = <&upg_clk>;
status = "disabled";
};
enet0: ethernet@430000 { enet0: ethernet@430000 {
phy-mode = "internal"; phy-mode = "internal";
phy-handle = <&phy1>; phy-handle = <&phy1>;
......
...@@ -40,6 +40,12 @@ uart_clk: uart_clk { ...@@ -40,6 +40,12 @@ uart_clk: uart_clk {
#clock-cells = <0>; #clock-cells = <0>;
clock-frequency = <81000000>; clock-frequency = <81000000>;
}; };
upg_clk: upg_clk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <27000000>;
};
}; };
rdb { rdb {
...@@ -190,6 +196,14 @@ bscd: i2c@408980 { ...@@ -190,6 +196,14 @@ bscd: i2c@408980 {
status = "disabled"; status = "disabled";
}; };
pwma: pwm@406400 {
compatible = "brcm,bcm7038-pwm";
reg = <0x406400 0x28>;
#pwm-cells = <2>;
clocks = <&upg_clk>;
status = "disabled";
};
enet0: ethernet@430000 { enet0: ethernet@430000 {
phy-mode = "internal"; phy-mode = "internal";
phy-handle = <&phy1>; phy-handle = <&phy1>;
......
...@@ -40,6 +40,12 @@ uart_clk: uart_clk { ...@@ -40,6 +40,12 @@ uart_clk: uart_clk {
#clock-cells = <0>; #clock-cells = <0>;
clock-frequency = <81000000>; clock-frequency = <81000000>;
}; };
upg_clk: upg_clk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <27000000>;
};
}; };
rdb { rdb {
...@@ -191,6 +197,22 @@ bsce: i2c@406800 { ...@@ -191,6 +197,22 @@ bsce: i2c@406800 {
status = "disabled"; status = "disabled";
}; };
pwma: pwm@406580 {
compatible = "brcm,bcm7038-pwm";
reg = <0x406580 0x28>;
#pwm-cells = <2>;
clocks = <&upg_clk>;
status = "disabled";
};
pwmb: pwm@406880 {
compatible = "brcm,bcm7038-pwm";
reg = <0x406880 0x28>;
#pwm-cells = <2>;
clocks = <&upg_clk>;
status = "disabled";
};
enet0: ethernet@468000 { enet0: ethernet@468000 {
phy-mode = "internal"; phy-mode = "internal";
phy-handle = <&phy1>; phy-handle = <&phy1>;
......
...@@ -40,6 +40,12 @@ uart_clk: uart_clk { ...@@ -40,6 +40,12 @@ uart_clk: uart_clk {
#clock-cells = <0>; #clock-cells = <0>;
clock-frequency = <81000000>; clock-frequency = <81000000>;
}; };
upg_clk: upg_clk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <27000000>;
};
}; };
rdb { rdb {
...@@ -209,6 +215,22 @@ bsce: i2c@406300 { ...@@ -209,6 +215,22 @@ bsce: i2c@406300 {
status = "disabled"; status = "disabled";
}; };
pwma: pwm@406580 {
compatible = "brcm,bcm7038-pwm";
reg = <0x406580 0x28>;
#pwm-cells = <2>;
clocks = <&upg_clk>;
status = "disabled";
};
pwmb: pwm@406800 {
compatible = "brcm,bcm7038-pwm";
reg = <0x406800 0x28>;
#pwm-cells = <2>;
clocks = <&upg_clk>;
status = "disabled";
};
enet0: ethernet@b80000 { enet0: ethernet@b80000 {
phy-mode = "internal"; phy-mode = "internal";
phy-handle = <&phy1>; phy-handle = <&phy1>;
......
...@@ -52,6 +52,12 @@ uart_clk: uart_clk { ...@@ -52,6 +52,12 @@ uart_clk: uart_clk {
#clock-cells = <0>; #clock-cells = <0>;
clock-frequency = <81000000>; clock-frequency = <81000000>;
}; };
upg_clk: upg_clk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <27000000>;
};
}; };
rdb { rdb {
...@@ -224,6 +230,22 @@ bsce: i2c@409180 { ...@@ -224,6 +230,22 @@ bsce: i2c@409180 {
status = "disabled"; status = "disabled";
}; };
pwma: pwm@406580 {
compatible = "brcm,bcm7038-pwm";
reg = <0x406580 0x28>;
#pwm-cells = <2>;
clocks = <&upg_clk>;
status = "disabled";
};
pwmb: pwm@406800 {
compatible = "brcm,bcm7038-pwm";
reg = <0x406800 0x28>;
#pwm-cells = <2>;
clocks = <&upg_clk>;
status = "disabled";
};
enet0: ethernet@b80000 { enet0: ethernet@b80000 {
phy-mode = "internal"; phy-mode = "internal";
phy-handle = <&phy1>; phy-handle = <&phy1>;
......
...@@ -45,6 +45,10 @@ &bscd { ...@@ -45,6 +45,10 @@ &bscd {
status = "okay"; status = "okay";
}; };
&pwma {
status = "okay";
};
/* FIXME: USB is wonky; disable it for now */ /* FIXME: USB is wonky; disable it for now */
&ehci0 { &ehci0 {
status = "disabled"; status = "disabled";
......
...@@ -49,6 +49,14 @@ &bsce { ...@@ -49,6 +49,14 @@ &bsce {
status = "okay"; status = "okay";
}; };
&pwma {
status = "okay";
};
&pwmb {
status = "okay";
};
&enet0 { &enet0 {
status = "okay"; status = "okay";
}; };
......
...@@ -45,6 +45,14 @@ &bscd { ...@@ -45,6 +45,14 @@ &bscd {
status = "okay"; status = "okay";
}; };
&pwma {
status = "okay";
};
&pwmb {
status = "okay";
};
&enet0 { &enet0 {
status = "okay"; status = "okay";
}; };
......
...@@ -45,6 +45,10 @@ &bscd { ...@@ -45,6 +45,10 @@ &bscd {
status = "okay"; status = "okay";
}; };
&pwma {
status = "okay";
};
&enet0 { &enet0 {
status = "okay"; status = "okay";
}; };
......
...@@ -41,6 +41,10 @@ &bscd { ...@@ -41,6 +41,10 @@ &bscd {
status = "okay"; status = "okay";
}; };
&pwma {
status = "okay";
};
&enet0 { &enet0 {
status = "okay"; status = "okay";
}; };
......
...@@ -51,6 +51,14 @@ &bsce { ...@@ -51,6 +51,14 @@ &bsce {
status = "okay"; status = "okay";
}; };
&pwma {
status = "okay";
};
&pwmb {
status = "okay";
};
/* FIXME: MAC driver comes up but cannot attach to PHY */ /* FIXME: MAC driver comes up but cannot attach to PHY */
&enet0 { &enet0 {
status = "disabled"; status = "disabled";
......
...@@ -51,6 +51,14 @@ &bsce { ...@@ -51,6 +51,14 @@ &bsce {
status = "okay"; status = "okay";
}; };
&pwma {
status = "okay";
};
&pwmb {
status = "okay";
};
&enet0 { &enet0 {
status = "okay"; status = "okay";
}; };
......
...@@ -51,6 +51,14 @@ &bsce { ...@@ -51,6 +51,14 @@ &bsce {
status = "okay"; status = "okay";
}; };
&pwma {
status = "okay";
};
&pwmb {
status = "okay";
};
&enet0 { &enet0 {
status = "okay"; status = "okay";
}; };
......
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