Commit 7bd22d8e authored by Michał Mirosław's avatar Michał Mirosław Committed by Kleber Sacilotto de Souza

mmc: sdhci: fix minimum clock rate for v3 controller

BugLink: https://bugs.launchpad.net/bugs/1864773

commit 2a187d03 upstream.

For SDHCIv3+ with programmable clock mode, minimal clock frequency is
still base clock / max(divider). Minimal programmable clock frequency is
always greater than minimal divided clock frequency. Without this patch,
SDHCI uses out-of-spec initial frequency when multiplier is big enough:

mmc1: mmc_rescan_try_freq: trying to init card at 468750 Hz
[for 480 MHz source clock divided by 1024]

The code in sdhci_calc_clk() already chooses a correct SDCLK clock mode.

Fixes: c3ed3877 ("mmc: sdhci: add support for programmable clock mode")
Cc: <stable@vger.kernel.org> # 4f6aa326: mmc: tegra: Only advertise UHS modes if IO regulator is present
Cc: <stable@vger.kernel.org>
Signed-off-by: default avatarMichał Mirosław <mirq-linux@rere.qmqm.pl>
Acked-by: default avatarAdrian Hunter <adrian.hunter@intel.com>
Link: https://lore.kernel.org/r/ffb489519a446caffe7a0a05c4b9372bd52397bb.1579082031.git.mirq-linux@rere.qmqm.plSigned-off-by: default avatarUlf Hansson <ulf.hansson@linaro.org>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Signed-off-by: default avatarKhalid Elmously <khalid.elmously@canonical.com>
Signed-off-by: default avatarKleber Sacilotto de Souza <kleber.souza@canonical.com>
parent 98d07bc1
...@@ -3111,11 +3111,13 @@ int sdhci_add_host(struct sdhci_host *host) ...@@ -3111,11 +3111,13 @@ int sdhci_add_host(struct sdhci_host *host)
if (host->ops->get_min_clock) if (host->ops->get_min_clock)
mmc->f_min = host->ops->get_min_clock(host); mmc->f_min = host->ops->get_min_clock(host);
else if (host->version >= SDHCI_SPEC_300) { else if (host->version >= SDHCI_SPEC_300) {
if (host->clk_mul) { if (host->clk_mul)
mmc->f_min = (host->max_clk * host->clk_mul) / 1024;
max_clk = host->max_clk * host->clk_mul; max_clk = host->max_clk * host->clk_mul;
} else /*
mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300; * Divided Clock Mode minimum clock rate is always less than
* Programmable Clock Mode minimum clock rate.
*/
mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300;
} else } else
mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200; mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200;
......
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