Commit 7cbc057d authored by H Hartley Sweeten's avatar H Hartley Sweeten Committed by Greg Kroah-Hartman

staging: comedi: addi_apci_3120: define the timer 2 operation bits

For aesthetics, redefine the bits in the mode register used to set the
operation mode of timer 2.
Signed-off-by: default avatarH Hartley Sweeten <hsweeten@visionengravers.com>
Reviewed-by: default avatarIan Abbott <abbotti@mev.co.uk>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent 1869ae02
......@@ -101,8 +101,6 @@ This program is distributed in the hope that it will be useful, but WITHOUT ANY
#define APCI3120_WRITE_MODE_SELECT 0x0e
#define APCI3120_RD_STATUS 0x02
#define APCI3120_ENABLE_WATCHDOG 0x20
#define APCI3120_ENABLE_TIMER_COUNTER 0x10
#define APCI3120_FC_TIMER 0x1000
#define APCI3120_TIMER2_SELECT_EOS 0xc0
......@@ -564,7 +562,7 @@ static int apci3120_cyclic_ai(int mode,
apci3120_clr_timer2_interrupt(dev);
/* enable timer counter and disable watch dog */
devpriv->mode |= APCI3120_ENABLE_TIMER_COUNTER;
devpriv->mode |= APCI3120_MODE_TIMER2_AS_COUNTER;
/* select EOS clock input for timer 2 */
devpriv->mode |= APCI3120_TIMER2_SELECT_EOS;
/* Enable timer2 interrupt */
......@@ -1081,9 +1079,9 @@ static int apci3120_config_insn_timer(struct comedi_device *dev,
apci3120_timer_enable(dev, 2, false);
/* Disable TIMER Interrupt */
/* disable timer 2 interrupt and reset operation mode (timer) */
devpriv->mode &= ~APCI3120_MODE_TIMER2_IRQ_ENA &
~APCI3120_ENABLE_TIMER_COUNTER;
~APCI3120_MODE_TIMER2_AS_MASK;
/* Disable Eoc and Eos Interrupts */
devpriv->mode &= ~APCI3120_MODE_EOC_IRQ_ENA &
......@@ -1156,10 +1154,11 @@ static int apci3120_write_insn_timer(struct comedi_device *dev,
if (devpriv->b_Timer2Mode == APCI3120_TIMER) { /* start timer */
/* Enable Timer */
devpriv->mode &= 0x0b;
devpriv->mode |= APCI3120_MODE_TIMER2_AS_TIMER;
} else { /* start watch dog */
/* Enable WatchDog */
devpriv->mode &= 0x0b;
devpriv->mode |= APCI3120_ENABLE_WATCHDOG;
devpriv->mode |= APCI3120_MODE_TIMER2_AS_WDOG;
}
/* enable disable interrupt */
......@@ -1179,15 +1178,9 @@ static int apci3120_write_insn_timer(struct comedi_device *dev,
break;
case APCI3120_STOP:
if (devpriv->b_Timer2Mode == APCI3120_TIMER) {
/* Disable timer */
devpriv->mode &= ~APCI3120_ENABLE_TIMER_COUNTER;
} else {
/* Disable WatchDog */
devpriv->mode &= ~APCI3120_ENABLE_WATCHDOG;
}
/* Disable timer interrupt */
devpriv->mode &= ~APCI3120_MODE_TIMER2_IRQ_ENA;
/* disable timer 2 interrupt and reset operation mode (timer) */
devpriv->mode &= ~APCI3120_MODE_TIMER2_IRQ_ENA &
~APCI3120_MODE_TIMER2_AS_MASK;
outb(devpriv->mode, dev->iobase + APCI3120_WRITE_MODE_SELECT);
apci3120_timer_enable(dev, 2, false);
......
......@@ -40,6 +40,10 @@
#define APCI3120_CTR0_REG 0x0d
#define APCI3120_CTR0_DO_BITS(x) ((x) << 4)
#define APCI3120_CTR0_TIMER_SEL(x) ((x) << 0)
#define APCI3120_MODE_TIMER2_AS_TIMER (0 << 4)
#define APCI3120_MODE_TIMER2_AS_COUNTER (1 << 4)
#define APCI3120_MODE_TIMER2_AS_WDOG (2 << 4)
#define APCI3120_MODE_TIMER2_AS_MASK (3 << 4) /* sets AS_TIMER */
#define APCI3120_MODE_SCAN_ENA (1 << 3)
#define APCI3120_MODE_TIMER2_IRQ_ENA (1 << 2)
#define APCI3120_MODE_EOS_IRQ_ENA (1 << 1)
......
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