Commit 7d7355f5 authored by Ben Hutchings's avatar Ben Hutchings Committed by David S. Miller

sh_eth: Ensure proper ordering of descriptor active bit write/read

When submitting a DMA descriptor, the active bit must be written last.
When reading a completed DMA descriptor, the active bit must be read
first.

Add memory barriers to ensure that this ordering is maintained.
Signed-off-by: default avatarBen Hutchings <ben.hutchings@codethink.co.uk>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent eee617a1
...@@ -1410,6 +1410,8 @@ static int sh_eth_txfree(struct net_device *ndev) ...@@ -1410,6 +1410,8 @@ static int sh_eth_txfree(struct net_device *ndev)
txdesc = &mdp->tx_ring[entry]; txdesc = &mdp->tx_ring[entry];
if (txdesc->status & cpu_to_edmac(mdp, TD_TACT)) if (txdesc->status & cpu_to_edmac(mdp, TD_TACT))
break; break;
/* TACT bit must be checked before all the following reads */
rmb();
/* Free the original skb. */ /* Free the original skb. */
if (mdp->tx_skbuff[entry]) { if (mdp->tx_skbuff[entry]) {
dma_unmap_single(&ndev->dev, txdesc->addr, dma_unmap_single(&ndev->dev, txdesc->addr,
...@@ -1447,6 +1449,8 @@ static int sh_eth_rx(struct net_device *ndev, u32 intr_status, int *quota) ...@@ -1447,6 +1449,8 @@ static int sh_eth_rx(struct net_device *ndev, u32 intr_status, int *quota)
limit = boguscnt; limit = boguscnt;
rxdesc = &mdp->rx_ring[entry]; rxdesc = &mdp->rx_ring[entry];
while (!(rxdesc->status & cpu_to_edmac(mdp, RD_RACT))) { while (!(rxdesc->status & cpu_to_edmac(mdp, RD_RACT))) {
/* RACT bit must be checked before all the following reads */
rmb();
desc_status = edmac_to_cpu(mdp, rxdesc->status); desc_status = edmac_to_cpu(mdp, rxdesc->status);
pkt_len = rxdesc->frame_length; pkt_len = rxdesc->frame_length;
...@@ -1526,6 +1530,7 @@ static int sh_eth_rx(struct net_device *ndev, u32 intr_status, int *quota) ...@@ -1526,6 +1530,7 @@ static int sh_eth_rx(struct net_device *ndev, u32 intr_status, int *quota)
skb_checksum_none_assert(skb); skb_checksum_none_assert(skb);
rxdesc->addr = dma_addr; rxdesc->addr = dma_addr;
} }
wmb(); /* RACT bit must be set after all the above writes */
if (entry >= mdp->num_rx_ring - 1) if (entry >= mdp->num_rx_ring - 1)
rxdesc->status |= rxdesc->status |=
cpu_to_edmac(mdp, RD_RACT | RD_RFP | RD_RDEL); cpu_to_edmac(mdp, RD_RACT | RD_RFP | RD_RDEL);
...@@ -2195,6 +2200,7 @@ static int sh_eth_start_xmit(struct sk_buff *skb, struct net_device *ndev) ...@@ -2195,6 +2200,7 @@ static int sh_eth_start_xmit(struct sk_buff *skb, struct net_device *ndev)
} }
txdesc->buffer_length = skb->len; txdesc->buffer_length = skb->len;
wmb(); /* TACT bit must be set after all the above writes */
if (entry >= mdp->num_tx_ring - 1) if (entry >= mdp->num_tx_ring - 1)
txdesc->status |= cpu_to_edmac(mdp, TD_TACT | TD_TDLE); txdesc->status |= cpu_to_edmac(mdp, TD_TACT | TD_TDLE);
else else
......
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