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Commit 7d938bc0 authored by Ville Syrjälä's avatar Ville Syrjälä
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drm/i915: Clean up DPINVGTT/VLV_DPFLIPSTAT bits 

Use REG_BIT() & co. for DPINVTT/VLV_DPFLIPSTAT bits.
Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20211112193813.8224-9-ville.syrjala@linux.intel.comReviewed-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
parent 6bb0a0e0
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Showing with 48 additions and 48 deletions
drivers/gpu/drm/i915/i915_irq.c
View file @ 7d938bc0
...@@ -3016,7 +3016,7 @@ static void vlv_display_irq_reset(struct drm_i915_private *dev_priv) ...@@ -3016,7 +3016,7 @@ static void vlv_display_irq_reset(struct drm_i915_private *dev_priv)
if (IS_CHERRYVIEW(dev_priv)) if (IS_CHERRYVIEW(dev_priv))
intel_uncore_write(uncore, DPINVGTT, DPINVGTT_STATUS_MASK_CHV); intel_uncore_write(uncore, DPINVGTT, DPINVGTT_STATUS_MASK_CHV);
else else
intel_uncore_write(uncore, DPINVGTT, DPINVGTT_STATUS_MASK); intel_uncore_write(uncore, DPINVGTT, DPINVGTT_STATUS_MASK_VLV);
i915_hotplug_interrupt_update_locked(dev_priv, 0xffffffff, 0); i915_hotplug_interrupt_update_locked(dev_priv, 0xffffffff, 0);
intel_uncore_write(uncore, PORT_HOTPLUG_STAT, intel_uncore_read(&dev_priv->uncore, PORT_HOTPLUG_STAT)); intel_uncore_write(uncore, PORT_HOTPLUG_STAT, intel_uncore_read(&dev_priv->uncore, PORT_HOTPLUG_STAT));
......
drivers/gpu/drm/i915/i915_reg.h
View file @ 7d938bc0
...@@ -6276,55 +6276,55 @@ enum { ...@@ -6276,55 +6276,55 @@ enum {
#define PIPE_STATUS_PORT_UNDERRUN_XELPD REG_BIT(26) #define PIPE_STATUS_PORT_UNDERRUN_XELPD REG_BIT(26)
#define VLV_DPFLIPSTAT _MMIO(VLV_DISPLAY_BASE + 0x70028) #define VLV_DPFLIPSTAT _MMIO(VLV_DISPLAY_BASE + 0x70028)
#define PIPEB_LINE_COMPARE_INT_EN (1 << 29) #define PIPEB_LINE_COMPARE_INT_EN REG_BIT(29)
#define PIPEB_HLINE_INT_EN (1 << 28) #define PIPEB_HLINE_INT_EN REG_BIT(28)
#define PIPEB_VBLANK_INT_EN (1 << 27) #define PIPEB_VBLANK_INT_EN REG_BIT(27)
#define SPRITED_FLIP_DONE_INT_EN (1 << 26) #define SPRITED_FLIP_DONE_INT_EN REG_BIT(26)
#define SPRITEC_FLIP_DONE_INT_EN (1 << 25) #define SPRITEC_FLIP_DONE_INT_EN REG_BIT(25)
#define PLANEB_FLIP_DONE_INT_EN (1 << 24) #define PLANEB_FLIP_DONE_INT_EN REG_BIT(24)
#define PIPE_PSR_INT_EN (1 << 22) #define PIPE_PSR_INT_EN REG_BIT(22)
#define PIPEA_LINE_COMPARE_INT_EN (1 << 21) #define PIPEA_LINE_COMPARE_INT_EN REG_BIT(21)
#define PIPEA_HLINE_INT_EN (1 << 20) #define PIPEA_HLINE_INT_EN REG_BIT(20)
#define PIPEA_VBLANK_INT_EN (1 << 19) #define PIPEA_VBLANK_INT_EN REG_BIT(19)
#define SPRITEB_FLIP_DONE_INT_EN (1 << 18) #define SPRITEB_FLIP_DONE_INT_EN REG_BIT(18)
#define SPRITEA_FLIP_DONE_INT_EN (1 << 17) #define SPRITEA_FLIP_DONE_INT_EN REG_BIT(17)
#define PLANEA_FLIPDONE_INT_EN (1 << 16) #define PLANEA_FLIPDONE_INT_EN REG_BIT(16)
#define PIPEC_LINE_COMPARE_INT_EN (1 << 13) #define PIPEC_LINE_COMPARE_INT_EN REG_BIT(13)
#define PIPEC_HLINE_INT_EN (1 << 12) #define PIPEC_HLINE_INT_EN REG_BIT(12)
#define PIPEC_VBLANK_INT_EN (1 << 11) #define PIPEC_VBLANK_INT_EN REG_BIT(11)
#define SPRITEF_FLIPDONE_INT_EN (1 << 10) #define SPRITEF_FLIPDONE_INT_EN REG_BIT(10)
#define SPRITEE_FLIPDONE_INT_EN (1 << 9) #define SPRITEE_FLIPDONE_INT_EN REG_BIT(9)
#define PLANEC_FLIPDONE_INT_EN (1 << 8) #define PLANEC_FLIPDONE_INT_EN REG_BIT(8)
#define DPINVGTT _MMIO(VLV_DISPLAY_BASE + 0x7002c) /* VLV/CHV only */ #define DPINVGTT _MMIO(VLV_DISPLAY_BASE + 0x7002c) /* VLV/CHV only */
#define SPRITEF_INVALID_GTT_INT_EN (1 << 27) #define DPINVGTT_EN_MASK_CHV REG_GENMASK(27, 16)
#define SPRITEE_INVALID_GTT_INT_EN (1 << 26) #define DPINVGTT_EN_MASK_VLV REG_GENMASK(23, 16)
#define PLANEC_INVALID_GTT_INT_EN (1 << 25) #define SPRITEF_INVALID_GTT_INT_EN REG_BIT(27)
#define CURSORC_INVALID_GTT_INT_EN (1 << 24) #define SPRITEE_INVALID_GTT_INT_EN REG_BIT(26)
#define CURSORB_INVALID_GTT_INT_EN (1 << 23) #define PLANEC_INVALID_GTT_INT_EN REG_BIT(25)
#define CURSORA_INVALID_GTT_INT_EN (1 << 22) #define CURSORC_INVALID_GTT_INT_EN REG_BIT(24)
#define SPRITED_INVALID_GTT_INT_EN (1 << 21) #define CURSORB_INVALID_GTT_INT_EN REG_BIT(23)
#define SPRITEC_INVALID_GTT_INT_EN (1 << 20) #define CURSORA_INVALID_GTT_INT_EN REG_BIT(22)
#define PLANEB_INVALID_GTT_INT_EN (1 << 19) #define SPRITED_INVALID_GTT_INT_EN REG_BIT(21)
#define SPRITEB_INVALID_GTT_INT_EN (1 << 18) #define SPRITEC_INVALID_GTT_INT_EN REG_BIT(20)
#define SPRITEA_INVALID_GTT_INT_EN (1 << 17) #define PLANEB_INVALID_GTT_INT_EN REG_BIT(19)
#define PLANEA_INVALID_GTT_INT_EN (1 << 16) #define SPRITEB_INVALID_GTT_INT_EN REG_BIT(18)
#define DPINVGTT_EN_MASK 0xff0000 #define SPRITEA_INVALID_GTT_INT_EN REG_BIT(17)
#define DPINVGTT_EN_MASK_CHV 0xfff0000 #define PLANEA_INVALID_GTT_INT_EN REG_BIT(16)
#define SPRITEF_INVALID_GTT_STATUS (1 << 11) #define DPINVGTT_STATUS_MASK_CHV REG_GENMASK(11, 0)
#define SPRITEE_INVALID_GTT_STATUS (1 << 10) #define DPINVGTT_STATUS_MASK_VLV REG_GENMASK(7, 0)
#define PLANEC_INVALID_GTT_STATUS (1 << 9) #define SPRITEF_INVALID_GTT_STATUS REG_BIT(11)
#define CURSORC_INVALID_GTT_STATUS (1 << 8) #define SPRITEE_INVALID_GTT_STATUS REG_BIT(10)
#define CURSORB_INVALID_GTT_STATUS (1 << 7) #define PLANEC_INVALID_GTT_STATUS REG_BIT(9)
#define CURSORA_INVALID_GTT_STATUS (1 << 6) #define CURSORC_INVALID_GTT_STATUS REG_BIT(8)
#define SPRITED_INVALID_GTT_STATUS (1 << 5) #define CURSORB_INVALID_GTT_STATUS REG_BIT(7)
#define SPRITEC_INVALID_GTT_STATUS (1 << 4) #define CURSORA_INVALID_GTT_STATUS REG_BIT(6)
#define PLANEB_INVALID_GTT_STATUS (1 << 3) #define SPRITED_INVALID_GTT_STATUS REG_BIT(5)
#define SPRITEB_INVALID_GTT_STATUS (1 << 2) #define SPRITEC_INVALID_GTT_STATUS REG_BIT(4)
#define SPRITEA_INVALID_GTT_STATUS (1 << 1) #define PLANEB_INVALID_GTT_STATUS REG_BIT(3)
#define PLANEA_INVALID_GTT_STATUS (1 << 0) #define SPRITEB_INVALID_GTT_STATUS REG_BIT(2)
#define DPINVGTT_STATUS_MASK 0xff #define SPRITEA_INVALID_GTT_STATUS REG_BIT(1)
#define DPINVGTT_STATUS_MASK_CHV 0xfff #define PLANEA_INVALID_GTT_STATUS REG_BIT(0)
#define DSPARB _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70030) #define DSPARB _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70030)
#define DSPARB_CSTART_MASK (0x7f << 7) #define DSPARB_CSTART_MASK (0x7f << 7)
......
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