Commit 7d9ef7f3 authored by Rob Herring's avatar Rob Herring

dt-bindings: riscv: Limit cpus schema to only check RiscV 'cpu' nodes

Matching on the 'cpus' node was a bad choice because the schema is
incorrectly applied to non-RiscV cpus nodes. As we now have a common cpus
schema which checks the general structure, it is also redundant to do so
in the Risc-V CPU schema.

The downside is one could conceivably mix different architecture's cpu
nodes or have typos in the compatible string. The latter problem pretty
much exists for every schema.
Acked-by: default avatarPaul Walmsley <paul.walmsley@sifive.com>
Signed-off-by: default avatarRob Herring <robh@kernel.org>
parent 15ffef1a
...@@ -10,97 +10,76 @@ maintainers: ...@@ -10,97 +10,76 @@ maintainers:
- Paul Walmsley <paul.walmsley@sifive.com> - Paul Walmsley <paul.walmsley@sifive.com>
- Palmer Dabbelt <palmer@sifive.com> - Palmer Dabbelt <palmer@sifive.com>
allOf:
- $ref: /schemas/cpus.yaml#
properties: properties:
$nodename: compatible:
const: cpus items:
description: Container of cpu nodes - enum:
- sifive,rocket0
'#address-cells': - sifive,e5
const: 1 - sifive,e51
description: | - sifive,u54-mc
A single unsigned 32-bit integer uniquely identifies each RISC-V - sifive,u54
hart in a system. (See the "reg" node under the "cpu" node, - sifive,u5
below). - const: riscv
description:
'#size-cells': Identifies that the hart uses the RISC-V instruction set
const: 0 and identifies the type of the hart.
mmu-type:
allOf:
- $ref: "/schemas/types.yaml#/definitions/string"
- enum:
- riscv,sv32
- riscv,sv39
- riscv,sv48
description:
Identifies the MMU address translation mode used on this
hart. These values originate from the RISC-V Privileged
Specification document, available from
https://riscv.org/specifications/
riscv,isa:
allOf:
- $ref: "/schemas/types.yaml#/definitions/string"
- enum:
- rv64imac
- rv64imafdc
description:
Identifies the specific RISC-V instruction set architecture
supported by the hart. These are documented in the RISC-V
User-Level ISA document, available from
https://riscv.org/specifications/
timebase-frequency:
type: integer
minimum: 1
description:
Specifies the clock frequency of the system timer in Hz.
This value is common to all harts on a single system image.
interrupt-controller:
type: object
description: Describes the CPU's local interrupt controller
patternProperties:
'^cpu@[0-9a-f]+$':
properties: properties:
compatible: '#interrupt-cells':
type: array const: 1
items:
- enum:
- sifive,rocket0
- sifive,e5
- sifive,e51
- sifive,u54-mc
- sifive,u54
- sifive,u5
- const: riscv
description:
Identifies that the hart uses the RISC-V instruction set
and identifies the type of the hart.
mmu-type:
allOf:
- $ref: "/schemas/types.yaml#/definitions/string"
- enum:
- riscv,sv32
- riscv,sv39
- riscv,sv48
description:
Identifies the MMU address translation mode used on this
hart. These values originate from the RISC-V Privileged
Specification document, available from
https://riscv.org/specifications/
riscv,isa:
allOf:
- $ref: "/schemas/types.yaml#/definitions/string"
- enum:
- rv64imac
- rv64imafdc
description:
Identifies the specific RISC-V instruction set architecture
supported by the hart. These are documented in the RISC-V
User-Level ISA document, available from
https://riscv.org/specifications/
timebase-frequency: compatible:
type: integer const: riscv,cpu-intc
minimum: 1
description:
Specifies the clock frequency of the system timer in Hz.
This value is common to all harts on a single system image.
interrupt-controller:
type: object
description: Describes the CPU's local interrupt controller
properties:
'#interrupt-cells':
const: 1
compatible:
const: riscv,cpu-intc
interrupt-controller: true
required: interrupt-controller: true
- '#interrupt-cells'
- compatible
- interrupt-controller
required: required:
- riscv,isa - '#interrupt-cells'
- timebase-frequency - compatible
- interrupt-controller - interrupt-controller
required:
- riscv,isa
- timebase-frequency
- interrupt-controller
examples: examples:
- | - |
// Example 1: SiFive Freedom U540G Development Kit // Example 1: SiFive Freedom U540G Development Kit
......
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