Commit 7dbdb53d authored by Jann Horn's avatar Jann Horn Committed by Greg Kroah-Hartman

USB: early: Handle AMD's spec-compliant identifiers, too

This fixes a bug that causes the USB3 early console to freeze after
printing a single line on AMD machines because it can't parse the
Transfer TRB properly.

The spec at
https://www.intel.com/content/dam/www/public/us/en/documents/technical-specifications/extensible-host-controler-interface-usb-xhci.pdf
says in section "4.5.1 Device Context Index" that the Context Index,
also known as Endpoint ID according to
section "1.6 Terms and Abbreviations", is normally computed as
`DCI = (Endpoint Number * 2) + Direction`, which matches the current
definitions of XDBC_EPID_OUT and XDBC_EPID_IN.

However, the numbering in a Debug Capability Context data structure is
supposed to be different:
Section "7.6.3.2 Endpoint Contexts and Transfer Rings" explains that a
Debug Capability Context data structure has the endpoints mapped to indices
0 and 1.

Change XDBC_EPID_OUT/XDBC_EPID_IN to the spec-compliant values, add
XDBC_EPID_OUT_INTEL/XDBC_EPID_IN_INTEL with Intel's incorrect values, and
let xdbc_handle_tx_event() handle both.

I have verified that with this patch applied, the USB3 early console works
on both an Intel and an AMD machine.

Fixes: aeb9dd1d ("usb/early: Add driver for xhci debug capability")
Cc: stable@vger.kernel.org
Signed-off-by: default avatarJann Horn <jannh@google.com>
Link: https://lore.kernel.org/r/20200401074619.8024-1-jannh@google.comSigned-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent 056ad39e
......@@ -728,19 +728,19 @@ static void xdbc_handle_tx_event(struct xdbc_trb *evt_trb)
case COMP_USB_TRANSACTION_ERROR:
case COMP_STALL_ERROR:
default:
if (ep_id == XDBC_EPID_OUT)
if (ep_id == XDBC_EPID_OUT || ep_id == XDBC_EPID_OUT_INTEL)
xdbc.flags |= XDBC_FLAGS_OUT_STALL;
if (ep_id == XDBC_EPID_IN)
if (ep_id == XDBC_EPID_IN || ep_id == XDBC_EPID_IN_INTEL)
xdbc.flags |= XDBC_FLAGS_IN_STALL;
xdbc_trace("endpoint %d stalled\n", ep_id);
break;
}
if (ep_id == XDBC_EPID_IN) {
if (ep_id == XDBC_EPID_IN || ep_id == XDBC_EPID_IN_INTEL) {
xdbc.flags &= ~XDBC_FLAGS_IN_PROCESS;
xdbc_bulk_transfer(NULL, XDBC_MAX_PACKET, true);
} else if (ep_id == XDBC_EPID_OUT) {
} else if (ep_id == XDBC_EPID_OUT || ep_id == XDBC_EPID_OUT_INTEL) {
xdbc.flags &= ~XDBC_FLAGS_OUT_PROCESS;
} else {
xdbc_trace("invalid endpoint id %d\n", ep_id);
......
......@@ -120,8 +120,22 @@ struct xdbc_ring {
u32 cycle_state;
};
#define XDBC_EPID_OUT 2
#define XDBC_EPID_IN 3
/*
* These are the "Endpoint ID" (also known as "Context Index") values for the
* OUT Transfer Ring and the IN Transfer Ring of a Debug Capability Context data
* structure.
* According to the "eXtensible Host Controller Interface for Universal Serial
* Bus (xHCI)" specification, section "7.6.3.2 Endpoint Contexts and Transfer
* Rings", these should be 0 and 1, and those are the values AMD machines give
* you; but Intel machines seem to use the formula from section "4.5.1 Device
* Context Index", which is supposed to be used for the Device Context only.
* Luckily the values from Intel don't overlap with those from AMD, so we can
* just test for both.
*/
#define XDBC_EPID_OUT 0
#define XDBC_EPID_IN 1
#define XDBC_EPID_OUT_INTEL 2
#define XDBC_EPID_IN_INTEL 3
struct xdbc_state {
u16 vendor;
......
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