s390/disassembler: Update instruction mnemonics to latest spec

Over the course of CPU generations a few instructions got extended,
changing their base mnemonic, while keeping the former as an extended
mnemonic. Update the instruction mnemonics in the disassembler to their
latest base mnemonic as documented in the latest IBM z/Architecture
Principles of Operation specification [1].

With the IBM z14 the base mnemonics of the following vector instructions
have been changed:
- Vector FP Load Lengthened (VFLL)
- Vector FP Load Rounded (VFLR)

With Message-Security-Assist Extension 5 Perform Pseudorandom Number
Operation (PPNO) has been renamed to Perform Random Number Operation
(PRNO).

With Vector Enhancements Facility 2 the base mnemonics of the following
vector instructions have been changed:
- Vector FP Convert from Fixed (VCFPS)
- Vector FP Convert from Logical (VCFPL)
- Vector FP Convert to Fixed (VCSFP)
- Vector FP Convert to Logical (VCLFP)

[1] IBM z/Architecture Principles of Operation, SA22-7832-13, IBM z16,
    https://publibfp.dhe.ibm.com/epubs/pdf/a227832d.pdfAcked-by: Vasily Gorbik <gor@linux.ibm.com>
Signed-off-by: Jens Remus <jremus@linux.ibm.com>
Signed-off-by: Vasily Gorbik <gor@linux.ibm.com>

arch/s390/tools/opcodes.txt

@@ -527,7 +527,7 @@ b938	sortl	RRE_RR
 b939	dfltcc	RRF_R0RR2
 b93a	kdsa	RRE_RR
 b93b	nnpa	RRE_00
-b93c	ppno	RRE_RR
+b93c	prno	RRE_RR
 b93e	kimd	RRE_RR
 b93f	klmd	RRE_RR
 b941	cfdtr	RRF_UURF
@@ -1017,12 +1017,12 @@ e7bb	vac	VRR_VVVU0V
 e7bc	vgfma	VRR_VVVU0V
 e7bd	vsbcbi	VRR_VVVU0V
 e7bf	vsbi	VRR_VVVU0V
-e7c0	vclgd	VRR_VV0UUU
-e7c1	vcdlg	VRR_VV0UUU
-e7c2	vcgd	VRR_VV0UUU
-e7c3	vcdg	VRR_VV0UUU
-e7c4	vlde	VRR_VV0UU2
-e7c5	vled	VRR_VV0UUU
+e7c0	vclfp	VRR_VV0UUU
+e7c1	vcfpl	VRR_VV0UUU
+e7c2	vcsfp	VRR_VV0UUU
+e7c3	vcfps	VRR_VV0UUU
+e7c4	vfll	VRR_VV0UU2
+e7c5	vflr	VRR_VV0UUU
 e7c7	vfi	VRR_VV0UUU
 e7ca	wfk	VRR_VV0UU2
 e7cb	wfc	VRR_VV0UU2