PPC32: Update the support for the IBM 40x embedded PowerPC chips and boards.

Some of this comes from recent work in the 2_4_devel tree, including the
conversion to using an array (core_ocp[]) to describe on-chip peripherals
in a standard format.  The other major change is to give the board file
control early on in the boot and let it call back to generic 4xx routines
rather than vice-versa.

arch/ppc/platforms/4xx/ash.c

 /*
  *
- *    Copyright 2001 MontaVista Software Inc.
+ *    Copyright 2001-2002 MontaVista Software Inc.
  *        <akuster@mvista.com>
  *	IBM NP405H ash eval board
- *
  */
 #include <linux/config.h>
 #include <linux/init.h>
@@ -13,9 +12,12 @@
 #include <asm/machdep.h>
 #include <asm/pci-bridge.h>
 #include <asm/io.h>
-
-#ifdef CONFIG_PPC_RTC
 #include <asm/todc.h>
+
+#ifdef DEBUG
+#define DBG(x...) printk(x)
+#else
+#define DBG(x...)
 #endif
 
 void *ash_rtc_base;
@@ -27,77 +29,211 @@ int __init
 ppc405_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
 {
 	static char pci_irq_table[][4] =
-	/*
-	 *      PCI IDSEL/INTPIN->INTLINE
-	 *      A       B       C       D
-	 */
+	    /*
+	     *      PCI IDSEL/INTPIN->INTLINE
+	     *      A       B       C       D
+	     */
 	{
-		{28, 28, 28, 28},	/* IDSEL 1 - PCI slot 1 */
-		{29, 29, 29, 29},	/* IDSEL 2 - PCI slot 2 */
-		{30, 30, 30, 30},	/* IDSEL 3 - PCI slot 3 */
-		{31, 31, 31, 31},	/* IDSEL 4 - PCI slot 4 */
+		{24, 24, 24, 24},	/* IDSEL 1 - PCI slot 1 */
+		{25, 25, 25, 25},	/* IDSEL 2 - PCI slot 2 */
+		{26, 26, 26, 26},	/* IDSEL 3 - PCI slot 3 */
+		{27, 27, 27, 27},	/* IDSEL 4 - PCI slot 4 */
 	};
 
 	const long min_idsel = 1, max_idsel = 4, irqs_per_slot = 4;
 	return PCI_IRQ_TABLE_LOOKUP;
-};
+}
 
 void __init
-board_setup_arch(void)
+ash_setup_arch(void)
 {
+	bd_t *bip = &__res;
 
-	bd_t *bip = (bd_t *)__res;
+	ppc4xx_setup_arch();
 
-#ifdef CONFIG_PPC_RTC
-        /* RTC step for the walnut */
-        ash_rtc_base = (void *) ASH_RTC_VADDR;
-	TODC_INIT(TODC_TYPE_DS1743, ash_rtc_base, ash_rtc_base,ash_rtc_base, 8);
-#endif /* CONFIG_PPC_RTC */
-#define CONFIG_DEBUG_BRINGUP
 #ifdef CONFIG_DEBUG_BRINGUP
+	int i;
 	printk("\n");
 	printk("machine\t: %s\n", PPC4xx_MACHINE_NAME);
 	printk("\n");
-	printk("bi_s_version\t %s\n",      bip->bi_s_version);
-	printk("bi_r_version\t %s\n",      bip->bi_r_version);
-	printk("bi_memsize\t 0x%8.8x\t %dMBytes\n", bip->bi_memsize,bip->bi_memsize/(1024*1000));
-	printk("bi_enetaddr %d\t %2.2x%2.2x%2.2x-%2.2x%2.2x%2.2x\n", 0,
-	bip->bi_enetaddr[0][0], bip->bi_enetaddr[0][1],
-	bip->bi_enetaddr[0][2], bip->bi_enetaddr[0][3],
-	bip->bi_enetaddr[0][4], bip->bi_enetaddr[0][5]);
-
-	printk("bi_enetaddr %d\t %2.2x%2.2x%2.2x-%2.2x%2.2x%2.2x\n", 1,
-	bip->bi_enetaddr[1][0], bip->bi_enetaddr[1][1],
-	bip->bi_enetaddr[1][2], bip->bi_enetaddr[1][3],
-	bip->bi_enetaddr[1][4], bip->bi_enetaddr[1][5]);
+	printk("bi_s_version\t %s\n", bip->bi_s_version);
+	printk("bi_r_version\t %s\n", bip->bi_r_version);
+	printk("bi_memsize\t 0x%8.8x\t %dMBytes\n", bip->bi_memsize,
+	       bip->bi_memsize / (1024 * 1000));
+	for (i = 0; i < EMAC_NUMS; i++) {
+		printk("bi_enetaddr %d\t %2.2x%2.2x%2.2x-%2.2x%2.2x%2.2x\n", i,
+		       bip->bi_enetaddr[i][0], bip->bi_enetaddr[i][1],
+		       bip->bi_enetaddr[i][2], bip->bi_enetaddr[i][3],
+		       bip->bi_enetaddr[i][4], bip->bi_enetaddr[i][5]);
+	}
+	printk("bi_pci_enetaddr %d\t %2.2x%2.2x%2.2x-%2.2x%2.2x%2.2x\n", 0,
+	       bip->bi_pci_enetaddr[0], bip->bi_pci_enetaddr[1],
+	       bip->bi_pci_enetaddr[2], bip->bi_pci_enetaddr[3],
+	       bip->bi_pci_enetaddr[4], bip->bi_pci_enetaddr[5]);
 
 	printk("bi_intfreq\t 0x%8.8x\t clock:\t %dMhz\n",
-	       bip->bi_intfreq, bip->bi_intfreq/ 1000000);
+	       bip->bi_intfreq, bip->bi_intfreq / 1000000);
 
 	printk("bi_busfreq\t 0x%8.8x\t plb bus clock:\t %dMHz\n",
-		bip->bi_busfreq, bip->bi_busfreq / 1000000 );
+	       bip->bi_busfreq, bip->bi_busfreq / 1000000);
 	printk("bi_pci_busfreq\t 0x%8.8x\t pci bus clock:\t %dMHz\n",
-	       bip->bi_pci_busfreq, bip->bi_pci_busfreq/1000000);
+	       bip->bi_pci_busfreq, bip->bi_pci_busfreq / 1000000);
 
 	printk("\n");
 #endif
+	/* RTC step for ash */
+	ash_rtc_base = (void *) ASH_RTC_VADDR;
+	TODC_INIT(TODC_TYPE_DS1743, ash_rtc_base, ash_rtc_base, ash_rtc_base,
+		  8);
 }
 
 void __init
-board_io_mapping(void)
+bios_fixup(struct pci_controller *hose, struct pcil0_regs *pcip)
 {
-	io_block_mapping(ASH_RTC_VADDR,
-		ASH_RTC_PADDR, ASH_RTC_SIZE, _PAGE_IO);
+
+	unsigned int bar_response, bar;
+	/*
+	 * Expected PCI mapping:
+	 *
+	 *  PLB addr             PCI memory addr
+	 *  ---------------------       ---------------------
+	 *  0000'0000 - 7fff'ffff <---  0000'0000 - 7fff'ffff
+	 *  8000'0000 - Bfff'ffff --->  8000'0000 - Bfff'ffff
+	 *
+	 *  PLB addr             PCI io addr
+	 *  ---------------------       ---------------------
+	 *  e800'0000 - e800'ffff --->  0000'0000 - 0001'0000
+	 *
+	 * The following code is simplified by assuming that the bootrom
+	 * has been well behaved in following this mapping.
+	 */
+
+#ifdef DEBUG
+	int i;
+
+	printk("ioremap PCLIO_BASE = 0x%x\n", pcip);
+	printk("PCI bridge regs before fixup \n");
+	for (i = 0; i <= 2; i++) {
+		printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].ma)));
+		printk(" pmm%dla\t0x%x\n", i, in_le32(&(pcip->pmm[i].la)));
+		printk(" pmm%dpcila\t0x%x\n", i,
+		       in_le32(&(pcip->pmm[i].pcila)));
+		printk(" pmm%dpciha\t0x%x\n", i,
+		       in_le32(&(pcip->pmm[i].pciha)));
+	}
+	printk(" ptm1ms\t0x%x\n", in_le32(&(pcip->ptm1ms)));
+	printk(" ptm1la\t0x%x\n", in_le32(&(pcip->ptm1la)));
+	printk(" ptm2ms\t0x%x\n", in_le32(&(pcip->ptm2ms)));
+	printk(" ptm2la\t0x%x\n", in_le32(&(pcip->ptm2la)));
+	for (bar = PCI_BASE_ADDRESS_1; bar <= PCI_BASE_ADDRESS_2; bar += 4) {
+		early_read_config_dword(hose, hose->first_busno,
+					PCI_FUNC(hose->first_busno), bar,
+					&bar_response);
+		DBG("BUS %d, device %d, Function %d bar 0x%8.8x is 0x%8.8x\n",
+		    hose->first_busno, PCI_SLOT(hose->first_busno),
+		    PCI_FUNC(hose->first_busno), bar, bar_response);
+	}
+
+#endif
+	if (ppc_md.progress)
+		ppc_md.progress("bios_fixup(): enter", 0x800);
+
+	/* added for IBM boot rom version 1.15 bios bar changes  -AK */
+
+	/* Disable region first */
+	out_le32((void *) &(pcip->pmm[0].ma), 0x00000000);
+	/* PLB starting addr, PCI: 0x80000000 */
+	out_le32((void *) &(pcip->pmm[0].la), 0x80000000);
+	/* PCI start addr, 0x80000000 */
+	out_le32((void *) &(pcip->pmm[0].pcila), PPC405_PCI_MEM_BASE);
+	/* 512MB range of PLB to PCI */
+	out_le32((void *) &(pcip->pmm[0].pciha), 0x00000000);
+	/* Enable no pre-fetch, enable region */
+	out_le32((void *) &(pcip->pmm[0].ma), ((0xffffffff -
+						(PPC405_PCI_UPPER_MEM -
+						 PPC405_PCI_MEM_BASE)) | 0x01));
+
+	/* Disable region one */
+	out_le32((void *) &(pcip->pmm[1].ma), 0x00000000);
+	out_le32((void *) &(pcip->pmm[1].la), 0x00000000);
+	out_le32((void *) &(pcip->pmm[1].pcila), 0x00000000);
+	out_le32((void *) &(pcip->pmm[1].pciha), 0x00000000);
+	out_le32((void *) &(pcip->pmm[1].ma), 0x00000000);
+
+	/* Disable region two */
+	out_le32((void *) &(pcip->pmm[2].ma), 0x00000000);
+	out_le32((void *) &(pcip->pmm[2].la), 0x00000000);
+	out_le32((void *) &(pcip->pmm[2].pcila), 0x00000000);
+	out_le32((void *) &(pcip->pmm[2].pciha), 0x00000000);
+	out_le32((void *) &(pcip->pmm[2].ma), 0x00000000);
+	
+	/* Enable PTM1 and PTM2, mapped to PLB address 0. */
+
+	out_le32((void *) &(pcip->ptm1la), 0x00000000);
+	out_le32((void *) &(pcip->ptm1ms), 0x00000001);
+	out_le32((void *) &(pcip->ptm2la), 0x00000000);
+	out_le32((void *) &(pcip->ptm2ms), 0x00000001);
+
+	/* Write zero to PTM1 BAR. */
+
+	early_write_config_dword(hose, hose->first_busno,
+				 PCI_FUNC(hose->first_busno), 
+				 PCI_BASE_ADDRESS_1,
+				 0x00000000);
+
+	/* Disable PTM2 (unused) */
+
+	out_le32((void *) &(pcip->ptm2la), 0x00000000);
+	out_le32((void *) &(pcip->ptm2ms), 0x00000000);
+
+	/* end work arround */
+	if (ppc_md.progress)
+		ppc_md.progress("bios_fixup(): done", 0x800);
+
+#ifdef DEBUG
+	printk("PCI bridge regs after fixup \n");
+	for (i = 0; i <= 2; i++) {
+		printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].ma)));
+		printk(" pmm%dla\t0x%x\n", i, in_le32(&(pcip->pmm[i].la)));
+		printk(" pmm%dpcila\t0x%x\n", i,
+		       in_le32(&(pcip->pmm[i].pcila)));
+		printk(" pmm%dpciha\t0x%x\n", i,
+		       in_le32(&(pcip->pmm[i].pciha)));
+	}
+	printk(" ptm1ms\t0x%x\n", in_le32(&(pcip->ptm1ms)));
+	printk(" ptm1la\t0x%x\n", in_le32(&(pcip->ptm1la)));
+	printk(" ptm2ms\t0x%x\n", in_le32(&(pcip->ptm2ms)));
+	printk(" ptm2la\t0x%x\n", in_le32(&(pcip->ptm2la)));
+
+	for (bar = PCI_BASE_ADDRESS_1; bar <= PCI_BASE_ADDRESS_2; bar += 4) {
+		early_read_config_dword(hose, hose->first_busno,
+					PCI_FUNC(hose->first_busno), bar,
+					&bar_response);
+		DBG("BUS %d, device %d, Function %d bar 0x%8.8x is 0x%8.8x\n",
+		    hose->first_busno, PCI_SLOT(hose->first_busno),
+		    PCI_FUNC(hose->first_busno), bar, bar_response);
+	}
+
+
+#endif
 }
+
 void __init
-board_setup_irq(void)
+ash_map_io(void)
 {
-
+	ppc4xx_map_io();
+	io_block_mapping(ASH_RTC_VADDR, ASH_RTC_PADDR, ASH_RTC_SIZE, _PAGE_IO);
 }
 
 void __init
-board_init(void)
+platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
+	      unsigned long r6, unsigned long r7)
 {
+	ppc4xx_init(r3, r4, r5, r6, r7);
+
+	ppc_md.setup_arch = ash_setup_arch;
+	ppc_md.setup_io_mappings = ash_map_io;
+
 #ifdef CONFIG_PPC_RTC
 	ppc_md.time_init = todc_time_init;
 	ppc_md.set_rtc_time = todc_set_rtc_time;

arch/ppc/platforms/4xx/ash.h

 /*
  *
  *
- *    Copyright 2000 MontaVista Software Inc.
+ *    Copyright 2000-2002  MontaVista Software Inc.
  * 	Author: MontaVista Software, Inc.
  *         	akuster@mvista.com or source@mvista.com
  *
@@ -17,7 +17,7 @@
 #ifdef __KERNEL__
 #ifndef __ASM_ASH_H__
 #define __ASM_ASH_H__
-#include <platforms/4xx/ibm_ocp.h>
+#include <asm/ibm_ocp.h>
 #include <platforms/4xx/ibmnp405h.h>
 
 #ifndef __ASSEMBLY__
@@ -32,7 +32,7 @@ typedef struct board_info {
 	unsigned char	 bi_s_version[4];	/* Version of this structure */
 	unsigned char	 bi_r_version[30];	/* Version of the IBM ROM */
 	unsigned int	 bi_memsize;		/* DRAM installed, in bytes */
-	unsigned char	 bi_enetaddr[EMAC_NUMS][6];	/* Local Ethernet MAC address */
+	unsigned char	 bi_enetaddr[4][6];	/* Local Ethernet MAC address */
 	unsigned char	 bi_pci_enetaddr[6];
 	unsigned int	 bi_intfreq;		/* Processor speed, in Hz */
 	unsigned int	 bi_busfreq;		/* PLB Bus speed, in Hz */
@@ -76,7 +76,7 @@ extern  void *ash_rtc_base;
 #define BASE_BAUD		691200
 #endif
 
-#define PPC4xx_MACHINE_NAME "IBM NP405H Ceder"
+#define PPC4xx_MACHINE_NAME "IBM NP405H Ash"
 
 extern char pci_irq_table[][4];
 

arch/ppc/platforms/4xx/cedar.c

@@ -11,73 +11,75 @@
 #include <asm/machdep.h>
 
 #include <asm/io.h>
-
-#ifdef CONFIG_PPC_RTC
 #include <asm/todc.h>
-#endif
 
-void *ceder_rtc_base;
+void *cedar_rtc_base;
 
 void __init
-board_setup_arch(void)
+cedar_setup_arch(void)
 {
+	bd_t *bip = &__res;
 
-	bd_t *bip = (bd_t *)__res;
+	/* RTC step for the walnut */
+	cedar_rtc_base = (void *) CEDAR_RTC_VADDR;
+	TODC_INIT(TODC_TYPE_DS1743, cedar_rtc_base, cedar_rtc_base,
+		  cedar_rtc_base, 8);
 
-#ifdef CONFIG_PPC_RTC
-        /* RTC step for the walnut */
-        ceder_rtc_base = (void *) CEDER_RTC_VADDR;
-	TODC_INIT(TODC_TYPE_DS1743, ceder_rtc_base, ceder_rtc_base,ceder_rtc_base, 8);
-#endif /* CONFIG_PPC_RTC */
-#define CONFIG_DEBUG_BRINGUP
 #ifdef CONFIG_DEBUG_BRINGUP
 	printk("\n");
 	printk("machine\t: %s\n", PPC4xx_MACHINE_NAME);
 	printk("\n");
-	printk("bi_s_version\t %s\n",      bip->bi_s_version);
-	printk("bi_r_version\t %s\n",      bip->bi_r_version);
-	printk("bi_memsize\t 0x%8.8x\t %dMBytes\n", bip->bi_memsize,bip->bi_memsize/(1024*1000));
+	printk("bi_s_version\t %s\n", bip->bi_s_version);
+	printk("bi_r_version\t %s\n", bip->bi_r_version);
+	printk("bi_memsize\t 0x%8.8x\t %dMBytes\n", bip->bi_memsize,
+	       bip->bi_memsize / (1024 * 1000));
 	printk("bi_enetaddr %d\t %2.2x%2.2x%2.2x-%2.2x%2.2x%2.2x\n", 0,
-	bip->bi_enetaddr[0][0], bip->bi_enetaddr[0][1],
-	bip->bi_enetaddr[0][2], bip->bi_enetaddr[0][3],
-	bip->bi_enetaddr[0][4], bip->bi_enetaddr[0][5]);
+	       bip->bi_enetaddr[0][0], bip->bi_enetaddr[0][1],
+	       bip->bi_enetaddr[0][2], bip->bi_enetaddr[0][3],
+	       bip->bi_enetaddr[0][4], bip->bi_enetaddr[0][5]);
 
 	printk("bi_enetaddr %d\t %2.2x%2.2x%2.2x-%2.2x%2.2x%2.2x\n", 1,
-	bip->bi_enetaddr[1][0], bip->bi_enetaddr[1][1],
-	bip->bi_enetaddr[1][2], bip->bi_enetaddr[1][3],
-	bip->bi_enetaddr[1][4], bip->bi_enetaddr[1][5]);
+	       bip->bi_enetaddr[1][0], bip->bi_enetaddr[1][1],
+	       bip->bi_enetaddr[1][2], bip->bi_enetaddr[1][3],
+	       bip->bi_enetaddr[1][4], bip->bi_enetaddr[1][5]);
 
 	printk("bi_intfreq\t 0x%8.8x\t clock:\t %dMhz\n",
-	       bip->bi_intfreq, bip->bi_intfreq/ 1000000);
+	       bip->bi_intfreq, bip->bi_intfreq / 1000000);
 
 	printk("bi_busfreq\t 0x%8.8x\t plb bus clock:\t %dMHz\n",
-		bip->bi_busfreq, bip->bi_busfreq / 1000000 );
+	       bip->bi_busfreq, bip->bi_busfreq / 1000000);
 	printk("bi_pci_busfreq\t 0x%8.8x\t pci bus clock:\t %dMHz\n",
-	       bip->bi_pci_busfreq, bip->bi_pci_busfreq/1000000);
+	       bip->bi_pci_busfreq, bip->bi_pci_busfreq / 1000000);
 
 	printk("\n");
 #endif
-}
 
-void __init
-board_io_mapping(void)
-{
-	io_block_mapping(CEDER_RTC_VADDR,
-		CEDER_RTC_PADDR, CEDER_RTC_SIZE, _PAGE_IO);
+	/* Identify the system */
+	printk
+	    ("IBM Cedar port (C) 2002 MontaVista Software, Inc. (source@mvista.com)\n");
+
 }
+
 void __init
-board_setup_irq(void)
+cedar_map_io(void)
 {
+	ppc4xx_map_io();
+	io_block_mapping(CEDAR_RTC_VADDR,
+			 CEDAR_RTC_PADDR, CEDAR_RTC_SIZE, _PAGE_IO);
 }
 
 void __init
-board_init(void)
+platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
+	      unsigned long r6, unsigned long r7)
 {
-#ifdef CONFIG_PPC_RTC
+	ppc4xx_init(r3, r4, r5, r6, r7);
+
+	ppc_md.setup_arch = cedar_setup_arch;
+	ppc_md.setup_io_mappings = cedar_map_io;
+
 	ppc_md.time_init = todc_time_init;
 	ppc_md.set_rtc_time = todc_set_rtc_time;
 	ppc_md.get_rtc_time = todc_get_rtc_time;
 	ppc_md.nvram_read_val = todc_direct_read_val;
 	ppc_md.nvram_write_val = todc_direct_write_val;
-#endif
 }

arch/ppc/platforms/4xx/cedar.h

@@ -5,24 +5,24 @@
  * 	Author: MontaVista Software, Inc.
  *         	akuster@mvista.com or source@mvista.com
  *
- *    Module name: ceder.h
+ *    Module name: cedar.h
  *
  *    Description:
  *      Macros, definitions, and data structures specific to the IBM PowerPC
- *      Ceder eval board.
+ *      Cedar eval board.
  *
  *
  */
 
 #ifdef __KERNEL__
-#ifndef __ASM_CEDER_H__
-#define __ASM_CEDER_H__
+#ifndef __ASM_CEDAR_H__
+#define __ASM_CEDAR_H__
 #include <platforms/4xx/ibmnp405l.h>
 
 #ifndef __ASSEMBLY__
 /*
  * Data structure defining board information maintained by the boot
- * ROM on IBM's "Ceder" evaluation board. An effort has been made to
+ * ROM on IBM's "Cedar" evaluation board. An effort has been made to
  * keep the field names consistent with the 8xx 'bd_t' board info
  * structures.
  */
@@ -31,7 +31,7 @@ typedef struct board_info {
 	unsigned char	 bi_s_version[4];	/* Version of this structure */
 	unsigned char	 bi_r_version[30];	/* Version of the IBM ROM */
 	unsigned int	 bi_memsize;		/* DRAM installed, in bytes */
-	unsigned char	 bi_enetaddr[EMAC_NUMS][6];	/* Local Ethernet MAC address */
+	unsigned char	 bi_enetaddr[2][6];	/* Local Ethernet MAC address */
 	unsigned char	 bi_pci_mac[6];
 	unsigned int	 bi_intfreq;		/* Processor speed, in Hz */
 	unsigned int	 bi_busfreq;		/* PLB Bus speed, in Hz */
@@ -42,32 +42,22 @@ typedef struct board_info {
 */
 #define bi_tbfreq bi_intfreq
 
-/* Memory map for the IBM "Ceder" NP405 evaluation board.
+/* Memory map for the IBM "Cedar" NP405 evaluation board.
  */
 
-extern  void *ceder_rtc_base;
-#define CEDER_RTC_PADDR		((uint)0xf0000000)
-#define CEDER_RTC_VADDR		CEDER_RTC_PADDR
-#define CEDER_RTC_SIZE		((uint)8*1024)
+extern  void *cedar_rtc_base;
+#define CEDAR_RTC_PADDR		((uint)0xf0000000)
+#define CEDAR_RTC_VADDR		CEDAR_RTC_PADDR
+#define CEDAR_RTC_SIZE		((uint)8*1024)
 
 
 /* Early initialization address mapping for block_io.
  * Standard 405GP map.
  */
-#define PPC4xx_PCI_IO_PADDR	((uint)PPC405_PCI_PHY_IO_BASE)
-#define PPC4xx_PCI_IO_VADDR	PPC4xx_PCI_IO_PADDR
-#define PPC4xx_PCI_IO_SIZE	((uint)64*1024)
-#define PPC4xx_PCI_CFG_PADDR	((uint)PPC405_PCI_CONFIG_ADDR)
-#define PPC4xx_PCI_CFG_VADDR	PPC4xx_PCI_CFG_PADDR
-#define PPC4xx_PCI_CFG_SIZE	((uint)4*1024)
-#define PPC4xx_PCI_LCFG_PADDR	((uint)0xef400000)
-#define PPC4xx_PCI_LCFG_VADDR	PPC4xx_PCI_LCFG_PADDR
-#define PPC4xx_PCI_LCFG_SIZE	((uint)4*1024)
 #define PPC4xx_ONB_IO_PADDR	((uint)0xef600000)
 #define PPC4xx_ONB_IO_VADDR	PPC4xx_ONB_IO_PADDR
 #define PPC4xx_ONB_IO_SIZE	((uint)4*1024)
 
-#define NR_BOARD_IRQS 32
 
 #ifdef CONFIG_PPC405GP_INTERNAL_CLOCK
 #define BASE_BAUD		201600
@@ -75,11 +65,11 @@ extern  void *ceder_rtc_base;
 #define BASE_BAUD		691200
 #endif
 
-#define PPC4xx_MACHINE_NAME "IBM NP405L Ceder"
+#define PPC4xx_MACHINE_NAME "IBM NP405L Cedar"
 
-extern char pci_irq_table[][4];
+ 
 
 
 #endif /* !__ASSEMBLY__ */
-#endif /* __ASM_CEDER_H__ */
+#endif /* __ASM_CEDAR_H__ */
 #endif /* __KERNEL__ */

arch/ppc/platforms/4xx/cpci405.c

@@ -13,9 +13,6 @@
  * Free Software Foundation;  either version 2 of the  License, or (at your
  * option) any later version.
  *
- *	History: 11/09/2001 - armin
- *       added board_init to add in additional instuctions needed during platfrom_init
- *
  */
 
 #include <linux/config.h>
@@ -26,6 +23,8 @@
 #include <asm/machdep.h>
 #include <asm/todc.h>
 
+void *cpci405_nvram; 
+
 /*
  * Some IRQs unique to CPCI-405.
  */
@@ -51,28 +50,31 @@ ppc405_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
 };
 
 void __init
-board_setup_arch(void)
+cpci405_setup_arch(void)
 {
+	ppc4xx_setup_arch();
+	TODC_INIT(TODC_TYPE_MK48T35, cpci405_nvram, cpci405_nvram, cpci405_nvram, 8);
 }
 
 void __init
-board_io_mapping(void)
+cpci405_map_io(void)
 {
+	ppc4xx_map_io();
+	cpci405_nvram = ioremap(CPCI405_NVRAM_PADDR, CPCI405_NVRAM_SIZE);
 }
 
 void __init
-board_setup_irq(void)
+platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
+	      unsigned long r6, unsigned long r7)
 {
-}
+	ppc4xx_init(r3, r4, r5, r6, r7);
+
+	ppc_md.setup_arch = cpci405_setup_arch;
+	ppc_md.setup_io_mappings = cpci405_map_io;
 
-void __init
-board_init(void)
-{
-#ifdef CONFIG_PPC_RTC
 	ppc_md.time_init = todc_time_init;
 	ppc_md.set_rtc_time = todc_set_rtc_time;
 	ppc_md.get_rtc_time = todc_get_rtc_time;
 	ppc_md.nvram_read_val = todc_direct_read_val;
 	ppc_md.nvram_write_val = todc_direct_write_val;
-#endif
 }

arch/ppc/platforms/4xx/cpci405.h

@@ -4,35 +4,25 @@
  * Copyright (c) 2001 Stefan Roese (stefan.roese@esd-electronics.com)
  */
 
+#ifdef __KERNEL__
 #ifndef __ASM_CPCI405_H__
 #define __ASM_CPCI405_H__
 
 #include <linux/config.h>
 
 /* We have a 405GP core */
-#include <platforms/ibm405gp.h>
+#include <platforms/4xx/ibm405gp.h>
 
 #include <asm/ppcboot.h>
 
+#ifndef __ASSEMBLY__
 /* Some 4xx parts use a different timebase frequency from the internal clock.
 */
 #define bi_tbfreq bi_intfreq
 
-/* Early initialization address mapping for block_io.
- * Standard 405GP map.
- */
-#define PPC4xx_PCI_IO_PADDR	((uint)PPC405_PCI_PHY_IO_BASE)
-#define PPC4xx_PCI_IO_VADDR	PPC4xx_PCI_IO_PADDR
-#define PPC4xx_PCI_IO_SIZE	((uint)64*1024)
-#define PPC4xx_PCI_CFG_PADDR	((uint)PPC405_PCI_CONFIG_ADDR)
-#define PPC4xx_PCI_CFG_VADDR	PPC4xx_PCI_CFG_PADDR
-#define PPC4xx_PCI_CFG_SIZE	((uint)4*1024)
-#define PPC4xx_PCI_LCFG_PADDR	((uint)0xef400000)
-#define PPC4xx_PCI_LCFG_VADDR	PPC4xx_PCI_LCFG_PADDR
-#define PPC4xx_PCI_LCFG_SIZE	((uint)4*1024)
-#define PPC4xx_ONB_IO_PADDR	((uint)0xef600000)
-#define PPC4xx_ONB_IO_VADDR	PPC4xx_ONB_IO_PADDR
-#define PPC4xx_ONB_IO_SIZE	((uint)4*1024)
+/* Map for the NVRAM space */
+#define CPCI405_NVRAM_PADDR	((uint)0xf0200000)
+#define CPCI405_NVRAM_SIZE	((uint)32*1024)
 
 #ifdef CONFIG_PPC405GP_INTERNAL_CLOCK
 #define BASE_BAUD		201600
@@ -42,4 +32,6 @@
 
 #define PPC4xx_MACHINE_NAME "esd CPCI-405"
 
+#endif /* !__ASSEMBLY__ */
 #endif	/* __ASM_CPCI405_H__ */
+#endif /* __KERNEL__ */

arch/ppc/platforms/4xx/ep405.c

@@ -2,7 +2,7 @@
  *    Copyright 2001 MontaVista Software Inc.
  *        <mlocke@mvista.com>
  *
- * 	Not much is needed for the Embedded Planet 405gp board
+ * 	Not much needed for the Embedded Planet 405gp board
  *
  */
 #include <linux/config.h>
@@ -12,7 +12,7 @@
 #include <asm/pci-bridge.h>
 #include <asm/machdep.h>
 #include <asm/todc.h>
-#include <platforms/4xx/ibm_ocp.h>
+#include <asm/ibm_ocp_pci.h>
 
 #undef DEBUG
 #ifdef DEBUG
@@ -33,7 +33,6 @@ static struct {
 	{0x07, 0x0E, 25},		/* EP405PC: USB */
 #endif
 };
-#define EP405_DEVTABLE_SIZE (sizeof(ep405_devtable)/sizeof(ep405_devtable[0]))
 
 int __init
 ppc405_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
@@ -42,7 +41,7 @@ ppc405_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
 
 	/* AFAICT this is only called a few times during PCI setup, so
 	   performance is not critical */
-	for (i = 0; i < EP405_DEVTABLE_SIZE; i++) {
+	for (i = 0; i < ARRAY_SIZE(ep405_devtable); i++) {
 		if (idsel == ep405_devtable[i].pci_idsel)
 			return ep405_devtable[i].irq;
 	}
@@ -50,11 +49,11 @@ ppc405_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
 };
 
 void __init
-board_setup_arch(void)
+ep405_setup_arch(void)
 {
-	bd_t *bip = (bd_t *) __res;
+	ppc4xx_setup_arch();
 
-	if (bip->bi_nvramsize == 512*1024) {
+	if (__res.bi_nvramsize == 512*1024) {
 		/* FIXME: we should properly handle NVRTCs of different sizes */
 		TODC_INIT(TODC_TYPE_DS1557, ep405_nvram, ep405_nvram, ep405_nvram, 8);
 	}
@@ -128,9 +127,11 @@ bios_fixup(struct pci_controller *hose, struct pcil0_regs *pcip)
 }
 
 void __init
-board_io_mapping(void)
+ep405_map_io(void)
 {
-	bd_t *bip = (bd_t *) __res;
+	bd_t *bip = &__res;
+
+	ppc4xx_map_io();
 
 	ep405_bcsr = ioremap(EP405_BCSR_PADDR, EP405_BCSR_SIZE);
 
@@ -140,10 +141,12 @@ board_io_mapping(void)
 }
 
 void __init
-board_setup_irq(void)
+ep405_init_IRQ(void)
 {
 	int i;
 
+	ppc4xx_init_IRQ();
+
 	/* Workaround for a bug in the firmware it incorrectly sets
 	   the IRQ polarities for XIRQ0 and XIRQ1 */
 	mtdcr(DCRN_UIC_PR(DCRN_UIC0_BASE), 0xffffff80); /* set the polarity */
@@ -153,7 +156,7 @@ board_setup_irq(void)
 	writeb(0xf0, ep405_bcsr+10);
 
 	/* Set up IRQ routing */
-	for (i = 0; i < EP405_DEVTABLE_SIZE; i++) {
+	for (i = 0; i < ARRAY_SIZE(ep405_devtable); i++) {
 		if ( (ep405_devtable[i].irq >= 25)
 		     && (ep405_devtable[i].irq) <= 31) {
 			writeb(ep405_devtable[i].cpld_xirq_select, ep405_bcsr+5);
@@ -163,22 +166,23 @@ board_setup_irq(void)
 }
 
 void __init
-board_init(void)
+platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
+	      unsigned long r6, unsigned long r7)
 {
-#ifdef CONFIG_PPC_RTC
-	bd_t *bip = (bd_t *) __res;
+	ppc4xx_init(r3, r4, r5, r6, r7);
+
+	ppc_md.setup_arch = ep405_setup_arch;
+	ppc_md.setup_io_mappings = ep405_map_io;
+	ppc_md.init_IRQ = ep405_init_IRQ;
 
-	/* FIXME: we should be able to access the NVRAM even if PPC_RTC is not configured */
 	ppc_md.nvram_read_val = todc_direct_read_val;
 	ppc_md.nvram_write_val = todc_direct_write_val;
 
-	if (bip->bi_nvramsize == 512*1024) {
+	if (__res.bi_nvramsize == 512*1024) {
 		ppc_md.time_init = todc_time_init;
 		ppc_md.set_rtc_time = todc_set_rtc_time;
 		ppc_md.get_rtc_time = todc_get_rtc_time;
 	} else {
 		printk("EP405: NVRTC size is not 512k (not a DS1557).  Not sure what to do with it\n");
 	}
-
-#endif
 }

arch/ppc/platforms/4xx/ep405.h

@@ -16,6 +16,9 @@
 #include <platforms/4xx/ibm405gp.h>
 
 #ifndef __ASSEMBLY__
+
+#include <linux/types.h>
+
 typedef struct board_info {
 	unsigned int	 bi_memsize;		/* DRAM installed, in bytes */
 	unsigned char	 bi_enetaddr[6];	/* Local Ethernet MAC address */

arch/ppc/platforms/4xx/ibm405gp.c

@@ -28,36 +28,20 @@
  *  with this program; if not, write  to the Free Software Foundation, Inc.,
  *  675 Mass Ave, Cambridge, MA 02139, USA.
  *
- *      History: 12/26/2001 - armin
- *		initial release
- *
  */
 
 #include <linux/config.h>
 #include <linux/init.h>
-#include <linux/smp.h>
-#include <linux/threads.h>
-#include <linux/param.h>
-#include <linux/string.h>
+#include <asm/ocp.h>
 #include <platforms/4xx/ibm405gp.h>
 
-const struct pcil0_regs *PCIL_ADDR[] = {
-	(struct pcil0_regs *) PCIL0_BASE,
-};
-
-const struct NS16550 *COM_PORTS[] = {
-	(struct NS16550 *) UART0_IO_BASE,
-	(struct NS16550 *) UART1_IO_BASE,
-};
-
-struct iic_regs *IIC_ADDR[] = {
-	(struct iic_regs *) IIC0_BASE,
-};
-
-const struct gpio_regs *GPIO_ADDR[] = {
-	(struct gpio_regs *) GPIO0_BASE,
-};
+struct ocp_def core_ocp[]  __initdata = {
+	{OCP_VENDOR_IBM, OCP_FUNC_OPB, OPB_BASE_START, OCP_IRQ_NA, OCP_CPM_NA},
+	{OCP_VENDOR_IBM, OCP_FUNC_16550, UART0_IO_BASE, UART0_INT,IBM_CPM_UART0},
+	{OCP_VENDOR_IBM, OCP_FUNC_16550, UART1_IO_BASE, UART1_INT, IBM_CPM_UART1},
+	{OCP_VENDOR_IBM, OCP_FUNC_IIC, IIC0_BASE, IIC0_IRQ, IBM_CPM_IIC0},
+	{OCP_VENDOR_IBM, OCP_FUNC_GPIO, GPIO0_BASE, OCP_IRQ_NA, IBM_CPM_GPIO0},
+	{OCP_VENDOR_IBM, OCP_FUNC_EMAC, EMAC0_BASE, BL_MAC_ETH0, IBM_CPM_EMAC0},
+	{OCP_VENDOR_INVALID, OCP_FUNC_INVALID, 0x0, OCP_IRQ_NA, OCP_CPM_NA},
 
-const struct emac_regs *EMAC_ADDR[] = {
-	(struct emac_regs *) EMAC0_BASE,
 };

arch/ppc/platforms/4xx/ibm405gp.h

@@ -30,19 +30,6 @@
  *  with this program; if not, write  to the Free Software Foundation, Inc.,
  *  675 Mass Ave, Cambridge, MA 02139, USA.
  *
- *	Version 1.0 (01/10/10) - A. Kuster
- *	Initial version	 - moved 40GP  specific out of ppc4xx.h
- *			- moved emac reg from ppc405_enet.h
- *
- *	Version 1.1 02/01/17 - A. Kuster
- *	Moved offsets to ibm405.h
- *
- *	Version 1.2 05/01/02 - Armin
- *	 added IIC_PORT_DFNS
- *
- *	Version 1.3 - armin
- *	  removed iic & uart num defines
- *	  and IIC_PORT_DFNS
  */
 
 #ifdef __KERNEL__
@@ -50,7 +37,6 @@
 #define __ASM_IBM405GP_H__
 
 #include <linux/config.h>
-#include <platforms/4xx/ibm_ocp.h>
 
 /* ibm405.h at bottom of this file */
 
@@ -88,6 +74,9 @@
 #define PPC4xx_ONB_IO_VADDR	PPC4xx_ONB_IO_PADDR
 #define PPC4xx_ONB_IO_SIZE	((uint)4*1024)
 
+#define OPB_BASE_START	0x40000000
+#define EBIU_BASE_START	0xF0100000
+
 /* serial port defines */
 #define RS_TABLE_SIZE	2
 
@@ -101,6 +90,13 @@
 #define OPB0_BASE	0xEF600600
 #define GPIO0_BASE	0xEF600700
 #define EMAC0_BASE	0xEF600800
+#define BL_MAC_WOL	9	/* WOL */
+#define BL_MAL_SERR	10	/* MAL SERR */
+#define BL_MAL_TXDE	13	/* MAL TXDE */
+#define BL_MAL_RXDE	14	/* MAL RXDE */
+#define BL_MAL_TXEOB	11	/* MAL TX EOB */
+#define BL_MAL_RXEOB	12	/* MAL RX EOB */
+#define BL_MAC_ETH0	15	/* MAC */
 
 #define EMAC_NUMS	1
 #define IIC0_IRQ	2
@@ -154,23 +150,25 @@
 #define  PSR_PCI_ASYNC_EN        0x00001000
 #define  PSR_PCI_ARBIT_EN        0x00000400
 
-#define CPM_IIC0		0x80000000	/* IIC interface */
-#define CPM_PCI			0x40000000	/* PCI bridge */
-#define CPM_CPU			0x20000000	/* processor core */
-#define CPM_DMA			0x10000000	/* DMA controller */
-#define CPM_BRG			0x08000000	/* PLB to OPB bridge */
-#define CPM_DCP			0x04000000	/* CodePack */
-#define CPM_EBC			0x02000000	/* ROM/SRAM peripheral controller */
-#define CPM_SDRAM0		0x01000000	/* SDRAM memory controller */
-#define CPM_PLB			0x00800000	/* PLB bus arbiter */
-#define CPM_GPIO0		0x00400000	/* General Purpose IO (??) */
-#define CPM_UART0		0x00200000	/* serial port 0 */
-#define CPM_UART1		0x00100000	/* serial port 1 */
-#define CPM_UIC			0x00080000	/* Universal Interrupt Controller */
-#define CPM_TMRCLK		0x00040000	/* CPU timers */
-#define CPM_EMAC_MM		0x00020000	/* on-chip ethernet MM unit */
-#define CPM_EMAC_RM		0x00010000	/* on-chip ethernet RM unit */
-#define CPM_EMAC_TM		0x00008000	/* on-chip ethernet TM unit */
+#define IBM_CPM_IIC0		0x80000000	/* IIC interface */
+#define IBM_CPM_PCI		0x40000000	/* PCI bridge */
+#define IBM_CPM_CPU		0x20000000	/* processor core */
+#define IBM_CPM_DMA		0x10000000	/* DMA controller */
+#define IBM_CPM_OPB		0x08000000	/* PLB to OPB bridge */
+#define IBM_CPM_DCP		0x04000000	/* CodePack */
+#define IBM_CPM_EBC		0x02000000	/* ROM/SRAM peripheral controller */
+#define IBM_CPM_SDRAM0		0x01000000	/* SDRAM memory controller */
+#define IBM_CPM_PLB		0x00800000	/* PLB bus arbiter */
+#define IBM_CPM_GPIO0		0x00400000	/* General Purpose IO (??) */
+#define IBM_CPM_UART0		0x00200000	/* serial port 0 */
+#define IBM_CPM_UART1		0x00100000	/* serial port 1 */
+#define IBM_CPM_UIC		0x00080000	/* Universal Interrupt Controller */
+#define IBM_CPM_TMRCLK		0x00040000	/* CPU timers */
+#define IBM_CPM_EMAC0		0x00020000	/* on-chip ethernet MM unit */
+#define DFLT_IBM4xx_PM		~(IBM_CPM_PCI | IBM_CPM_CPU | IBM_CPM_DMA \
+					| IBM_CPM_OPB | IBM_CPM_EBC \
+					| IBM_CPM_SDRAM0 | IBM_CPM_PLB \
+					| IBM_CPM_UIC | IBM_CPM_TMRCLK)
 
 #define DCRN_DMA0_BASE		0x100
 #define DCRN_DMA1_BASE		0x108

arch/ppc/platforms/4xx/ibmnp405h.c

@@ -28,51 +28,28 @@
  *  with this program; if not, write  to the Free Software Foundation, Inc.,
  *  675 Mass Ave, Cambridge, MA 02139, USA.
  *
- *      History: 01/02/2002 - armin
- *		initial release
- *
  */
 
 #include <linux/config.h>
 #include <linux/init.h>
-#include <linux/smp.h>
-#include <linux/threads.h>
-#include <linux/param.h>
-#include <linux/string.h>
+#include <asm/ocp.h>
 #include <platforms/4xx/ibmnp405h.h>
 
-const struct NS16550* COM_PORTS[] =
-{
-  (struct NS16550*) UART0_IO_BASE,
-  (struct NS16550*) UART1_IO_BASE,
-};
-
-const struct pcil0_regs* PCIL0[]=
-{
-	(struct pcil0_regs*)	PCIL0_BASE,
-};
-
-
-const struct iic_regs* IIC_ADDR[]=
-{
-	(struct iic_regs*) IIC0_BASE,
-};
-
-
-const struct gpio_regs* GPIO_ADDR[] =
-{
-	(struct gpio_regs*)	GPIO0_BASE,
-};
-
-const struct emac_regs* EMAC_ADDR[]=
-{
-	(struct emac_regs*) EMAC0_BASE,
-	(struct emac_regs*) EMAC1_BASE,
-	(struct emac_regs*) EMAC2_BASE,
-	(struct emac_regs*) EMAC3_BASE
-};
 
-const struct zmii_regs* ZMII_ADDR[]=
-{
-	(zmii_t*)	ZMII0_BASE,
+struct ocp_def core_ocp[] = {
+//	{OCP_VENDOR_IBM, OCP_FUNC_PLB, 0x0, OCP_IRQ_NA, OCP_CPM_NA},
+	{OCP_VENDOR_IBM, OCP_FUNC_OPB, OPB_BASE_START, OCP_IRQ_NA, OCP_CPM_NA},
+	{OCP_VENDOR_IBM, OCP_FUNC_16550, UART0_IO_BASE, UART0_INT,IBM_CPM_UART0},
+	{OCP_VENDOR_IBM, OCP_FUNC_16550, UART1_IO_BASE, UART1_INT, IBM_CPM_UART1},
+	{OCP_VENDOR_IBM, OCP_FUNC_IIC, IIC0_BASE, IIC0_IRQ, IBM_CPM_IIC0},
+	{OCP_VENDOR_IBM, OCP_FUNC_GPIO, GPIO0_BASE, OCP_IRQ_NA, IBM_CPM_GPIO0},
+	{OCP_VENDOR_IBM, OCP_FUNC_EMAC, EMAC0_BASE, BL_MAC_ETH0, IBM_CPM_EMAC0},
+	{OCP_VENDOR_IBM, OCP_FUNC_EMAC, EMAC0_BASE, BL_MAC_ETH0, IBM_CPM_EMAC0},
+	{OCP_VENDOR_IBM, OCP_FUNC_EMAC, EMAC1_BASE, BL_MAC_ETH1, IBM_CPM_EMAC1},
+	{OCP_VENDOR_IBM, OCP_FUNC_EMAC, EMAC2_BASE, BL_MAC_ETH2, IBM_CPM_EMAC2},
+	{OCP_VENDOR_IBM, OCP_FUNC_EMAC, EMAC3_BASE, BL_MAC_ETH3, IBM_CPM_EMAC3},
+	{OCP_VENDOR_IBM, OCP_FUNC_PHY, ZMII0_BASE, OCP_IRQ_NA, OCP_CPM_NA},
+//	{OCP_VENDOR_IBM, OCP_FUNC_EXT, EBIU_BASE_START, OCP_IRQ_NA,IBM_CPM_EBC},
+//	{OCP_VENDOR_IBM, OCP_FUNC_PCI, PCIL0_BASE, OCP_IRQ_NA, IBM_CPM_PCI},
+	{OCP_VENDOR_INVALID, OCP_FUNC_INVALID, 0x0, OCP_IRQ_NA, OCP_CPM_NA},
 };

arch/ppc/platforms/4xx/ibmnp405h.h

@@ -30,11 +30,6 @@
  *  with this program; if not, write  to the Free Software Foundation, Inc.,
  *  675 Mass Ave, Cambridge, MA 02139, USA.
  *
- *	Version 1.0 (02/01/03) - A. Kuster
- *	Initial version
- *
- *	Version 1.1 02/01/17 - A. Kuster
- *	moved common ofsets to ibm405.h
  */
 
 #ifdef __KERNEL__
@@ -42,7 +37,7 @@
 #define __ASM_IBMNP405H_H__
 
 #include <linux/config.h>
-#include <platforms/4xx/ibm_ocp.h>
+#include <asm/ibm_ocp.h>
 
 /* ibm405.h at bottom of this file */
 
@@ -70,6 +65,9 @@
 #define PPC4xx_ONB_IO_ADDR	((uint)0xef600000)
 #define PPC4xx_ONB_IO_SIZE	((uint)4*1024)
 
+#define OPB_BASE_START	0x40000000
+#define EBIU_BASE_START	0xF0100000
+
 /* serial port defines */
 #define RS_TABLE_SIZE	4
 
@@ -83,28 +81,40 @@
 #define GPIO0_BASE	0xEF600700
 #define EMAC0_BASE	0xEF600800
 #define EMAC1_BASE	0xEF600900
-#define EMAC2_BASE	0xEF600900
-#define EMAC3_BASE	0xEF600900
+#define EMAC2_BASE	0xEF600a00
+#define EMAC3_BASE	0xEF600b00
 #define ZMII0_BASE	0xEF600C10
+#define BL_MAC_WOL	41 	/* WOL */
+#define BL_MAL_SERR	45	/* MAL SERR */
+#define BL_MAL_TXDE	46	/* MAL TXDE */
+#define BL_MAL_RXDE	47	/* MAL RXDE */
+#define BL_MAL_TXEOB	17	/* MAL TX EOB */
+#define BL_MAL_RXEOB	18	/* MAL RX EOB */
+#define BL_MAC_ETH0	37	/* MAC */
+#define BL_MAC_ETH1	38	/* MAC */
+#define BL_MAC_ETH2	39	/* MAC */
+#define BL_MAC_ETH3	40	/* MAC */
 
 #define EMAC_NUMS	4
-#define UART_NUMS	2
-#define ZMII_NUMS	1
+#define IIC0_IRQ	2
+
 #define BD_EMAC_ADDR(e,i) bi_enetaddr[e][i]
 
 #define STD_UART_OP(num)					\
 	{ 0, BASE_BAUD, 0, UART##num##_INT,			\
 		(ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST),	\
-		iomem_base: UART##num##_IO_BASE,		\
+		iomem_base:(u8 *) UART##num##_IO_BASE,		\
 		io_type: SERIAL_IO_MEM},
 
 #if defined(CONFIG_UART0_TTYS0)
+#define SERIAL_DEBUG_IO_BASE	UART0_IO_BASE
 #define SERIAL_PORT_DFNS        \
         STD_UART_OP(0)          \
         STD_UART_OP(1)
 #endif
 
 #if defined(CONFIG_UART0_TTYS1)
+#define SERIAL_DEBUG_IO_BASE	UART0_IO_BASE
 #define SERIAL_PORT_DFNS        \
         STD_UART_OP(1)          \
         STD_UART_OP(0)
@@ -113,28 +123,42 @@
 /* DCR defines */
 /* ------------------------------------------------------------------------- */
 
-#define DCRN_CHCR_BASE	0x0B1
+#define DCRN_CHCR_BASE	0x0F1
 #define DCRN_CHPSR_BASE	0x0B4
-#define DCRN_CPMSR_BASE	0x0B8
-#define DCRN_CPMFR_BASE	0x0BA
-
-#define CPM_IIC0	0x80000000	/* IIC interface */
-#define CPM_PCI		0x40000000	/* PCI bridge */
-#define CPM_CPU		0x20000000	/* processor core */
-#define CPM_DMA		0x10000000	/* DMA controller */
-#define CPM_BRG		0x08000000	/* PLB to OPB bridge */
-#define CPM_DCP		0x04000000	/* CodePack */
-#define CPM_EBC		0x02000000	/* ROM/SRAM peripheral controller */
-#define CPM_SDRAM0	0x01000000	/* SDRAM memory controller */
-#define CPM_PLB		0x00800000	/* PLB bus arbiter */
-#define CPM_GPIO0	0x00400000	/* General Purpose IO (??) */
-#define CPM_UART0	0x00200000	/* serial port 0 */
-#define CPM_UART1	0x00100000	/* serial port 1 */
-#define CPM_UIC	=	0x00080000	/* Universal Interrupt Controller */
-#define CPM_TMRCLK	0x00040000	/* CPU timers */
-#define CPM_EMAC_MM	0x00020000	/* on-chip ethernet MM unit */
-#define CPM_EMAC_RM	0x00010000	/* on-chip ethernet RM unit */
-#define CPM_EMAC_TM	0x00008000	/* on-chip ethernet TM unit */
+#define DCRN_CPMSR_BASE	0x0BA
+#define DCRN_CPMFR_BASE	0x0B9
+#define DCRN_CPMER_BASE	0x0B8
+
+/* CPM Clocking & Power Mangement defines */
+#define IBM_CPM_PCI		0x40000000	/* PCI */
+#define IBM_CPM_EMAC2	0x20000000	/* EMAC 2 MII */
+#define IBM_CPM_EMAC3	0x04000000	/* EMAC 3 MII */
+#define IBM_CPM_EMAC0	0x00800000	/* EMAC 0 MII */
+#define IBM_CPM_EMAC1	0x00100000	/* EMAC 1 MII */
+#define IBM_CPM_EMMII	0	/* Shift value for MII */
+#define IBM_CPM_EMRX	1	/* Shift value for recv */
+#define IBM_CPM_EMTX	2	/* Shift value for MAC */
+#define IBM_CPM_UIC1	0x00020000	/* Universal Interrupt Controller */
+#define IBM_CPM_UIC0	0x00010000	/* Universal Interrupt Controller */
+#define IBM_CPM_CPU	0x00008000	/* processor core */
+#define IBM_CPM_EBC	0x00004000	/* ROM/SRAM peripheral controller */
+#define IBM_CPM_SDRAM0	0x00002000	/* SDRAM memory controller */
+#define IBM_CPM_GPIO0	0x00001000	/* General Purpose IO (??) */
+#define IBM_CPM_HDLC	0x00000800	/* HDCL */
+#define IBM_CPM_TMRCLK	0x00000400	/* CPU timers */
+#define IBM_CPM_PLB	0x00000100	/* PLB bus arbiter */
+#define IBM_CPM_OPB	0x00000080	/* PLB to OPB bridge */
+#define IBM_CPM_DMA	0x00000040	/* DMA controller */
+#define IBM_CPM_IIC0	0x00000010	/* IIC interface */
+#define IBM_CPM_UART0	0x00000002	/* serial port 0 */
+#define IBM_CPM_UART1	0x00000001	/* serial port 1 */
+/* this is the default setting for devices put to sleep when booting */
+
+#define DFLT_IBM4xx_PM	~(IBM_CPM_UIC0 | IBM_CPM_UIC1 | IBM_CPM_CPU 	\
+			| IBM_CPM_EBC | IBM_CPM_SDRAM0 | IBM_CPM_PLB 	\
+			| IBM_CPM_OPB | IBM_CPM_TMRCLK | IBM_CPM_DMA	\
+			| IBM_CPM_EMAC0 | IBM_CPM_EMAC1 | IBM_CPM_EMAC2	\
+			| IBM_CPM_EMAC3 | IBM_CPM_PCI)
 
 #define DCRN_DMA0_BASE	0x100
 #define DCRN_DMA1_BASE	0x108
@@ -151,20 +175,29 @@
 #define DCRN_POB0_BASE	0x0A0
 #define DCRN_SDRAM0_BASE 0x010
 #define DCRN_UIC0_BASE	0x0C0
-
-/* unique H offsets */
-
-#ifdef DCRN_UIC1_BASE
-#define DCRN_UIC1_SR	(DCRN_UIC1_BASE + 0x0)
-#define DCRN_UIC1_SRS	(DCRN_UIC1_BASE + 0x1)
-#define DCRN_UIC1_ER	(DCRN_UIC1_BASE + 0x2)
-#define DCRN_UIC1_CR	(DCRN_UIC1_BASE + 0x3)
-#define DCRN_UIC1_PR	(DCRN_UIC1_BASE + 0x4)
-#define DCRN_UIC1_TR	(DCRN_UIC1_BASE + 0x5)
-#define DCRN_UIC1_MSR	(DCRN_UIC1_BASE + 0x6)
-#define DCRN_UIC1_VR	(DCRN_UIC1_BASE + 0x7)
-#define DCRN_UIC1_VCR	(DCRN_UIC1_BASE + 0x8)
-#endif
+#define DCRN_UIC1_BASE	0x0D0
+#define DCRN_CPC0_EPRCSR 0x0F3
+
+#define UIC0_UIC1NC      30	/* UIC1 non-critical interrupt */
+#define UIC0_UIC1CR      31	/* UIC1 critical interrupt */
+
+#define CHR1_CETE	0x00000004	/* CPU external timer enable */
+#define UIC0	DCRN_UIC0_BASE
+#define UIC1	DCRN_UIC1_BASE
+
+#undef NR_UICS
+#define NR_UICS	2
+#define UIC_CASCADE_MASK 0x0003	/* bits 30 & 31 */
+
+/* EMAC DCRN's FIXME: armin */
+#define DCRN_MALRXCTP2R(base)	((base) + 0x42)	/* Channel Rx 2 Channel Table Pointer */
+#define DCRN_MALRXCTP3R(base)	((base) + 0x43)	/* Channel Rx 3 Channel Table Pointer */
+#define DCRN_MALTXCTP4R(base)	((base) + 0x24)	/* Channel Tx 4 Channel Table Pointer */
+#define DCRN_MALTXCTP5R(base)	((base) + 0x25)	/* Channel Tx 5 Channel Table Pointer */
+#define DCRN_MALTXCTP6R(base)	((base) + 0x26)	/* Channel Tx 6 Channel Table Pointer */
+#define DCRN_MALTXCTP7R(base)	((base) + 0x27)	/* Channel Tx 7 Channel Table Pointer */
+#define DCRN_MALRCBS2(base)	((base) + 0x62)	/* Channel Rx 2 Channel Buffer Size */
+#define DCRN_MALRCBS3(base)	((base) + 0x63)	/* Channel Rx 3 Channel Buffer Size */
 
 #include <asm/ibm405.h>
 

arch/ppc/platforms/4xx/ibmnp405l.c

@@ -28,9 +28,6 @@
  *  with this program; if not, write  to the Free Software Foundation, Inc.,
  *  675 Mass Ave, Cambridge, MA 02139, USA.
  *
- *      History: 12/26/2001 - armin
- *		initial release
- *
  */
 
 #include <linux/config.h>
@@ -41,30 +38,15 @@
 #include <linux/string.h>
 #include <platforms/4xx/ibmnp405l.h>
 
-const struct NS16550* COM_PORTS[] =
-{
-  (struct NS16550*) UART0_IO_BASE,
-  (struct NS16550*) UART1_IO_BASE,
-};
-
-const struct iic_regs* IIC_ADDR[]=
-{
-	(struct iic_regs*) IIC0_BASE,
-};
-
-
-const struct gpio_regs* GPIO_ADDR[] =
-{
-	(struct gpio_regs*)	GPIO0_BASE,
-};
-
-const struct emac_regs* EMAC_ADDR[]=
-{
-	(struct emac_regs*) EMAC0_BASE,
-	(struct emac_regs*) EMAC1_BASE
-};
+struct ocp_def core_ocp[] = {
+	{UART, UART0_IO_BASE, UART0_INT, IBM_CPM_UART0},
+	{UART, UART1_IO_BASE, UART1_INT, IBM_CPM_UART1},
+	{IIC, IIC0_BASE, IIC0_IRQ, IBM_CPM_IIC0},
+	{GPIO, GPIO0_BASE, OCP_IRQ_NA, IBM_CPM_GPIO0},
+	{OPB, OPB0_BASE, OCP_IRQ_NA, IBM_CPM_OPB},
+	{EMAC, EMAC0_BASE, BL_MAC_ETH0, IBM_CPM_EMAC0},
+	{EMAC, EMAC1_BASE, BL_MAC_ETH1, IBM_CPM_EMAC1},
+	{ZMII, ZMII0_BASE, OCP_IRQ_NA, OCP_CPM_NA},
+	{OCP_NULL_TYPE, 0x0, OCP_IRQ_NA, OCP_CPM_NA},
 
-const struct zmii_regs* ZMII_ADDR[]=
-{
-	(zmii_t*)	ZMII0_BASE,
 };

arch/ppc/platforms/4xx/ibmnp405l.h

@@ -30,11 +30,6 @@
  *  with this program; if not, write  to the Free Software Foundation, Inc.,
  *  675 Mass Ave, Cambridge, MA 02139, USA.
  *
- *	Version 1.0 (01/10/10) - A. Kuster
- *	Initial version
- *
- *	Version 1.1 (02/01/16) - A. Kuster
- *	Cleaned out common 405B3 core stuff
  */
 
 #ifdef __KERNEL__
@@ -42,18 +37,6 @@
 #define __ASM_IBMNP405L_H__
 
 #include <linux/config.h>
-#include <platforms/4xx/ibm_ocp.h>
-
-/* ibm405.h at bottom of this file */
-
-#define PPC4xx_PCI_IO_ADDR	((uint)PPC405_PCI_PHY_IO_BASE)
-#define PPC4xx_PCI_IO_SIZE	((uint)64*1024)
-#define PPC4xx_PCI_CFG_ADDR	((uint)PPC405_PCI_CONFIG_ADDR)
-#define PPC4xx_PCI_CFG_SIZE	((uint)4*1024)
-#define PPC4xx_PCI_LCFG_ADDR	((uint)0xef400000)
-#define PPC4xx_PCI_LCFG_SIZE	((uint)4*1024)
-#define PPC4xx_ONB_IO_ADDR	((uint)0xef600000)
-#define PPC4xx_ONB_IO_SIZE	((uint)4*1024)
 
 /* serial port defines */
 #define RS_TABLE_SIZE	2
@@ -61,33 +44,48 @@
 #define UART0_INT	0
 #define UART1_INT	1
 
-#define UART0_IO_BASE	(u8 *)0xEF600300
-#define UART1_IO_BASE	(u8 *)0xEF600400
+#define UART0_IO_BASE	0xEF600300
+#define UART1_IO_BASE	0xEF600400
 #define IIC0_BASE	0xEF600500
 #define OPB0_BASE	0xEF600600
 #define GPIO0_BASE	0xEF600700
 #define EMAC0_BASE	0xEF600800
 #define EMAC1_BASE	0xEF600900
 #define ZMII0_BASE	0xEF600C10
+#define BL_MAC_WOL	41	/* WOL */
+#define BL_MAL_SERR	45	/* MAL SERR */
+#define BL_MAL_TXDE	46	/* MAL TXDE */
+#define BL_MAL_RXDE	47	/* MAL RXDE */
+#define BL_MAL_TXEOB	17	/* MAL TX EOB */
+#define BL_MAL_RXEOB	18	/* MAL RX EOB */
+#define BL_MAC_ETH0	37	/* MAC */
+#define BL_MAC_ETH1	38	/* MAC */
 
 #define EMAC_NUMS	2
-#define UART_NUMS	2
-#define ZMII_NUMS	1
+
+#define IIC0_IRQ	2
+
+#undef NR_UICS
+#define NR_UICS	2
+#define UIC_CASCADE_MASK 0x0003	/* bits 30 & 31 */
+
 #define BD_EMAC_ADDR(e,i) bi_enetaddr[e][i]
 
 #define STD_UART_OP(num)					\
 	{ 0, BASE_BAUD, 0, UART##num##_INT,			\
 		(ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST),	\
-		iomem_base: UART##num##_IO_BASE,		\
+		iomem_base:(u8 *) UART##num##_IO_BASE,		\
 		io_type: SERIAL_IO_MEM},
 
 #if defined(CONFIG_UART0_TTYS0)
+#define SERIAL_DEBUG_IO_BASE	UART0_IO_BASE
 #define SERIAL_PORT_DFNS        \
         STD_UART_OP(0)          \
         STD_UART_OP(1)
 #endif
 
 #if defined(CONFIG_UART0_TTYS1)
+#define SERIAL_DEBUG_IO_BASE	UART1_IO_BASE
 #define SERIAL_PORT_DFNS        \
         STD_UART_OP(1)          \
         STD_UART_OP(0)
@@ -96,28 +94,32 @@
 /* DCR defines */
 /* ------------------------------------------------------------------------- */
 
-#define DCRN_CHCR_BASE	0x0B1
+#define DCRN_CHCR_BASE	0x0F1
 #define DCRN_CHPSR_BASE	0x0B4
-#define DCRN_CPMSR_BASE	0x0B8
-#define DCRN_CPMFR_BASE	0x0BA
-
-#define CPM_IIC0	0x80000000	/* IIC interface */
-#define CPM_PCI		0x40000000	/* PCI bridge */
-#define CPM_CPU		0x20000000	/* processor core */
-#define CPM_DMA		0x10000000	/* DMA controller */
-#define CPM_BRG		0x08000000	/* PLB to OPB bridge */
-#define CPM_DCP		0x04000000	/* CodePack */
-#define CPM_EBC		0x02000000	/* ROM/SRAM peripheral controller */
-#define CPM_SDRAM0	0x01000000	/* SDRAM memory controller */
-#define CPM_PLB		0x00800000	/* PLB bus arbiter */
-#define CPM_GPIO0	0x00400000	/* General Purpose IO (??) */
-#define CPM_UART0	0x00200000	/* serial port 0 */
-#define CPM_UART1	0x00100000	/* serial port 1 */
-#define CPM_UIC		0x00080000	/* Universal Interrupt Controller */
-#define CPM_TMRCLK	0x00040000	/* CPU timers */
-#define CPM_EMAC_MM	0x00020000	/* on-chip ethernet MM unit */
-#define CPM_EMAC_RM	0x00010000	/* on-chip ethernet RM unit */
-#define CPM_EMAC_TM	0x00008000	/* on-chip ethernet TM unit */
+#define DCRN_CPMSR_BASE	0x0BA
+#define DCRN_CPMFR_BASE	0x0B9
+#define DCRN_CPMER_BASE	0x0B8
+
+#define IBM_CPM_EMAC0	0x00800000	/* on-chip ethernet MM unit */
+#define IBM_CPM_EMAC1	0x00100000	/* EMAC 1 MII */
+#define IBM_CPM_UIC1	0x00020000	/* Universal Interrupt Controller */
+#define IBM_CPM_UIC0	0x00010000	/* Universal Interrupt Controller */
+#define IBM_CPM_CPU	0x00008000	/* processor core */
+#define IBM_CPM_EBC	0x00004000	/* ROM/SRAM peripheral controller */
+#define IBM_CPM_SDRAM0	0x00002000	/* SDRAM memory controller */
+#define IBM_CPM_GPIO0	0x00001000	/* General Purpose IO (??) */
+#define IBM_CPM_HDLC	0x00000800	/* HDCL */
+#define IBM_CPM_TMRCLK	0x00000400	/* CPU timers */
+#define IBM_CPM_PLB	0x00000100	/* PLB bus arbiter */
+#define IBM_CPM_OPB	0x00000080	/* PLB to OPB bridge */
+#define IBM_CPM_DMA	0x00000040	/* DMA controller */
+#define IBM_CPM_IIC0	0x00000010	/* IIC interface */
+#define IBM_CPM_UART0	0x00000002	/* serial port 0 */
+#define IBM_CPM_UART1	0x00000001	/* serial port 1 */
+#define DFLT_IBM4xx_PM	~(IBM_CPM_UIC0 | IBM_CPM_UIC1 | IBM_CPM_CPU	\
+			| IBM_CPM_EBC | IBM_CPM_SDRAM0 | IBM_CPM_PLB	\
+			| IBM_CPM_OPB | IBM_CPM_TMRCLK | IBM_CPM_DMA	\
+			| IBM_CPM_EMAC0 | IBM_CPM_EMAC1)
 
 #define DCRN_DMA0_BASE	0x100
 #define DCRN_DMA1_BASE	0x108
@@ -128,28 +130,26 @@
 #define DCRN_EBC_BASE	0x012
 #define DCRN_DCP0_BASE	0x014
 #define DCRN_MAL_BASE	0x180
+#define DCRN_MAL1_BASE	0x200
 #define DCRN_OCM0_BASE	0x018
 #define DCRN_PLB0_BASE	0x084
-#define DCRN_PLLMR_BASE	0x0B0
+#define DCRN_PLLMR_BASE	0x0F0
 #define DCRN_POB0_BASE	0x0A0
 #define DCRN_SDRAM0_BASE 0x010
 #define DCRN_UIC0_BASE	0x0C0
-#define DCRN_UIC1_BASE	0x0C0
-
-/* need to clean this up - armin */
-
-#ifdef DCRN_UIC1_BASE
-#define DCRN_UIC1_SR	(DCRN_UIC1_BASE + 0x0)
-#define DCRN_UIC1_SRS	(DCRN_UIC1_BASE + 0x1)
-#define DCRN_UIC1_ER	(DCRN_UIC1_BASE + 0x2)
-#define DCRN_UIC1_CR	(DCRN_UIC1_BASE + 0x3)
-#define DCRN_UIC1_PR	(DCRN_UIC1_BASE + 0x4)
-#define DCRN_UIC1_TR	(DCRN_UIC1_BASE + 0x5)
-#define DCRN_UIC1_MSR	(DCRN_UIC1_BASE + 0x6)
-#define DCRN_UIC1_VR	(DCRN_UIC1_BASE + 0x7)
-#define DCRN_UIC1_VCR	(DCRN_UIC1_BASE + 0x8)
-#endif
+#define DCRN_UIC1_BASE	0x0D0
+#define DCRN_CPC0_EPRCSR 0x0F3
+
+#define UIC0_UIC1NC      30	/* UIC1 non-critical interrupt */
+#define UIC0_UIC1CR      31	/* UIC1 critical interrupt */
+
+#define CHR1_CETE	0x00000004	/* CPU external timer enable */
+#define UIC0	DCRN_UIC0_BASE
+#define UIC1	DCRN_UIC1_BASE
 
+#define SDRAM_CFG	0x20
+#define SDRAM0_ECCCFG	0x94
+#define SDRAM_NO_ECC	0x10000000
 #include <asm/ibm405.h>
 
 #endif				/* __ASM_IBMNP405L_H__ */

arch/ppc/platforms/4xx/ibmstb3.c

@@ -28,26 +28,18 @@
  *  with this program; if not, write  to the Free Software Foundation, Inc.,
  *  675 Mass Ave, Cambridge, MA 02139, USA.
  *
- *      History: 01/08/2002 - armin
- *		initial release
- *
  */
 
 #include <linux/config.h>
-#include <platforms/4xx/ibmstb3.h>
+#include "ibmstb3.h"
+#include <asm/ocp.h>
 
-const struct NS16550* COM_PORTS[] =
-{
-  (struct NS16550*) UART0_IO_BASE,
-};
+struct ocp_def core_ocp[] = {
+	{UART, UART0_IO_BASE, UART0_INT, IBM_CPM_UART0},
+	{IIC, IIC0_BASE, IIC0_IRQ, IBM_CPM_IIC0},
+	{IIC, IIC1_BASE, IIC1_IRQ, IBM_CPM_IIC1},
+	{GPIO, GPIO0_BASE, OCP_IRQ_NA, IBM_CPM_GPIO0},
+	{OPB, OPB0_BASE, OCP_IRQ_NA, OCP_CPM_NA},
+	{OCP_NULL_TYPE, 0x0, OCP_IRQ_NA, OCP_CPM_NA},
 
-const struct iic_regs* IIC_ADDR[]=
-{
-	(struct iic_regs*) IIC0_BASE,
 };
-
-const struct gpio_regs* GPIO_ADDR[] =
-{
-	(struct gpio_regs*)	GPIO0_BASE,
-};
-

arch/ppc/platforms/4xx/ibmstb3.h

@@ -32,15 +32,6 @@
  *  with this program; if not, write  to the Free Software Foundation, Inc.,
  *  675 Mass Ave, Cambridge, MA 02139, USA.
  *
- *	Version 1.0 Oct 10, 2001 - A. Kuster
- *	Initial version	 - moved stbx  specific out of ibm4xx.h
- *
- *	Version 1.1 Oct 25, 2001 - T. Rini
- *	Lots of cleanups, and we get included by the board-specific file.
- *
- *	Version 1.2 Jan 16, 2002 - A. Kuster
- *	Removed common dcr offests that are now in ibm405.h 
- *
  */
 
 #ifdef __KERNEL__
@@ -84,9 +75,9 @@
 #define RS_TABLE_SIZE		1
 #define UART0_INT		20
 #ifdef __BOOTER__
-#define UART0_IO_BASE		(u8 *)0x40040000
+#define UART0_IO_BASE		0x40040000
 #else
-#define UART0_IO_BASE		(u8 *)STB03xxx_MAP_IO_ADDR(0x40040000)
+#define UART0_IO_BASE		0xe0040000
 #endif
 
  /* UART 0 is duped here so when the SICC is the default console
@@ -95,9 +86,9 @@
 
 #define UART1_INT		20
 #ifdef __BOOTER__
-#define UART1_IO_BASE		(u8 *)0x40040000
+#define UART1_IO_BASE		0x40040000
 #else
-#define UART1_IO_BASE		(u8 *)STB03xxx_MAP_IO_ADDR(0x40040000)
+#define UART1_IO_BASE		0xe0040000
 #endif
 
 /* need to make this work in scheme - armin */
@@ -106,25 +97,35 @@
 #define SICC0_INTTX		22
 #define SICC0_IO_BASE		((uint* )0x40000000)
 
+#define IDE0_BASE		0xf2100000
+#define REDWOOD_IDE_CTRL	0xf4100000
+
 #define IIC0_BASE	0x40030000
 #define IIC1_BASE	0x400b0000
 #define OPB0_BASE	0x40010000
 #define GPIO0_BASE	0x40060000
+#define IIC0_IRQ	9
+#define IIC1_IRQ	10
+#define IIC_OWN		0x55
+#define IIC_CLOCK	50
+#define IDE0_IRQ 	25
 
 #define BD_EMAC_ADDR(e,i) bi_enetaddr[i]
 
 #define STD_UART_OP(num)					\
 	{ 0, BASE_BAUD, 0, UART##num##_INT,			\
 		(ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST),	\
-		iomem_base: UART##num##_IO_BASE,		\
+		iomem_base: (u8 *)UART##num##_IO_BASE,		\
 		io_type: SERIAL_IO_MEM},
 
 #if defined(CONFIG_UART0_TTYS0)
+#define SERIAL_DEBUG_IO_BASE	UART0_IO_BASE
 #define SERIAL_PORT_DFNS	\
 	STD_UART_OP(0)
 #endif
 
 #if defined(CONFIG_UART0_TTYS1)
+#define SERIAL_DEBUG_IO_BASE	UART1_IO_BASE
 #define SERIAL_PORT_DFNS	\
 	STD_UART_OP(1)
 #endif
@@ -149,72 +150,39 @@
 
 #define DCRN_CPMFR_BASE		0x102
 #define DCRN_SCCR_BASE		0x120
+#define UIC0 DCRN_UIC0_BASE
+
+#define IBM_CPM_IIC0	0x80000000	/* IIC 0 interface */
+#define IBM_CPM_I1284	0x40000000	/* IEEE-1284 */
+#define IBM_CPM_IIC1	0x20000000	/* IIC 1 interface */
+#define IBM_CPM_CPU	0x10000000	/* PPC405B3 clock control */
+#define IBM_CPM_AUD	0x08000000	/* Audio Decoder */
+#define IBM_CPM_EBIU	0x04000000	/* External Bus Interface Unit */
+#define IBM_CPM_SDRAM1	0x02000000	/* SDRAM 1 memory controller */
+#define IBM_CPM_DMA	0x01000000	/* DMA controller */
+#define IBM_CPM_UART1	0x00100000	/* Serial 1 / Infrared */
+#define IBM_CPM_UART0	0x00080000	/* Serial 0 / 16550 */
+#define IBM_CPM_DCRX	0x00040000	/* DCR Extension */
+#define IBM_CPM_SC0	0x00020000	/* Smart Card 0 */
+#define IBM_CPM_SC1	0x00008000	/* Smart Card 1 */
+#define IBM_CPM_SDRAM0	0x00004000	/* SDRAM 0 memory controller */
+#define IBM_CPM_XPT54	0x00002000	/* Transport - 54 Mhz */
+#define IBM_CPM_CBS	0x00001000	/* Cross Bar Switch */
+#define IBM_CPM_GPT	0x00000800	/* GPTPWM */
+#define IBM_CPM_GPIO0	0x00000400	/* General Purpose IO 0 */
+#define IBM_CPM_DENC	0x00000200	/* Digital video Encoder */
+#define IBM_CPM_TMRCLK	0x00000100	/* CPU timers */
+#define IBM_CPM_XPT27	0x00000080	/* Transport - 27 Mhz */
+#define IBM_CPM_UIC	0x00000040	/* Universal Interrupt Controller */
+#define IBM_CPM_MSI	0x00000010	/* Modem Serial Interface (SSP) */
+#define IBM_CPM_UART2	0x00000008	/* Serial Control Port */
+#define IBM_CPM_DSCR	0x00000004	/* Descrambler */
+#define IBM_CPM_VID2	0x00000002	/* Video Decoder clock domain 2 */
 
-#define CPM_IIC0	0x80000000	/* IIC 0 interface */
-#define CPM_I1284	0x40000000	/* IEEE-1284 */
-#define CPM_IIC1	0x20000000	/* IIC 1 interface */
-#define CPM_CPU		0x10000000	/* PPC405B3 clock control */
-#define CPM_AUD		0x08000000	/* Audio Decoder */
-#define CPM_EBIU	0x04000000	/* External Bus Interface Unit */
-#define CPM_SDRAM1	0x02000000	/* SDRAM 1 memory controller */
-#define CPM_DMA		0x01000000	/* DMA controller */
-#define CPM_RES_1	0x00800000	/* reserved */
-#define CPM_RES_2	0x00400000	/* reserved */
-#define CPM_RES_3	0x00200000	/* reserved */
-#define CPM_UART1	0x00100000	/* Serial 1 / Infrared */
-#define CPM_UART0	0x00080000	/* Serial 0 / 16550 */
-#define CPM_DCRX	0x00040000	/* DCR Extension */
-#define CPM_SC0		0x00020000	/* Smart Card 0 */
-#define CPM_RES_4	0x00010000	/* reserved */
-#define CPM_SC1		0x00008000	/* Smart Card 1 */
-#define CPM_SDRAM0	0x00004000	/* SDRAM 0 memory controller */
-#define CPM_XPT54	0x00002000	/* Transport - 54 Mhz */
-#define CPM_CBS		0x00001000	/* Cross Bar Switch */
-#define CPM_GPT		0x00000800	/* GPTPWM */
-#define CPM_GPIO0	0x00000400	/* General Purpose IO 0 */
-#define CPM_DENC	0x00000200	/* Digital video Encoder */
-#define CPM_TMRCLK	0x00000100	/* CPU timers */
-#define CPM_XPT27	0x00000080	/* Transport - 27 Mhz */
-#define CPM_UIC		0x00000040	/* Universal Interrupt Controller */
-#define CPM_RES_5	0x00000020	/* reserved */
-#define CPM_MSI		0x00000010	/* Modem Serial Interface (SSP) */
-#define CPM_UART2	0x00000008	/* Serial Control Port */
-#define CPM_DSCR	0x00000004	/* Descrambler */
-#define CPM_VID2	0x00000002	/* Video Decoder clock domain 2 */
-#define CPM_RES_6	0x00000001	/* reserved */
-
-/*			0x80000000 */
-#define UIC_XPORT	0x40000000	/* 1 Transport */
-#define UIC_AUDIO	0x20000000	/* 2 Audio Decoder */
-#define UIC_VIDEO	0x10000000	/* 3 Video Decoder */
-#define UIC_D0		0x08000000	/* 4 DMA Channel 0 */
-#define UIC_D1		0x04000000	/* 5 DMA Channel 1 */
-#define UIC_D2		0x02000000	/* 6 DMA Channel 2 */
-#define UIC_D3		0x01000000	/* 7 DMA Channel 3 */
-#define UIC_SC0		0x00800000	/* 8 SmartCard 0 Controller */
-#define UIC_IIC0	0x00400000	/* 9 IIC 0 */
-#define UIC_IIC1	0x00200000	/* 10 IIC 1 */
-#define UIC_PWM0	0x00100000	/* 11 GPT_PWM 0: Capture Timers */
-#define UIC_PWM1	0x00080000	/* 12 GPT_PWM 1: Compare Timers */
-#define UIC_SCP		0x00040000	/* 13 Serial Control Port */
-#define UIC_SSP		0x00020000	/* 14 Soft Modem/Synchronous Serial Port */
-#define UIC_PWM2	0x00010000	/* 15 GPT_PWM 2: Down Counters */
-#define UIC_SC1		0x00008000	/* 16 SmartCard 1 Controller */
-#define UIC_EIR7	0x00004000	/* 17 External IRQ 7 */
-#define UIC_EIR8	0x00002000	/* 18 External IRQ 8 */
-#define UIC_EIR9	0x00001000	/* 19 External IRQ 9 */
-#define UIC_U0		0x00000800	/* 20 UART0 */
-#define UIC_IR_RCV	0x00000400	/* 21 Serial 1 / Infrared UART Receive */
-#define UIC_IR_XMIT	0x00000200	/* 22 Serial 1 / Infrared UART Transmit */
-#define UIC_IEEE1284	0x00000100	/* 23 IEEE-1284 / PPU */
-#define UIC_DCRX	0x00000080	/* 24 DCRX */
-#define UIC_EIR0	0x00000040	/* 25 External IRQ 0 */
-#define UIC_EIR1	0x00000020	/* 26 External IRQ 1 */
-#define UIC_EIR2	0x00000010	/* 27 External IRQ 2 */
-#define UIC_EIR3	0x00000008	/* 28 External IRQ 3 */
-#define UIC_EIR4	0x00000004	/* 29 External IRQ 4 */
-#define UIC_EIR5	0x00000002	/* 30 External IRQ 5 */
-#define UIC_EIR6	0x00000001	/* 31 External IRQ 6 */
+#define DFLT_IBM4xx_PM	~(IBM_CPM_CPU | IBM_CPM_EBIU | IBM_CPM_SDRAM1 \
+			| IBM_CPM_DMA | IBM_CPM_CBS | IBM_CPM_SDRAM0 \
+			| IBM_CPM_XPT54 | IBM_CPM_TMRCLK | IBM_CPM_XPT27 \
+			| IBM_CPM_UIC)
 
 #ifdef DCRN_CIC_BASE
 #define DCRN_CICCR	(DCRN_CIC_BASE + 0x0)	/* CIC Control Register */

arch/ppc/platforms/4xx/ibmstb4.c

@@ -28,34 +28,21 @@
  *  with this program; if not, write  to the Free Software Foundation, Inc.,
  *  675 Mass Ave, Cambridge, MA 02139, USA.
  *
- *      History: 12/26/2001 - armin
- *		initial release
- *
  */
 
 #include <linux/config.h>
-#include <platforms/4xx/ibmstb4.h>
-
-const struct NS16550* COM_PORTS[] =
-{
-  (struct NS16550*) UART0_IO_BASE,
-  (struct NS16550*) UART1_IO_BASE,
-  (struct NS16550*) UART2_IO_BASE,
-};
-
-const struct iic_regs* IIC_ADDR[]=
-{
-	(struct iic_regs*) IIC0_BASE,
-};
-
-
-const struct gpio_regs* GPIO_ADDR[] =
-{
-	(struct gpio_regs*)	GPIO0_BASE,
-};
-
-const struct ide_regs* IDE_ADDR[] =
-{
-	(struct ide_regs*) IDE0_IO_ADDR,
+#include <linux/module.h>
+#include "ibmstb4.h"
+#include <asm/ocp.h>
 
+struct ocp_def core_ocp[] = {
+	{UART, UART0_IO_BASE, UART0_INT,IBM_CPM_UART0},
+	{UART, UART1_IO_BASE, UART1_INT, IBM_CPM_UART1},
+	{UART, UART2_IO_BASE, UART2_INT, IBM_CPM_UART2},
+	{IIC, IIC0_BASE, IIC0_IRQ, IBM_CPM_IIC0},
+	{IIC, IIC1_BASE, IIC1_IRQ, IBM_CPM_IIC1},
+	{GPIO, GPIO0_BASE, OCP_IRQ_NA, IBM_CPM_GPIO0},
+	{IDE, IDE0_BASE, IDE0_IRQ, OCP_CPM_NA},
+	{USB, USB0_BASE, USB0_IRQ, IBM_CPM_USB0},
+	{OCP_NULL_TYPE, 0x0, OCP_IRQ_NA, OCP_CPM_NA},
 };

arch/ppc/platforms/4xx/ibmstb4.h

@@ -30,11 +30,6 @@
  *  with this program; if not, write  to the Free Software Foundation, Inc.,
  *  675 Mass Ave, Cambridge, MA 02139, USA.
  *
- *	Version 1.0 (01/10/10) - A. Kuster
- *	Initial version	
- *
- *	Version 1.1 02/01/17 - A. Kuster
- *	moved common offsets to ibm405.h
  */
 
 #ifdef __KERNEL__
@@ -72,31 +67,57 @@
 
 #define RS_TABLE_SIZE		3
 #define UART0_INT		20
-#define UART0_IO_BASE		(u8 *)0x40040000
+
+#ifdef __BOOTER__
+#define UART0_IO_BASE		0x40040000
+#else
+#define UART0_IO_BASE		0xe0040000
+#endif
+
 #define UART1_INT		21
-#define UART1_IO_BASE		(u8 *)0x40000000
-#define UART2_INT		31
-#define UART2_IO_BASE		(u8 *)0x400e0000
 
-#define IDE0_IO_ADDR	0x400F0000
-#define IDE0_IO_SIZE	0x200
+#ifdef __BOOTER__
+#define UART1_IO_BASE		0x40000000
+#else
+#define UART1_IO_BASE		0xe0000000
+#endif
 
+#define UART2_INT		31
+#ifdef __BOOTER__
+#define UART2_IO_BASE		0x400e0000
+#else
+#define UART2_IO_BASE		0xe00e0000
+#endif
+
+#define IDE0_BASE	0x400F0000
+#define IDE0_SIZE	0x200
+#define IDE0_IRQ	25
 #define IIC0_BASE	0x40030000
 #define IIC1_BASE	0x400b0000
 #define OPB0_BASE	0x40000000
 #define GPIO0_BASE	0x40060000
 
+#define USB0_IRQ	18
+#define USB0_BASE	STB04xxx_MAP_IO_ADDR(0x40010000)
+#define USB0_EXTENT 4096
+
+#define IIC_NUMS 2
 #define UART_NUMS	3
+#define IIC0_IRQ	9
+#define IIC1_IRQ	10
+#define IIC_OWN		0x55
+#define IIC_CLOCK	50
 
 #define BD_EMAC_ADDR(e,i) bi_enetaddr[i]
 
 #define STD_UART_OP(num)					\
 	{ 0, BASE_BAUD, 0, UART##num##_INT,			\
 		(ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST),	\
-		iomem_base: UART##num##_IO_BASE,		\
+		iomem_base: (u8 *)UART##num##_IO_BASE,		\
 		io_type: SERIAL_IO_MEM},
 
 #if defined(CONFIG_UART0_TTYS0)
+#define SERIAL_DEBUG_IO_BASE	UART0_IO_BASE
 #define SERIAL_PORT_DFNS	\
 	STD_UART_OP(0)		\
 	STD_UART_OP(1)		\
@@ -104,6 +125,7 @@
 #endif
 
 #if defined(CONFIG_UART0_TTYS1)
+#define SERIAL_DEBUG_IO_BASE	UART2_IO_BASE
 #define SERIAL_PORT_DFNS	\
 	STD_UART_OP(1)		\
 	STD_UART_OP(0)		\
@@ -111,6 +133,7 @@
 #endif
 
 #if defined(CONFIG_UART0_TTYS2)
+#define SERIAL_DEBUG_IO_BASE	UART2_IO_BASE
 #define SERIAL_PORT_DFNS	\
 	STD_UART_OP(2)		\
 	STD_UART_OP(0)		\
@@ -140,72 +163,43 @@
 #define DCRN_DCRX_BASE		0x020
 #define DCRN_CPMFR_BASE		0x102
 #define DCRN_SCCR_BASE		0x120
+#define UIC0 DCRN_UIC0_BASE
 
-#define CPM_IIC0	0x80000000	/* IIC 0 interface */
-#define CPM_I1284	0x40000000	/* IEEE-1284 */
-#define CPM_IIC1	0x20000000	/* IIC 1 interface */
-#define CPM_CPU		0x10000000	/* PPC405B3 clock control */
-#define CPM_AUD		0x08000000	/* Audio Decoder */
-#define CPM_EBIU	0x04000000	/* External Bus Interface Unit */
-#define CPM_SDRAM1	0x02000000	/* SDRAM 1 memory controller */
-#define CPM_DMA		0x01000000	/* DMA controller */
-#define CPM_RES_1	0x00800000	/* reserved */
-#define CPM_RES_2	0x00400000	/* reserved */
-#define CPM_RES_3	0x00200000	/* reserved */
-#define CPM_UART1	0x00100000	/* Serial 1 / Infrared */
-#define CPM_UART0	0x00080000	/* Serial 0 / 16550 */
-#define CPM_DCRX	0x00040000	/* DCR Extension */
-#define CPM_SC0		0x00020000	/* Smart Card 0 */
-#define CPM_RES_4	0x00010000	/* reserved */
-#define CPM_SC1		0x00008000	/* Smart Card 1 */
-#define CPM_SDRAM0	0x00004000	/* SDRAM 0 memory controller */
-#define CPM_XPT54	0x00002000	/* Transport - 54 Mhz */
-#define CPM_CBS		0x00001000	/* Cross Bar Switch */
-#define CPM_GPT		0x00000800	/* GPTPWM */
-#define CPM_GPIO0	0x00000400	/* General Purpose IO 0 */
-#define CPM_DENC	0x00000200	/* Digital video Encoder */
-#define CPM_TMRCLK	0x00000100	/* CPU timers */
-#define CPM_XPT27	0x00000080	/* Transport - 27 Mhz */
-#define CPM_UIC		0x00000040	/* Universal Interrupt Controller */
-#define CPM_RES_5	0x00000020	/* reserved */
-#define CPM_MSI		0x00000010	/* Modem Serial Interface (SSP) */
-#define CPM_UART2	0x00000008	/* Serial Control Port */
-#define CPM_DSCR	0x00000004	/* Descrambler */
-#define CPM_VID2	0x00000002	/* Video Decoder clock domain 2 */
-#define CPM_RES_6	0x00000001	/* reserved */
+#define IBM_CPM_IIC0	0x80000000	/* IIC 0 interface */
+#define IBM_CPM_USB0	0x40000000	/* IEEE-1284 */
+#define IBM_CPM_IIC1	0x20000000	/* IIC 1 interface */
+#define IBM_CPM_CPU	0x10000000	/* PPC405B3 clock control */
+#define IBM_CPM_AUD	0x08000000	/* Audio Decoder */
+#define IBM_CPM_EBIU	0x04000000	/* External Bus Interface Unit */
+#define IBM_CPM_SDRAM1	0x02000000	/* SDRAM 1 memory controller */
+#define IBM_CPM_DMA	0x01000000	/* DMA controller */
+#define IBM_CPM_DMA1	0x00800000	/* reserved */
+#define IBM_CPM_XPT1	0x00400000	/* reserved */
+#define IBM_CPM_XPT2	0x00200000	/* reserved */
+#define IBM_CPM_UART1	0x00100000	/* Serial 1 / Infrared */
+#define IBM_CPM_UART0	0x00080000	/* Serial 0 / 16550 */
+#define IBM_CPM_EPI	0x00040000	/* DCR Extension */
+#define IBM_CPM_SC0	0x00020000	/* Smart Card 0 */
+#define IBM_CPM_VID	0x00010000	/* reserved */
+#define IBM_CPM_SC1	0x00008000	/* Smart Card 1 */
+#define IBM_CPM_USBSDRA	0x00004000	/* SDRAM 0 memory controller */
+#define IBM_CPM_XPT0	0x00002000	/* Transport - 54 Mhz */
+#define IBM_CPM_CBS	0x00001000	/* Cross Bar Switch */
+#define IBM_CPM_GPT	0x00000800	/* GPTPWM */
+#define IBM_CPM_GPIO0	0x00000400	/* General Purpose IO 0 */
+#define IBM_CPM_DENC	0x00000200	/* Digital video Encoder */
+#define IBM_CPM_TMRCLK	0x00000100	/* CPU timers */
+#define IBM_CPM_XPT27	0x00000080	/* Transport - 27 Mhz */
+#define IBM_CPM_UIC	0x00000040	/* Universal Interrupt Controller */
+#define IBM_CPM_SSP	0x00000010	/* Modem Serial Interface (SSP) */
+#define IBM_CPM_UART2	0x00000008	/* Serial Control Port */
+#define IBM_CPM_DDIO	0x00000004	/* Descrambler */
+#define IBM_CPM_VID2	0x00000002	/* Video Decoder clock domain 2 */
 
-/*			0x80000000 */
-#define UIC_XPORT	0x40000000	/* 1 Transport */
-#define UIC_AUDIO	0x20000000	/* 2 Audio Decoder */
-#define UIC_VIDEO	0x10000000	/* 3 Video Decoder */
-#define UIC_D0		0x08000000	/* 4 DMA Channel 0 */
-#define UIC_D1		0x04000000	/* 5 DMA Channel 1 */
-#define UIC_D2		0x02000000	/* 6 DMA Channel 2 */
-#define UIC_D3		0x01000000	/* 7 DMA Channel 3 */
-#define UIC_SC0		0x00800000	/* 8 SmartCard 0 Controller */
-#define UIC_IIC0	0x00400000	/* 9 IIC 0 */
-#define UIC_IIC1	0x00200000	/* 10 IIC 1 */
-#define UIC_PWM0	0x00100000	/* 11 GPT_PWM 0: Capture Timers */
-#define UIC_PWM1	0x00080000	/* 12 GPT_PWM 1: Compare Timers */
-#define UIC_SCP		0x00040000	/* 13 Serial Control Port */
-#define UIC_SSP		0x00020000	/* 14 Soft Modem/Synchronous Serial Port */
-#define UIC_PWM2	0x00010000	/* 15 GPT_PWM 2: Down Counters */
-#define UIC_SC1		0x00008000	/* 16 SmartCard 1 Controller */
-#define UIC_EIR7	0x00004000	/* 17 External IRQ 7 */
-#define UIC_EIR8	0x00002000	/* 18 External IRQ 8 */
-#define UIC_EIR9	0x00001000	/* 19 External IRQ 9 */
-#define UIC_U0		0x00000800	/* 20 UART0 */
-#define UIC_IR_RCV	0x00000400	/* 21 Serial 1 / Infrared UART Receive */
-#define UIC_IR_XMIT	0x00000200	/* 22 Serial 1 / Infrared UART Transmit */
-#define UIC_IEEE1284	0x00000100	/* 23 IEEE-1284 / PPU */
-#define UIC_DCRX	0x00000080	/* 24 DCRX */
-#define UIC_EIR0	0x00000040	/* 25 External IRQ 0 */
-#define UIC_EIR1	0x00000020	/* 26 External IRQ 1 */
-#define UIC_EIR2	0x00000010	/* 27 External IRQ 2 */
-#define UIC_EIR3	0x00000008	/* 28 External IRQ 3 */
-#define UIC_EIR4	0x00000004	/* 29 External IRQ 4 */
-#define UIC_EIR5	0x00000002	/* 30 External IRQ 5 */
-#define UIC_EIR6	0x00000001	/* 31 External IRQ 6 */
+#define DFLT_IBM4xx_PM	~(IBM_CPM_CPU | IBM_CPM_EBIU | IBM_CPM_SDRAM1 \
+			| IBM_CPM_DMA | IBM_CPM_DMA1 | IBM_CPM_CBS \
+			| IBM_CPM_USBSDRA | IBM_CPM_XPT0 | IBM_CPM_TMRCLK \
+			| IBM_CPM_XPT27 | IBM_CPM_UIC )
 
 #define DCRN_BEAR	(DCRN_BE_BASE + 0x0)	/* Bus Error Address Register */
 #define DCRN_BESR	(DCRN_BE_BASE + 0x1)	/* Bus Error Syndrome Register */

arch/ppc/platforms/4xx/redwood.c

@@ -7,11 +7,6 @@
  *
  *    Module name: redwood.c
  *
- *    Description:
- *
- *      History:  11/09/2001 - Armin
- *      added board_init to add in additional instuctions needed during platfrom_init
- *
  */
 
 #include <linux/config.h>
@@ -22,26 +17,58 @@
 #include <asm/machdep.h>
 
 void __init
-board_setup_arch(void)
+redwood_setup_arch(void)
 {
+	ppc4xx_setup_arch();
+
+#ifdef CONFIG_IDE
+	void *xilinx, *xilinx_1, *xilinx_2;
+	unsigned short reg5;
+
+	xilinx = ioremap(IDE_XLINUX_MUX_BASE, 0x10);
+
+	/* init xilinx control registers - enable ide mux, clear reset bit */
+	if (!xilinx) {
+		printk(KERN_CRIT
+		       "redwood4_setup_arch() xilinx ioremap failed\n");
+		return;
+	}
+	xilinx_1 = xilinx;
+	xilinx_2 = xilinx + 0xe;
+
+	reg5 = readw(xilinx_1);
+	writeb(reg5 |= ~(0x8001), xilinx_1);
+	writeb(0, xilinx_2);
+
+	udelay(10 * 1000);
+
+	writeb(reg5 & 0x8001, xilinx_1);
+	writeb(0, xilinx_2);
+	
+       	/* add RE & OEN to value set by boot rom */
+        mtdcr(DCRN_BRCR3, 0x407cfffe);
+
+#endif
+
 }
 
 void __init
-board_io_mapping(void)
+redwood_map_io(void)
 {
 	int i;
 
+	ppc4xx_map_io();
 	io_block_mapping(OAKNET_IO_VADDR,
 			 OAKNET_IO_PADDR, OAKNET_IO_SIZE, _PAGE_IO);
 
 }
 
 void __init
-board_setup_irq(void)
+platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
+	      unsigned long r6, unsigned long r7)
 {
-}
+	ppc4xx_init(r3, r4, r5, r6, r7);
 
-void __init
-board_init(void)
-{
+	ppc_md.setup_arch = redwood_setup_arch;
+	ppc_md.setup_io_mappings = redwood_map_io;
 }

arch/ppc/platforms/4xx/redwood.h

@@ -27,10 +27,12 @@ typedef struct board_info {
 	unsigned char	bi_enetaddr[6];		/* Ethernet MAC address */
 	unsigned int	bi_intfreq;		/* Processor speed, in Hz */
 	unsigned int	bi_busfreq;		/* Bus speed, in Hz */
-	unsigned int	bi_tbfreq;		/* Software timebase freq */
 } bd_t;
+#define bi_tbfreq bi_intfreq
+
 #endif /* !__ASSEMBLY__ */
 
+#define bi_tbfreq bi_intfreq
 #define OAKNET_IO_PADDR		((uint)0xf2000000)
 #define OAKNET_IO_VADDR		OAKNET_IO_PADDR
 #define OAKNET_IO_BASE		OAKNET_IO_VADDR
@@ -39,6 +41,9 @@ typedef struct board_info {
 #define OAKNET_IO_SIZE		0xffff
 #define OAKNET_INT		26	/* EXTINT1 */
 
+#define IDE_XLINUX_MUX_BASE        0xf2040000
+#define IDE_DMA_ADDR	0xfce00000
+
 #define _IO_BASE	0
 #define _ISA_MEM_BASE	0
 #define PCI_DRAM_OFFSET	0

arch/ppc/platforms/4xx/redwood5.c

@@ -9,9 +9,6 @@
  *    Description:
  *    	IBM redwood5 eval board file
  *
- *      History:  12/29/2001 - Armin
- *    	initail release
- *
  */
 
 #include <linux/config.h>
@@ -21,12 +18,12 @@
 #include <asm/machdep.h>
 
 void __init
-board_setup_arch(void)
+redwood5_setup_arch(void)
 {
+	bd_t *bip = &__res;
 
-	bd_t *bip = (bd_t *)__res;
+	ppc4xx_setup_arch();
 
-#define CONFIG_DEBUG_BRINGUP
 #ifdef CONFIG_DEBUG_BRINGUP
 	printk("\n");
 	printk("machine\t: %s\n", PPC4xx_MACHINE_NAME);
@@ -53,10 +50,11 @@ board_setup_arch(void)
 }
 
 void __init
-board_io_mapping(void)
+redwood5_map_io(void)
 {
 	int i;
 
+	ppc4xx_map_io();
 	for (i = 0; i < 16; i++) {
 	 unsigned long v, p;
 
@@ -72,11 +70,11 @@ board_io_mapping(void)
 }
 
 void __init
-board_setup_irq(void)
+platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
+	      unsigned long r6, unsigned long r7)
 {
-}
+	ppc4xx_init(r3, r4, r5, r6, r7);
 
-void __init
-board_init(void)
-{
+	ppc_md.setup_arch = redwood5_setup_arch;
+	ppc_md.setup_io_mappings = redwood5_map_io;
 }

arch/ppc/platforms/4xx/walnut.c

 /*
  *
- *    Copyrigh t(c) 1999-2000 Grant Erickson <grant@lcse.umn.edu>
+ *    Copyright(c) 1999-2000 Grant Erickson <grant@lcse.umn.edu>
  *
- *    Copyright 2000-2001 MontaVista Software Inc.
+ *    Copyright 2000-2002 MontaVista Software Inc.
  *      Completed implementation.
  *      Author: MontaVista Software, Inc.  <source@mvista.com>
  *
@@ -14,13 +14,6 @@
  *      code by Gary Thomas, Cort Dougan <cort@fsmlabs.com>, and Dan Malek
  *      <dan@net4x.com>.
  *
- *      History: 11/09/2001 - armin
- *      added board_init to add in additional instuctions needed during platfrom_init
- *
- *      01/22/2002 - Armin
- *      converted pci to ocp
- *
- *
  */
 #include <linux/config.h>
 #include <linux/init.h>
@@ -39,13 +32,8 @@
 #include <asm/page.h>
 #include <asm/time.h>
 #include <asm/io.h>
-#include <platforms/4xx/ibm_ocp.h>
-
-#ifdef CONFIG_PPC_RTC
+#include <asm/ibm_ocp_pci.h>
 #include <asm/todc.h>
-#endif
-
-#include "walnut.h"
 
 #undef DEBUG
 
@@ -82,8 +70,9 @@ ppc405_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
 };
 
 void __init
-board_setup_arch(void)
+walnut_setup_arch(void)
 {
+
 	void *fpga_brdc;
 	unsigned char fpga_brdc_data;
 	void *fpga_enable;
@@ -91,6 +80,8 @@ board_setup_arch(void)
 	void *fpga_status;
 	void *fpga_trigger;
 
+	ppc4xx_setup_arch();
+
 	kb_data = ioremap(WALNUT_PS2_BASE, 8);
 	if (!kb_data) {
 		printk(KERN_CRIT
@@ -123,20 +114,19 @@ board_setup_arch(void)
 
 	writeb(0x3, fpga_trigger);
 
-#ifdef CONFIG_PPC_RTC
 	/* RTC step for the walnut */
 	walnut_rtc_base = (void *) WALNUT_RTC_VADDR;
 	TODC_INIT(TODC_TYPE_DS1743, walnut_rtc_base, walnut_rtc_base,
 		  walnut_rtc_base, 8);
-#endif				/* CONFIG_PPC_RTC */
+	/* Identify the system */
+	printk("IBM Walnut port (C) 2000-2002 MontaVista Software, Inc. (source@mvista.com)\n");
 }
 
 void __init
-bios_fixup(struct pci_controller *hose, void *pcil0_base)
+bios_fixup(struct pci_controller *hose, struct pcil0_regs *pcip)
 {
-
+#ifdef CONFIG_PCI
 	unsigned int bar_response, bar;
-	struct pcil0_regs *pcip;
 	/*
 	 * Expected PCI mapping:
 	 *
@@ -155,7 +145,6 @@ bios_fixup(struct pci_controller *hose, void *pcil0_base)
 
 #ifdef DEBUG
 	int i;
-	pcip = (struct pcil0_regs *) pcil0_base;
 
 	printk("ioremap PCLIO_BASE = 0x%x\n", pcip);
 	printk("PCI bridge regs before fixup \n");
@@ -170,8 +159,6 @@ bios_fixup(struct pci_controller *hose, void *pcil0_base)
 	printk(" ptm2ms\t0x%x\n", in_le32(&(pcip->ptm2ms)));
 	printk(" ptm2la\t0x%x\n", in_le32(&(pcip->ptm2la)));
 
-#else
-	pcip = (struct pcil0_regs *) pcil0_base;
 #endif
 
 	/* added for IBM boot rom version 1.15 bios bar changes  -AK */
@@ -232,25 +219,28 @@ bios_fixup(struct pci_controller *hose, void *pcil0_base)
 	printk(" ptm2ms\t0x%x\n", in_le32(&(pcip->ptm2ms)));
 	printk(" ptm2la\t0x%x\n", in_le32(&(pcip->ptm2la)));
 
+#endif
 #endif
 }
 
 void __init
-board_io_mapping(void)
+walnut_map_io(void)
 {
+	ppc4xx_map_io();
 	io_block_mapping(WALNUT_RTC_VADDR,
 			 WALNUT_RTC_PADDR, WALNUT_RTC_SIZE, _PAGE_IO);
 }
 
 void __init
-board_setup_irq(void)
+platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
+	      unsigned long r6, unsigned long r7)
 {
-}
+	ppc4xx_init(r3, r4, r5, r6, r7);
 
-void __init
-board_init(void)
-{
-#ifdef CONFIG_PPC_RTC
+	ppc_md.setup_arch = walnut_setup_arch;
+	ppc_md.setup_io_mappings = walnut_map_io;
+
+#ifdef CONFIG_GEN_RTC
 	ppc_md.time_init = todc_time_init;
 	ppc_md.set_rtc_time = todc_set_rtc_time;
 	ppc_md.get_rtc_time = todc_get_rtc_time;

arch/ppc/platforms/4xx/walnut.h

@@ -60,10 +60,6 @@ extern void *walnut_rtc_base;
 #define WALNUT_RTC_VADDR	WALNUT_RTC_PADDR
 #define WALNUT_RTC_SIZE		((uint)8*1024)
 
-/* ps2 keyboard and mouse */
-#define KEYBOARD_IRQ		25
-#define AUX_IRQ			26
-
 #ifdef CONFIG_PPC405GP_INTERNAL_CLOCK
 #define BASE_BAUD		201600
 #else

arch/ppc/syslib/Makefile

@@ -12,14 +12,18 @@ endif
 CFLAGS_prom_init.o      += -mrelocatable-lib
 CFLAGS_btext.o          += -mrelocatable-lib
 
+export-objs			:=  ppc4xx_dma.o ppc4xx_pm.o
+
 obj-$(CONFIG_PPCBUG_NVRAM)	+= prep_nvram.o
 ifeq ($(CONFIG_4xx),y)
-obj-$(CONFIG_4xx)		+= ppc4xx_setup.o ppc4xx_pic.o ppc4xx_serial.o
-obj-$(CONFIG_PPC_RTC)		+= todc_time.o
+obj-$(CONFIG_4xx)		+= ppc4xx_pic.o
+obj-$(CONFIG_40x)		+= ppc4xx_setup.o
+obj-$(CONFIG_GEN_RTC)		+= todc_time.o
+obj-$(CONFIG_KGDB)		+= ppc4xx_kgdb.o
+ifeq ($(CONFIG_40x),y)
 obj-$(CONFIG_KGDB)		+= ppc4xx_kgdb.o
-obj-$(CONFIG_405_DMA)		+= ppc405_dma.o
-obj-$(CONFIG_PCI)		+= ppc405_pci.o indirect_pci.o pci_auto.o
-obj-$(CONFIG_PM)		+= ppc4xx_pm.o
+obj-$(CONFIG_PCI)		+= indirect_pci.o pci_auto.o ppc405_pci.o
+endif
 endif
 obj-$(CONFIG_8xx)		+= m8xx_setup.o ppc8xx_pic.o
 ifeq ($(CONFIG_8xx),y)

arch/ppc/syslib/ppc405_pci.c

@@ -7,6 +7,7 @@
  * Author: MontaVista Software, Inc.  <source@mvista.com>
  *         Frank Rowand <frank_rowand@mvista.com>
  *         Debbie Chu   <debbie_chu@mvista.com>
+ * Further modifications by Armin Kuster.
  *
  * Copyright 2000 MontaVista Software Inc.
  *
@@ -36,20 +37,16 @@
 #include <asm/system.h>
 #include <asm/machdep.h>
 #include <linux/init.h>
+#include <linux/errno.h>
+#include <asm/ocp.h>
 #include <asm/ibm4xx.h>
 #include <asm/pci-bridge.h>
-#include <platforms/4xx/ibm_ocp.h>
+#include <asm/ibm_ocp_pci.h>
 
-#ifdef  CONFIG_DEBUG_BRINGUP
-#define DBG(x...) printk(x)
-#else
-#define DBG(x...)
-#endif
-
-extern void bios_fixup(struct pci_controller *, void *);
+ 
+extern void bios_fixup(struct pci_controller *, struct pcil0_regs *);
 extern int ppc405_map_irq(struct pci_dev *dev, unsigned char idsel,
 			  unsigned char pin);
-extern struct pcil0_regs *PCIL_ADDR[];
 
 void
 ppc405_pcibios_fixup_resources(struct pci_dev *dev)
@@ -87,7 +84,7 @@ ppc405_pcibios_fixup_resources(struct pci_dev *dev)
 			    KERN_ERR "  fixup will be attempted later\n",
 			    min_host_addr, i, max_host_addr,
 			    dev->bus->number, PCI_SLOT(dev->devfn),
-			    PCI_FUNC(dev->devfn), dev->name);
+			    PCI_FUNC(dev->devfn), dev->slot.name);
 
 			/* force pcibios_assign_resources() to assign a new address */
 			res->end -= res->start;
@@ -120,19 +117,22 @@ ppc4xx_find_bridges(void)
 	isa_io_base = 0;
 	isa_mem_base = 0;
 	pci_dram_offset = 0;
-	
+
+#if  (PSR_PCI_ARBIT_EN > 1)
 	/* Check if running in slave mode */
 	if ((mfdcr(DCRN_CHPSR) & PSR_PCI_ARBIT_EN) == 0) {
 		printk("Running as PCI slave, kernel PCI disabled !\n");
 		return;
 	}
+#endif
 	/* Setup PCI32 hose */
 	hose_a = pcibios_alloc_controller();
 	if (!hose_a)
 		return;
 	setup_indirect_pci(hose_a, PPC405_PCI_CONFIG_ADDR,
 			   PPC405_PCI_CONFIG_DATA);
-	pcip = ioremap((unsigned long) PCIL_ADDR[0], PAGE_SIZE);
+
+	pcip = ioremap(PPC4xx_PCI_LCFG_PADDR, PAGE_SIZE);
 	if (pcip != NULL) {
 
 #if defined(CONFIG_BIOS_FIXUP)
@@ -140,68 +140,67 @@ ppc4xx_find_bridges(void)
 #endif
 		new_pmm_min = 0xffffffff;
 		for (reg_index = 0; reg_index < 3; reg_index++) {
-			tmp_size = in_le32((void *) &(pcip->pmm[reg_index].ma));	// *_PMM0MA
-			if (tmp_size & 0x1) {
-				tmp_addr = in_le32((void *) &(pcip->pmm[reg_index].pcila));	// *_PMM0PCILA
-				if (tmp_addr < PPC405_PCI_PHY_MEM_BASE) {
-					printk(KERN_DEBUG
-					       "Disabling mapping to PCI mem addr 0x%8.8x\n",
-					       tmp_addr);
-					out_le32((void *) &(pcip->pmm[reg_index].ma), tmp_size & ~1);	// *_PMMOMA
-				} else {
-					tmp_addr = in_le32((void *) &(pcip->pmm[reg_index].la));	// *_PMMOLA
-					if (tmp_addr < new_pmm_min)
-						new_pmm_min = tmp_addr;
-					tmp_addr =
-					    tmp_addr + (0xffffffff -
-							(tmp_size &
-							 0xffffc000));
-					if (tmp_addr > PPC405_PCI_UPPER_MEM) {
-						new_pmm_max = tmp_addr;	// PPC405_PCI_UPPER_MEM 
-					} else {
-						new_pmm_max =
-						    PPC405_PCI_UPPER_MEM;
-					}
-				}
+			tmp_size = in_le32(&pcip->pmm[reg_index].ma);	// mask & attrs
+			/* test the enable bit */
+			if ((tmp_size & 0x1) == 0)
+				continue;
+			tmp_addr = in_le32(&pcip->pmm[reg_index].pcila);	// PCI addr
+			if (tmp_addr < PPC405_PCI_PHY_MEM_BASE) {
+				printk(KERN_DEBUG
+				       "Disabling mapping to PCI mem addr 0x%8.8x\n",
+				       tmp_addr);
+				out_le32(&pcip->pmm[reg_index].ma, tmp_size & ~1);	// *_PMMOMA
+				continue;
+			}
+			tmp_addr = in_le32(&pcip->pmm[reg_index].la);	// *_PMMOLA
+			if (tmp_addr < new_pmm_min)
+				new_pmm_min = tmp_addr;
+			tmp_addr = tmp_addr +
+				(0xffffffff - (tmp_size & 0xffffc000));
+			if (tmp_addr > PPC405_PCI_UPPER_MEM) {
+				new_pmm_max = tmp_addr;	// PPC405_PCI_UPPER_MEM 
+			} else {
+				new_pmm_max = PPC405_PCI_UPPER_MEM;
 			}
 
 		}		// for
 
 		iounmap(pcip);
 	}
-	hose_a->first_busno      = 0;
-	hose_a->last_busno       = 0xff;
-	hose_a->pci_mem_offset   = 0;
+
+	hose_a->first_busno = 0;
+	hose_a->last_busno = 0xff;
+	hose_a->pci_mem_offset = 0;
 
 	/* Setup bridge memory/IO ranges & resources
 	 * TODO: Handle firmwares setting up a legacy ISA mem base
 	 */
-	hose_a->io_space.start		= PPC405_PCI_LOWER_IO;
-	hose_a->io_space.end		= PPC405_PCI_UPPER_IO;
-	hose_a->mem_space.start		= new_pmm_min;
-	hose_a->mem_space.end		= new_pmm_max;
-	hose_a->io_base_phys		= PPC405_PCI_PHY_IO_BASE;
-	hose_a->io_base_virt		= ioremap(hose_a->io_base_phys, 0x10000);
-	hose_a->io_resource.start	= 0;
-	hose_a->io_resource.end		= PPC405_PCI_UPPER_IO-PPC405_PCI_LOWER_IO;
-	hose_a->io_resource.flags	= IORESOURCE_IO;
-	hose_a->io_resource.name	= "PCI I/O";
-	hose_a->mem_resources[0].start	= new_pmm_min;
-	hose_a->mem_resources[0].end	= new_pmm_max;
-	hose_a->mem_resources[0].flags	= IORESOURCE_MEM;
-	hose_a->mem_resources[0].name	= "PCI Memory";
-	isa_io_base			= (int)hose_a->io_base_virt;
-	isa_mem_base			= 0;	      /*     ISA not implemented */
-	ISA_DMA_THRESHOLD		= 0x00ffffff; /* ??? ISA not implemented */
+	hose_a->io_space.start = PPC405_PCI_LOWER_IO;
+	hose_a->io_space.end = PPC405_PCI_UPPER_IO;
+	hose_a->mem_space.start = new_pmm_min;
+	hose_a->mem_space.end = new_pmm_max;
+	hose_a->io_base_phys = PPC405_PCI_PHY_IO_BASE;
+	hose_a->io_base_virt = ioremap(hose_a->io_base_phys, 0x10000);
+	hose_a->io_resource.start = 0;
+	hose_a->io_resource.end = PPC405_PCI_UPPER_IO - PPC405_PCI_LOWER_IO;
+	hose_a->io_resource.flags = IORESOURCE_IO;
+	hose_a->io_resource.name = "PCI I/O";
+	hose_a->mem_resources[0].start = new_pmm_min;
+	hose_a->mem_resources[0].end = new_pmm_max;
+	hose_a->mem_resources[0].flags = IORESOURCE_MEM;
+	hose_a->mem_resources[0].name = "PCI Memory";
+	isa_io_base = (int) hose_a->io_base_virt;
+	isa_mem_base = 0;	/*     ISA not implemented */
+	ISA_DMA_THRESHOLD = 0x00ffffff;	/* ??? ISA not implemented */
 
 	/* Scan busses & initial setup by pci_auto */
 	hose_a->last_busno = pciauto_bus_scan(hose_a, hose_a->first_busno);
 	hose_a->last_busno = 0;
 
 	/* Setup ppc_md */
-	ppc_md.pcibios_fixup     	= NULL;
-	ppc_md.pci_exclude_device	= ppc4xx_exclude_device;
-	ppc_md.pcibios_fixup_resources	= ppc405_pcibios_fixup_resources;
-	ppc_md.pci_swizzle		= common_swizzle;
-	ppc_md.pci_map_irq		= ppc405_map_irq;
+	ppc_md.pcibios_fixup = NULL;
+	ppc_md.pci_exclude_device = ppc4xx_exclude_device;
+	ppc_md.pcibios_fixup_resources = ppc405_pcibios_fixup_resources;
+	ppc_md.pci_swizzle = common_swizzle;
+	ppc_md.pci_map_irq = ppc405_map_irq;
 }

arch/ppc/syslib/ppc4xx_pic.c

@@ -38,6 +38,13 @@
 
 /* Global Variables */
 struct hw_interrupt_type *ppc4xx_pic;
+/*
+ * We define 4xxIRQ_InitSenses table thusly:
+ * bit 0x1: sense, 1 for edge and 0 for level.
+ * bit 0x2: polarity, 0 for negative, 1 for positive.
+ */
+unsigned int ibm4xxPIC_NumInitSenses __initdata = 0;
+unsigned char *ibm4xxPIC_InitSenses __initdata = NULL;
 
 /* Six of one, half dozen of the other....#ifdefs, separate files,
  * other tricks.....
@@ -140,21 +147,42 @@ static void
 ppc405_uic_enable(unsigned int irq)
 {
 	int bit, word;
+	irq_desc_t *desc = irq_desc + irq;
 
 	bit = irq & 0x1f;
 	word = irq >> 5;
-#ifdef UIC_DEBUG	
-	printk("ppc405_uic_enable - irq %d word %d bit 0x%x\n",irq, word , bit);
+
+#ifdef UIC_DEBUG
+	printk("ppc405_uic_enable - irq %d word %d bit 0x%x\n", irq, word, bit);
 #endif
 	ppc_cached_irq_mask[word] |= 1 << (31 - bit);
-	switch (word){
-		case 0:
-			mtdcr(DCRN_UIC_ER(UIC0), ppc_cached_irq_mask[word]);
-		break;
-		case 1:
-			mtdcr(DCRN_UIC_ER(UIC1), ppc_cached_irq_mask[word]);
+	switch (word) {
+	case 0:
+		mtdcr(DCRN_UIC_ER(UIC0), ppc_cached_irq_mask[word]);
+		if ((mfdcr(DCRN_UIC_TR(UIC0)) & (1 << (31 - bit))) == 0)
+			desc->status |= IRQ_LEVEL;
+		else
+		/* lets hope this works since in linux/irq.h
+		 * there is no define for EDGE and it's assumed
+		 * once you set status to LEVEL you would not 
+		 * want to change it - Armin
+		 */
+		desc->status = desc->status & ~IRQ_LEVEL;
 		break;
+	case 1:
+		mtdcr(DCRN_UIC_ER(UIC1), ppc_cached_irq_mask[word]);
+		if ((mfdcr(DCRN_UIC_TR(UIC1)) & (1 << (31 - bit))) == 0)
+			desc->status |= IRQ_LEVEL;
+		else
+		/* lets hope this works since in linux/irq.h
+		 * there is no define for EDGE and it's assumed
+		 * once you set status to LEVEL you would not 
+		 * want to change it - Armin
+		 */
+		desc->status = desc->status & ~IRQ_LEVEL;
+	break;
 	}
+
 }
 
 static void
@@ -164,16 +192,17 @@ ppc405_uic_disable(unsigned int irq)
 
 	bit = irq & 0x1f;
 	word = irq >> 5;
-#ifdef UIC_DEBUG	
-	printk("ppc405_uic_disable - irq %d word %d bit 0x%x\n",irq, word , bit);
+#ifdef UIC_DEBUG
+	printk("ppc405_uic_disable - irq %d word %d bit 0x%x\n", irq, word,
+	       bit);
 #endif
 	ppc_cached_irq_mask[word] &= ~(1 << (31 - bit));
-	switch (word){
-		case 0:
-			mtdcr(DCRN_UIC_ER(UIC0), ppc_cached_irq_mask[word]);
+	switch (word) {
+	case 0:
+		mtdcr(DCRN_UIC_ER(UIC0), ppc_cached_irq_mask[word]);
 		break;
-		case 1:
-			mtdcr(DCRN_UIC_ER(UIC1), ppc_cached_irq_mask[word]);
+	case 1:
+		mtdcr(DCRN_UIC_ER(UIC1), ppc_cached_irq_mask[word]);
 		break;
 	}
 }
@@ -186,18 +215,19 @@ ppc405_uic_disable_and_ack(unsigned int irq)
 	bit = irq & 0x1f;
 	word = irq >> 5;
 
-#ifdef UIC_DEBUG	
-printk("ppc405_uic_disable_and_ack - irq %d word %d bit 0x%x\n",irq, word , bit);
+#ifdef UIC_DEBUG
+	printk("ppc405_uic_disable_and_ack - irq %d word %d bit 0x%x\n", irq,
+	       word, bit);
 #endif
 	ppc_cached_irq_mask[word] &= ~(1 << (31 - bit));
-	switch (word){
-		case 0:
-			mtdcr(DCRN_UIC_ER(UIC0), ppc_cached_irq_mask[word]);
-			mtdcr(DCRN_UIC_SR(UIC0), (1 << (31 - bit)));
+	switch (word) {
+	case 0:
+		mtdcr(DCRN_UIC_ER(UIC0), ppc_cached_irq_mask[word]);
+		mtdcr(DCRN_UIC_SR(UIC0), (1 << (31 - bit)));
 		break;
-		case 1:	
-			mtdcr(DCRN_UIC_ER(UIC1), ppc_cached_irq_mask[word]);
-			mtdcr(DCRN_UIC_SR(UIC1), (1 << (31 - bit)));
+	case 1:
+		mtdcr(DCRN_UIC_ER(UIC1), ppc_cached_irq_mask[word]);
+		mtdcr(DCRN_UIC_SR(UIC1), (1 << (31 - bit)));
 		break;
 	}
 }
@@ -211,40 +241,39 @@ ppc405_uic_end(unsigned int irq)
 	bit = irq & 0x1f;
 	word = irq >> 5;
 
-#ifdef UIC_DEBUG	
-	printk("ppc405_uic_end - irq %d word %d bit 0x%x\n",irq, word , bit);
+#ifdef UIC_DEBUG
+	printk("ppc405_uic_end - irq %d word %d bit 0x%x\n", irq, word, bit);
 #endif
 
-	switch (word){
-		case 0:
-			tr_bits = mfdcr(DCRN_UIC_TR(UIC0));
+	switch (word) {
+	case 0:
+		tr_bits = mfdcr(DCRN_UIC_TR(UIC0));
 		break;
-		case 1:
-			tr_bits = mfdcr(DCRN_UIC_TR(UIC1));
+	case 1:
+		tr_bits = mfdcr(DCRN_UIC_TR(UIC1));
 		break;
 	}
 
 	if ((tr_bits & (1 << (31 - bit))) == 0) {
 		/* level trigger */
-		switch (word){
-			case 0:
-				mtdcr(DCRN_UIC_SR(UIC0), 1 << (31 - bit));
+		switch (word) {
+		case 0:
+			mtdcr(DCRN_UIC_SR(UIC0), 1 << (31 - bit));
 			break;
-			case 1:
-				mtdcr(DCRN_UIC_SR(UIC1), 1 << (31 - bit));
+		case 1:
+			mtdcr(DCRN_UIC_SR(UIC1), 1 << (31 - bit));
 			break;
 		}
 	}
 
-	if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))
-	    && irq_desc[irq].action) {
+	if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) {
 		ppc_cached_irq_mask[word] |= 1 << (31 - bit);
-		switch (word){
-			case 0:
-				mtdcr(DCRN_UIC_ER(UIC0), ppc_cached_irq_mask[word]);
+		switch (word) {
+		case 0:
+			mtdcr(DCRN_UIC_ER(UIC0), ppc_cached_irq_mask[word]);
 			break;
-			case 1:
-				mtdcr(DCRN_UIC_ER(UIC1), ppc_cached_irq_mask[word]);
+		case 1:
+			mtdcr(DCRN_UIC_ER(UIC1), ppc_cached_irq_mask[word]);
 			break;
 		}
 	}
@@ -278,15 +307,15 @@ ppc405_pic_get_irq(struct pt_regs *regs)
 
 	bits = mfdcr(DCRN_UIC_MSR(UIC0));
 
-#if (NR_UICS > 1) 
-	if (bits & UIC_CASCADE_MASK){
+#if (NR_UICS > 1)
+	if (bits & UIC_CASCADE_MASK) {
 		bits = mfdcr(DCRN_UIC_MSR(UIC1));
 		cas_irq = 32 - ffs(bits);
 		irq = 32 + cas_irq;
 	} else {
 		irq = 32 - ffs(bits);
 		if (irq == 32)
-			irq= -1;
+			irq = -1;
 	}
 #else
 	/*
@@ -301,16 +330,82 @@ ppc405_pic_get_irq(struct pt_regs *regs)
 		irq = -1;
 
 #ifdef UIC_DEBUG
-printk("ppc405_pic_get_irq - irq %d bit 0x%x\n",irq, bits);
+	printk("ppc405_pic_get_irq - irq %d bit 0x%x\n", irq, bits);
 #endif
 
 	return (irq);
 }
 #endif
 
+void __init
+ppc4xx_extpic_init(void)
+{
+	/* set polarity 
+	 * 1 = default/pos/rising  , 0= neg/falling internal
+	 * 1 = neg/falling , 0= pos/rising external
+	 * Sense
+	 * 0 = default level internal
+	 * 0 = level, 1 = edge external
+	 */
+
+	unsigned int sense, irq;
+	int bit, word;
+	unsigned long ppc_cached_sense_mask[NR_MASK_WORDS];
+	unsigned long ppc_cached_pol_mask[NR_MASK_WORDS];
+	ppc_cached_sense_mask[0] = 0;
+	ppc_cached_sense_mask[1] = 0;
+	ppc_cached_pol_mask[0] = 0;
+	ppc_cached_pol_mask[1] = 0;
+
+	for (irq = 0; irq < NR_IRQS; irq++) {
+
+		bit = irq & 0x1f;
+		word = irq >> 5;
+
+		sense =
+		    (irq <
+		     ibm4xxPIC_NumInitSenses) ? ibm4xxPIC_InitSenses[irq] : 3;
+#ifdef PPC4xx_PIC_DEBUG
+		printk("PPC4xx_picext %d word:%x bit:%x sense:%x", irq, word,
+		       bit, sense);
+#endif
+		ppc_cached_sense_mask[word] |=
+		    (sense & IRQ_SENSE_MASK) << (31 - bit);
+		ppc_cached_pol_mask[word] |=
+		    ((sense & IRQ_POLARITY_MASK) >> 1) << (31 - bit);
+		switch (word) {
+		case 0:
+#ifdef PPC4xx_PIC_DEBUG
+			printk("Pol %x ", mfdcr(DCRN_UIC_PR(UIC0)));
+			printk("Level %x\n", mfdcr(DCRN_UIC_TR(UIC0)));
+#endif
+			/* polarity  setting */
+			mtdcr(DCRN_UIC_PR(UIC0), ppc_cached_pol_mask[word]);
+
+			/* Level setting */
+			mtdcr(DCRN_UIC_TR(UIC0), ppc_cached_sense_mask[word]);
+
+			break;
+		case 1:
+#ifdef PPC4xx_PIC_DEBUG
+			printk("Pol %x ", mfdcr(DCRN_UIC_PR(UIC1)));
+			printk("Level %x\n", mfdcr(DCRN_UIC_TR(UIC1)));
+#endif
+			/* polarity  setting */
+			mtdcr(DCRN_UIC_PR(UIC1), ppc_cached_pol_mask[word]);
+
+			/* Level setting */
+			mtdcr(DCRN_UIC_TR(UIC1), ppc_cached_sense_mask[word]);
+
+			break;
+		}
+	}
+
+}
 void __init
 ppc4xx_pic_init(void)
 {
+
 	/*
 	 * Disable all external interrupts until they are
 	 * explicity requested.
@@ -324,25 +419,26 @@ ppc4xx_pic_init(void)
 	ppc4xx_pic = &ppc403_aic;
 	ppc_md.get_irq = ppc403_pic_get_irq;
 #else
-#if  (NR_UICS > 1) 
-	ppc_cached_irq_mask[0] |= 1 << (31 - UIC0_UIC1NC ); /* enable cascading interrupt */
-	mtdcr(DCRN_UIC_ER(UIC0), ppc_cached_irq_mask[0]);
+#if  (NR_UICS > 1)
+	ppc_cached_irq_mask[0] |= 1 << (31 - UIC0_UIC1NC);	/* enable cascading interrupt */
 	mtdcr(DCRN_UIC_ER(UIC1), ppc_cached_irq_mask[1]);
-
-	/* Set all interrupts to non-critical.
-	 */
-	mtdcr(DCRN_UIC_CR(UIC0), 0);
 	mtdcr(DCRN_UIC_CR(UIC1), 0);
 
-#else	
+#endif
 	mtdcr(DCRN_UIC_ER(UIC0), ppc_cached_irq_mask[0]);
-
-	/* Set all interrupts to non-critical.
-	 */
 	mtdcr(DCRN_UIC_CR(UIC0), 0);
+	
+	if (ibm4xxPIC_InitSenses != NULL)
+		ppc4xx_extpic_init();
+
+	/* Clear any pending interrupts */
+#if (NR_UICS > 1)
+	mtdcr(DCRN_UIC_SR(UIC1), 0xffffffff);
 #endif
+	mtdcr(DCRN_UIC_SR(UIC0), 0xffffffff);
 
 	ppc4xx_pic = &ppc405_uic;
 	ppc_md.get_irq = ppc405_pic_get_irq;
 #endif
+
 }

arch/ppc/syslib/ppc4xx_setup.c

@@ -7,23 +7,10 @@
  *      Author: MontaVista Software, Inc.  <source@mvista.com>
  *              Frank Rowand <frank_rowand@mvista.com>
  *              Debbie Chu   <debbie_chu@mvista.com>
+ *	Further modifications by Armin Kuster
  *
  *    Module name: ppc4xx_setup.c
  *
- *    Description:
- *      Architecture- / platform-specific boot-time initialization code for
- *      IBM PowerPC 4xx based boards. Adapted from original
- *      code by Gary Thomas, Cort Dougan <cort@fsmlabs.com>, and Dan Malek
- *      <dan@net4x.com>.
- *
- * 	History: 11/09/2001 - armin
- *	rename board_setup_nvram_access to board_init. board_init is
- *	used for all other board specific instructions needed during
- *	platform_init.
- *	moved RTC to board.c files
- *	moved VT/FB to board.c files
- *	moved r/w4 ide to redwood.c
- *
  */
 
 #include <linux/config.h>
@@ -63,19 +50,12 @@ extern void ppc4xx_wdt_heartbeat(void);
 extern int wdt_enable;
 extern unsigned long wdt_period;
 
-/* Board specific functions */
-extern void board_setup_arch(void);
-extern void board_io_mapping(void);
-extern void board_setup_irq(void);
-extern void board_init(void);
-
 /* Global Variables */
-unsigned char __res[sizeof (bd_t)];
+bd_t __res;
 
-static void __init
+void __init
 ppc4xx_setup_arch(void)
 {
-
 	/* Setup PCI host bridges */
 
 #ifdef CONFIG_PCI
@@ -85,8 +65,6 @@ ppc4xx_setup_arch(void)
 #if defined(CONFIG_FB)
 	conswitchp = &dummy_con;
 #endif
-
-	board_setup_arch();
 }
 
 /*
@@ -97,9 +75,7 @@ ppc4xx_setup_arch(void)
 static int
 ppc4xx_show_percpuinfo(struct seq_file *m, int i)
 {
-	bd_t *bip = (bd_t *) __res;
-
-	seq_printf(m, "clock\t\t: %ldMHz\n", (long) bip->bi_intfreq / 1000000);
+	seq_printf(m, "clock\t\t: %ldMHz\n", (long)__res.bi_intfreq / 1000000);
 
 	return 0;
 }
@@ -111,7 +87,7 @@ ppc4xx_show_percpuinfo(struct seq_file *m, int i)
 static int
 ppc4xx_show_cpuinfo(struct seq_file *m)
 {
-	bd_t *bip = (bd_t *) __res;
+	bd_t *bip = &__res;
 
 	seq_printf(m, "machine\t\t: %s\n", PPC4xx_MACHINE_NAME);
 	seq_printf(m, "plb bus clock\t: %ldMHz\n",
@@ -130,13 +106,11 @@ ppc4xx_show_cpuinfo(struct seq_file *m)
 static unsigned long __init
 ppc4xx_find_end_of_memory(void)
 {
-	bd_t *bip = (bd_t *) __res;
-
-	return ((unsigned long) bip->bi_memsize);
+	return ((unsigned long) __res.bi_memsize);
 }
 
-static void __init
-m4xx_map_io(void)
+void __init
+ppc4xx_map_io(void)
 {
 	io_block_mapping(PPC4xx_ONB_IO_VADDR,
 			 PPC4xx_ONB_IO_PADDR, PPC4xx_ONB_IO_SIZE, _PAGE_IO);
@@ -148,10 +122,9 @@ m4xx_map_io(void)
 	io_block_mapping(PPC4xx_PCI_LCFG_VADDR,
 			 PPC4xx_PCI_LCFG_PADDR, PPC4xx_PCI_LCFG_SIZE, _PAGE_IO);
 #endif
-	board_io_mapping();
 }
 
-static void __init
+void __init
 ppc4xx_init_IRQ(void)
 {
 	int i;
@@ -160,10 +133,6 @@ ppc4xx_init_IRQ(void)
 
 	for (i = 0; i < NR_IRQS; i++)
 		irq_desc[i].handler = ppc4xx_pic;
-
-	/* give board specific code a chance to setup things */
-	board_setup_irq();
-	return;
 }
 
 static void
@@ -199,19 +168,13 @@ static void __init
 ppc4xx_calibrate_decr(void)
 {
 	unsigned int freq;
-	bd_t *bip = (bd_t *) __res;
+	bd_t *bip = &__res;
 
-#if defined(CONFIG_WALNUT) || defined(CONFIG_CEDER)
+#if defined(CONFIG_WALNUT) || defined(CONFIG_CEDER)|| defined(CONFIG_ASH) || defined(CONFIG_SYCAMORE)
 	/* Walnut boot rom sets DCR CHCR1 (aka CPC0_CR1) bit CETE to 1 */
 	mtdcr(DCRN_CHCR1, mfdcr(DCRN_CHCR1) & ~CHR1_CETE);
 #endif
-#ifdef CONFIG_REDWOOD_5
 	freq = bip->bi_tbfreq;
-#else
-	freq = bip->bi_intfreq;
-
-#endif
-
 	tb_ticks_per_jiffy = freq / HZ;
 	tb_to_us = mulhwu_scale_factor(freq, 1000000);
 
@@ -230,20 +193,40 @@ ppc4xx_calibrate_decr(void)
 	/* Set the PIT reload value and just let it run. */
 	mtspr(SPRN_PIT, tb_ticks_per_jiffy);
 }
+#ifdef CONFIG_SERIAL_TEXT_DEBUG
 
-#ifdef CONFIG_DEBUG_TEXT
+/* We assume that the UART has already been initialized by the
+   firmware or the boot loader */
 static void
-ppc4xx_progress(char *s, unsigned short hex)
+serial_putc(u8 * com_port, unsigned char c)
 {
-	printk("%s\n\r", s);
+	while ((readb(com_port + (UART_LSR)) & UART_LSR_THRE) == 0) ;
+	writeb(c, com_port);
 }
+
+static void
+ppc4xx_progress(char *s, unsigned short hex)
+{
+	char c;
+#ifdef SERIAL_DEBUG_IO_BASE
+	u8 *com_port = (u8 *) SERIAL_DEBUG_IO_BASE;
+
+	while ((c = *s++) != '\0') {
+		serial_putc(com_port, c);
+	}
+	serial_putc(com_port, '\r');
+	serial_putc(com_port, '\n');
+#else
+	printk("%s\r\n");
 #endif
+}
+#endif				/* CONFIG_SERIAL_TEXT_DEBUG */
 
 /*
  * IDE stuff.
  * should be generic for every IDE PCI chipset
  */
-#ifdef  CONFIG_PCI
+#if defined(CONFIG_PCI) && defined(CONFIG_IDE)
 static void
 ppc4xx_ide_init_hwif_ports(hw_regs_t * hw, ide_ioreg_t data_port,
 			   ide_ioreg_t ctrl_port, int *irq)
@@ -255,7 +238,7 @@ ppc4xx_ide_init_hwif_ports(hw_regs_t * hw, ide_ioreg_t data_port,
 
 	hw->io_ports[IDE_CONTROL_OFFSET] = ctrl_port;
 }
-#endif
+#endif /* defined(CONFIG_PCI) && defined(CONFIG_IDE) */
 
 TODC_ALLOC();
 
@@ -272,8 +255,8 @@ TODC_ALLOC();
  *        command-line parameters.
  */
 void __init
-platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
-	      unsigned long r6, unsigned long r7)
+ppc4xx_init(unsigned long r3, unsigned long r4, unsigned long r5,
+	    unsigned long r6, unsigned long r7)
 {
 	parse_bootinfo(find_bootinfo());
 
@@ -281,11 +264,9 @@ platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
 	 * If we were passed in a board information, copy it into the
 	 * residual data area.
 	 */
-	if (r3) {
-		memcpy((void *) __res, (void *) (r3 + KERNELBASE),
-		       sizeof (bd_t));
+	if (r3)
+		__res = *(bd_t *)(r3 + KERNELBASE);
 
-	}
 #if defined(CONFIG_BLK_DEV_INITRD)
 	/*
 	 * If the init RAM disk has been configured in, and there's a valid
@@ -320,7 +301,7 @@ platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
 	}
 #endif
 
-	/* Initialize machine-dependency vectors */
+	/* Initialize machine-dependent vectors */
 
 	ppc_md.setup_arch = ppc4xx_setup_arch;
 	ppc_md.show_percpuinfo = ppc4xx_show_percpuinfo;
@@ -339,9 +320,9 @@ platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
 	ppc_md.heartbeat_count = 0;
 
 	ppc_md.find_end_of_memory = ppc4xx_find_end_of_memory;
-	ppc_md.setup_io_mappings = m4xx_map_io;
+	ppc_md.setup_io_mappings = ppc4xx_map_io;
 
-#ifdef CONFIG_DEBUG_TEXT
+#ifdef CONFIG_SERIAL_TEXT_DEBUG
 	ppc_md.progress = ppc4xx_progress;
 #endif
 
@@ -349,12 +330,7 @@ platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
 **   m8xx_setup.c, prep_setup.c use
 **     defined(CONFIG_BLK_DEV_IDE) || defined(CONFIG_BLK_DEV_IDE_MODULE)
 */
-#ifdef CONFIG_IDE
-# ifdef CONFIG_PCI
+#if defined(CONFIG_PCI) && defined(CONFIG_IDE)
 	ppc_ide_md.ide_init_hwif = ppc4xx_ide_init_hwif_ports;
-# endif
-#endif
-	board_init();
-
-	return;
+#endif /* defined(CONFIG_PCI) && defined(CONFIG_IDE) */
 }

include/asm-ppc/ibm403.h

 /*
  * ibm403.h
  *
- *	This was dirived from the ibm4xx.h and all 403 specific definitions
- *	where moved here.
+ *	This was derived from the ibm4xx.h and all 403 specific definitions
+ *	were moved here.
  *	
  *      Armin Kuster <akuster@mvista.com>
  *      Tom Rini <trini@mvista.com>
@@ -30,11 +30,6 @@
  *  You should have received a copy of the  GNU General Public License along
  *  with this program; if not, write  to the Free Software Foundation, Inc.,
  *  675 Mass Ave, Cambridge, MA 02139, USA.
- *
- *	Version 1.0 Oct 10, 2001 - A. Kuster
- *	Initial version	 - moved 403  specific out of ibm4xx.h 
- *	Version 1.1 Oct 25, 2001 - T. Rini
- *	Lots of cleanups.
  */
 
 

include/asm-ppc/ibm405.h

@@ -29,12 +29,6 @@
  *  You should have received a copy of the  GNU General Public License along
  *  with this program; if not, write  to the Free Software Foundation, Inc.,
  *  675 Mass Ave, Cambridge, MA 02139, USA.
- *
- *	Version 1.0 (02/01/17) - A. Kuster
- *	Initial version	 - moved 405  specific out of the other core.h's
- *
- *	Version 1.0 (02/08/02) - A. Kuster
- *	removed DCRN_UIC1_BASE to NP405L & H
  */
 
 #ifdef __KERNEL__
@@ -56,6 +50,11 @@
 #define ET_BUSERR	4
 #define ET_BUSTO	6
 
+/* Clock and power management shifts for emacs */
+#define IBM_CPM_EMMII	0	/* Shift value for MII */
+#define IBM_CPM_EMRX	1	/* Shift value for recv */
+#define IBM_CPM_EMTX	2	/* Shift value for MAC */
+
 #ifdef DCRN_CHCR_BASE
 #define DCRN_CHCR0	(DCRN_CHCR_BASE + 0x0)	/* Chip Control Register 1 */
 #define DCRN_CHCR1	(DCRN_CHCR_BASE + 0x1)	/* Chip Control Register 2 */
@@ -234,16 +233,6 @@
 #define DCRN_MALRCBS0(base)	((base) + 0x60)	/* Channel Rx 0 Channel Buffer Size */
 #define DCRN_MALRCBS1(base)	((base) + 0x61)	/* Channel Rx 1 Channel Buffer Size */
 
-/* EMAC DCRN's */
-#define DCRN_MALRXCTP2R(base)	((base) + 0x42)	/* Channel Rx 2 Channel Table Pointer */
-#define DCRN_MALRXCTP3R(base)	((base) + 0x43)	/* Channel Rx 3 Channel Table Pointer */
-#define DCRN_MALTXCTP4R(base)	((base) + 0x24)	/* Channel Tx 4 Channel Table Pointer */
-#define DCRN_MALTXCTP5R(base)	((base) + 0x25)	/* Channel Tx 5 Channel Table Pointer */
-#define DCRN_MALTXCTP6R(base)	((base) + 0x26)	/* Channel Tx 6 Channel Table Pointer */
-#define DCRN_MALTXCTP7R(base)	((base) + 0x27)	/* Channel Tx 7 Channel Table Pointer */
-#define DCRN_MALRCBS2(base)	((base) + 0x62)	/* Channel Rx 2 Channel Buffer Size */
-#define DCRN_MALRCBS3(base)	((base) + 0x63)	/* Channel Rx 3 Channel Buffer Size */
-
  /* DCRN_MALCR */
 #define MALCR_MMSR		0x80000000	/* MAL Software reset */
 #define MALCR_PLBP_1		0x00400000	/* MAL reqest priority: */

include/asm-ppc/ibm4xx.h

@@ -16,14 +16,56 @@
 
 #include <linux/config.h>
 
+#ifdef CONFIG_4xx
+
+#ifndef __ASSEMBLY__
+
+/* Device Control Registers */
+
+#define stringify(s)	tostring(s)
+#define tostring(s)	#s
+
+#define mfdcr(rn) mfdcr_or_dflt(rn, 0)
+
+#define mfdcr_or_dflt(rn,default_rval) \
+	({unsigned int rval;						\
+	if (rn == 0)							\
+		rval = default_rval;					\
+	else								\
+		asm volatile("mfdcr %0," stringify(rn) : "=r" (rval));	\
+	rval;})
+
+#define mtdcr(rn, v)  \
+do {                  \
+	if (rn != 0) \
+		asm volatile("mtdcr " stringify(rn) ",%0" : : "r" (v));	\
+} while (0)
+
+/* R/W of indirect DCRs make use of standard naming conventions for DCRs */
+
+#define mfdcri(base, reg)			\
+({						\
+     mtdcr(base##_CFGADDR, base##_##reg);	\
+     mfdcr(base##_CFGDATA);			\
+})
+
+#define mtdcri(base, reg, data)			\
+do {						\
+     mtdcr(base##_CFGADDR, base##_##reg);	\
+     mtdcr(base##_CFGDATA, data);		\
+} while (0)
+#endif /* __ASSEMBLY__ */
+
+#endif /* CONFIG_4xx */
+
 #ifdef CONFIG_40x
 
 #if defined(CONFIG_ASH)
 #include <platforms/4xx/ash.h>
 #endif
 
-#if defined (CONFIG_CEDER)
-#include <platforms/4xx/ceder.h>
+#if defined (CONFIG_CEDAR)
+#include <platforms/4xx/cedar.h>
 #endif
 
 #if defined(CONFIG_CPCI405)
@@ -50,12 +92,26 @@
 #include <platforms/4xx/walnut.h>
 #endif
 
+#ifndef __ASSEMBLY__
+
+/*
+ * The "residual" board information structure the boot loader passes
+ * into the kernel.
+ */
+extern bd_t __res;
+
+void ppc4xx_setup_arch(void);
+void ppc4xx_map_io(void);
+void ppc4xx_init_IRQ(void);
+void ppc4xx_init(unsigned long r3, unsigned long r4, unsigned long r5,
+		 unsigned long r6, unsigned long r7);
+#endif
+
 #ifndef PPC4xx_MACHINE_NAME
 #define PPC4xx_MACHINE_NAME	"Unidentified 4xx class"
 #endif
 
 
-
 /* IO_BASE is for PCI I/O.
  * ISA not supported, just here to resolve copilation.
  */
@@ -66,33 +122,7 @@
 #define PCI_DRAM_OFFSET	0
 #endif
 
-/*
- * The "residual" board information structure the boot loader passes
- * into the kernel.
- */
-#ifndef __ASSEMBLY__
-extern unsigned char __res[];
-
-/* Device Control Registers */
-
-#define stringify(s)	tostring(s)
-#define tostring(s)	#s
 
-#define mfdcr(rn) mfdcr_or_dflt(rn, 0)
-
-#define mfdcr_or_dflt(rn,default_rval) \
-	({unsigned int rval;						\
-	if (rn == 0)							\
-		rval = default_rval;					\
-	else								\
-		asm volatile("mfdcr %0," stringify(rn) : "=r" (rval));	\
-	rval;})
-
-#define mtdcr(rn, v)  \
-	{if (rn != 0) \
-		asm volatile("mtdcr " stringify(rn) ",%0" : : "r" (v));}
-
-#endif /* __ASSEMBLY__ */
 #endif /* CONFIG_40x */
 #endif /* __ASM_IBM4XX_H__ */
 #endif /* __KERNEL__ */

arch/ppc/platforms/4xx/ibm_ocp.h → include/asm-ppc/ibm_ocp_pci.h

 /*
- * ibm_ocp.h
+ * ibm_ocp_pci.h
  *
- *	This was dirived from the ppc4xx.h and all 405GP specific definition and board
- *	inclusions where moved here.
+ *	This was derived from the ibm_ocp.h 
  *
  * 	Current Maintainer
  *      Armin Kuster akuster@mvista.com
- *      Nov, 2001
+ *      AUg, 2002 
  *
  *
- * Copyright 2001 MontaVista Softare Inc.
+ * Copyright 2001-2002 MontaVista Softare Inc.
  *
  * This program is free software; you can redistribute  it and/or modify it
  *  under  the terms of  the GNU General  Public License as published by the
@@ -30,19 +29,13 @@
  *  You should have received a copy of the  GNU General Public License along
  *  with this program; if not, write  to the Free Software Foundation, Inc.,
  *  675 Mass Ave, Cambridge, MA 02139, USA.
- *
- *	Version 1.0 (01/11/26) - A. Kuster
- *	Initial version	 -
  */
 
 #ifdef __KERNEL__
-#ifndef __ASM_IBM_OCP_H__
-#define __ASM_IBM_OCP_H__
-
-#ifndef __ASSEMBLY__
-#include <linux/types.h>
+#ifndef __ASM_IBM_OCP_PCI_H__
+#define __ASM_IBM_OCP_PCI_H__
 
- /* PCI 32 */
+/* PCI 32 */
 
 struct pmm_regs {
 	u32 la;
@@ -59,134 +52,5 @@ typedef struct pcil0_regs {
 	u32 ptm2la;
 } pci0_t;
 
-/* Serial Ports */
-
-#define thr rbr
-#define iir fcr
-#define dll rbr
-#define dlm ier
-
-typedef struct NS16550 {
-	u8 rbr;			/* 0 */
-	u8 ier;			/* 1 */
-	u8 fcr;			/* 2 */
-	u8 lcr;			/* 3 */
-	u8 mcr;			/* 4 */
-	u8 lsr;			/* 5 */
-	u8 msr;			/* 6 */
-	u8 scr;			/* 7 */
-} uart_t;
-
-/* I2c */
-typedef struct iic_regs {
-	u16 mdbuf;
-	u16 sbbuf;
-	u8 lmadr;
-	u8 hmadr;
-	u8 cntl;
-	u8 mdcntl;
-	u8 sts;
-	u8 extsts;
-	u8 lsadr;
-	u8 hsadr;
-	u8 clkdiv;
-	u8 intmsk;
-	u8 xfrcnt;
-	u8 xtcntlss;
-	u8 directcntl;
-} iic_t;
-
-/* OPB arbiter */
-typedef struct opb {
-	u8 pr;
-	u8 cr;
-} opb_t;
-
-/* General purpose i/o */
-
-typedef struct gpio_regs {
-	u32 or;
-	u32 tcr;
-	u32 pad[4];
-	u32 odr;
-	u32 ir;
-} gpio_t;
-
-/* Emac */
-typedef struct emac_regs {
-	volatile u32 em0mr0;
-	volatile u32 em0mr1;
-	volatile u32 em0tmr0;
-	volatile u32 em0tmr1;
-	volatile u32 em0rmr;
-	volatile u32 em0isr;
-	volatile u32 em0iser;
-	volatile u32 em0iahr;
-	volatile u32 em0ialr;
-	volatile u32 em0vtpid;
-	volatile u32 em0vtci;
-	volatile u32 em0ptr;
-	volatile u32 em0iaht1;
-	volatile u32 em0iaht2;
-	volatile u32 em0iaht3;
-	volatile u32 em0iaht4;
-	volatile u32 em0gaht1;
-	volatile u32 em0gaht2;
-	volatile u32 em0gaht3;
-	volatile u32 em0gaht4;
-	volatile u32 em0lsal;
-	volatile u32 em0lsah;
-	volatile u32 em0ipgvr;
-	volatile u32 em0stacr;
-	volatile u32 em0trtr;
-	volatile u32 em0rwmr;
-} emac_t;
-
-/* ZMII bridge */
-typedef struct zmii_regs {
-	u32 fer;		/* Function enable reg */
-	u32 ssr;		/* Spedd select reg */
-	u32 smiirs;		/* SMII status reg */
-} zmii_t;
-
-/* Structure of the memory mapped IDE control.
-*/
-typedef struct ide_regs {
-	unsigned int si_stat;	/* IDE status */
-	unsigned int si_intenable;	/* IDE interrupt enable */
-	unsigned int si_control;	/* IDE control */
-	unsigned int pad0[0x3d];
-	unsigned int si_c0rt;	/* Chan 0 Register transfer timing */
-	unsigned int si_c0fpt;	/* Chan 0 Fast PIO transfer timing */
-	unsigned int si_c0timo;	/* Chan 0 timeout */
-	unsigned int pad1[2];
-	unsigned int si_c0d0u;	/* Chan 0 UDMA transfer timing */
-#define si_c0d0m si_c0d0u	/* Chan 0 Multiword DMA timing */
-	unsigned int pad2;
-	unsigned int si_c0d1u;	/* Chan 0 dev 1 UDMA timing */
-#define si_c0d1m si_c0d1u	/* Chan 0 dev 1 Multiword DMA timing */
-	unsigned int si_c0c;	/* Chan 0 Control */
-	unsigned int si_c0s0;	/* Chan 0 Status 0 */
-	unsigned int si_c0ie;	/* Chan 0 Interrupt Enable */
-	unsigned int si_c0s1;	/* Chan 0 Status 0 */
-	unsigned int pad4[4];
-	unsigned int si_c0dcm;	/* Chan 0 DMA Command */
-	unsigned int si_c0tb;	/* Chan 0 PRD Table base address */
-	unsigned int si_c0dct;	/* Chan 0 DMA Count */
-	unsigned int si_c0da;	/* Chan 0 DMA Address */
-	unsigned int si_c0sr;	/* Chan 0 Slew Rate Output Control */
-	unsigned char pad5[0xa2];
-	unsigned short si_c0adc;	/* Chan 0 Alt status/control */
-	unsigned char si_c0d;	/* Chan 0 data */
-	unsigned char si_c0ef;	/* Chan 0 error/features */
-	unsigned char si_c0sct;	/* Chan 0 sector count */
-	unsigned char si_c0sn;	/* Chan 0 sector number */
-	unsigned char si_c0cl;	/* Chan 0 cylinder low */
-	unsigned char si_c0ch;	/* Chan 0 cylinder high */
-	unsigned char si_c0dh;	/* Chan 0 device/head */
-	unsigned char si_c0scm;	/* Chan 0 status/command */
-} ide_t;
-
-#endif				/* __ASSEMBLY__ */
-#endif				/* __ASM_IBM_OCP_H__ */
+#endif				/* __ASM_IBM_OCP_PCI_H__ */
 #endif				/* __KERNEL__ */

include/asm-ppc/ocp.h

+/*
+ * ocp.h
+ *
+ *
+ * 	Current Maintainer
+ *      Armin Kuster akuster@pacbell.net
+ *      Jan, 2002
+ *
+ *
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR   IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT,  INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifdef __KERNEL__
+#ifndef __OCP_H__
+#define __OCP_H__
+
+#include <linux/list.h>
+#include <linux/config.h>
+#include <linux/device.h>
+#include <linux/devfs_fs_kernel.h>
+
+#include <asm/ocp_ids.h>
+#include <asm/mmu.h>		/* For phys_addr_t */
+#undef DEBUG
+/* #define DEBUG*/
+
+#ifdef DEBUG
+#define DBG(x...) printk(x)
+#else
+#define DBG(x...)
+#endif
+
+#define OCP_IRQ_NA	-1	/* used when ocp device does not have an irq */
+#define OCP_IRQ_MUL	-2	/* used for ocp devices with multiple irqs */
+#define OCP_NULL_TYPE	0	/* used to mark end of list */
+#define OCP_DEV_NA	-1
+#define OCP_CPM_NA	0	/* No Clock or Power Management avaliable */
+
+#define OCP_ANY_ID	(~0)
+
+
+extern struct list_head ocp_root_buses;
+extern struct list_head ocp_devices;
+
+struct ocp_device_id {
+	unsigned int vendor, device;		/* Vendor and device ID or PCI_ANY_ID */
+	char name[16];
+	char desc[50];
+	unsigned long driver_data;		/* Data private to the driver */
+};
+
+struct func_info {
+	char name[16];
+	char desc[50];
+};
+
+struct ocp_def {
+	unsigned int vendor;
+	unsigned int device;
+	phys_addr_t paddr;
+	int irq;
+	unsigned long pm;
+};
+
+
+/* Struct for single ocp device managment */
+struct ocp_device {
+	struct list_head global_list;
+	unsigned int	num;		/* instance of device */
+	char		name[80];	/* device name */
+	unsigned int vendor;
+	unsigned int device;
+	phys_addr_t paddr;
+	int irq;
+	unsigned long pm;
+	void *ocpdev;		/* driver data for this device */
+	struct ocp_driver *driver;
+	u32 current_state;	/* Current operating state. In ACPI-speak,
+				   this is D0-D3, D0 being fully functional,
+				   and D3 being off. */
+	struct device dev;
+};
+
+struct ocp_driver {
+	struct list_head node;
+	char *name;
+	const struct ocp_device_id *id_table;	/* NULL if wants all devices */
+	int  (*probe)  (struct ocp_device *dev);	/* New device inserted */
+	void (*remove) (struct ocp_device *dev);	/* Device removed (NULL if not a hot-plug capable driver) */
+	int  (*save_state) (struct ocp_device *dev, u32 state);    /* Save Device Context */
+	int  (*suspend) (struct ocp_device *dev, u32 state);	/* Device suspended */
+	int  (*resume) (struct ocp_device *dev);	                /* Device woken up */
+	int  (*enable_wake) (struct ocp_device *dev, u32 state, int enable);   /* Enable wake event */
+	struct device_driver driver;
+};
+
+#define	to_ocp_dev(n) container_of(n, struct ocp_device, dev)
+#define	to_ocp_driver(n) container_of(n, struct ocp_driver, driver)
+
+extern int ocp_register_driver(struct ocp_driver *drv);
+extern void ocp_unregister_driver(struct ocp_driver *drv);
+
+#define ocp_dev_g(n) list_entry(n, struct ocp_device, global_list)
+
+#define ocp_for_each_dev(dev) \
+	for(dev = ocp_dev_g(ocp_devices.next); dev != ocp_dev_g(&ocp_devices); dev = ocp_dev_g(dev->global_list.next))
+
+/* Similar to the helpers above, these manipulate per-ocp_dev
+ * driver-specific data.  Currently stored as ocp_dev::ocpdev,
+ * a void pointer, but it is not present on older kernels.
+ */
+static inline void *
+ocp_get_drvdata(struct ocp_device *pdev)
+{
+	return pdev->ocpdev;
+}
+
+static inline void
+ocp_set_drvdata(struct ocp_device *pdev, void *data)
+{
+	pdev->ocpdev = data;
+}
+
+/*
+ * a helper function which helps ensure correct pci_driver
+ * setup and cleanup for commonly-encountered hotplug/modular cases
+ *
+ * This MUST stay in a header, as it checks for -DMODULE
+ */
+static inline int ocp_module_init(struct ocp_driver *drv)
+{
+	int rc = ocp_register_driver(drv);
+
+	if (rc > 0)
+		return 0;
+
+	/* iff CONFIG_HOTPLUG and built into kernel, we should
+	 * leave the driver around for future hotplug events.
+	 * For the module case, a hotplug daemon of some sort
+	 * should load a module in response to an insert event. */
+#if defined(CONFIG_HOTPLUG) && !defined(MODULE)
+	if (rc == 0)
+		return 0;
+#else
+	if (rc == 0)
+		rc = -ENODEV;		
+#endif
+
+	/* if we get here, we need to clean up pci driver instance
+	 * and return some sort of error */
+	ocp_unregister_driver (drv);
+	
+	return rc;
+}
+
+#if defined (CONFIG_PM)
+/*
+ * This is right for the IBM 405 and 440 but will need to be
+ * generalized if the OCP stuff gets used on other processors.
+ */
+static inline void
+ocp_force_power_off(struct ocp_device *odev)
+{
+	mtdcr(DCRN_CPMFR, mfdcr(DCRN_CPMFR) | odev->pm);
+}
+
+static inline void
+ocp_force_power_on(struct ocp_device *odev)
+{
+	mtdcr(DCRN_CPMFR, mfdcr(DCRN_CPMFR) & ~odev->pm);
+}
+#else
+#define ocp_force_power_off(x)	(void)(x)
+#define ocp_force_power_on(x)	(void)(x)
+#endif
+
+extern void ocp_init(void);
+extern struct bus_type ocp_bus_type;
+extern struct ocp_device *ocp_get_dev(unsigned int device, int index);
+extern unsigned int ocp_get_num(unsigned int device);
+
+extern int ocp_generic_suspend(struct ocp_device *pdev, u32 state);
+extern int ocp_generic_resume(struct ocp_device *pdev);
+
+#endif				/* __OCP_H__ */
+#endif				/* __KERNEL__ */

include/asm-ppc/ocp_ids.h

+/*
+ * FILE NAME: ocp_ids.h
+ *
+ * BRIEF MODULE DESCRIPTION: 
+ * OCP device ids based on the ideas from PCI
+ *
+ * Maintained by: Armin <akuster@mvista.com>
+ *
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ *  Version 1.0 08/22/02 -Armin
+ *  	initial release
+ */
+
+/*
+ * Vender  device
+ * [xxxx]  [xxxx]
+ *
+ *  Keep in order, please
+ */
+
+/* Vendor IDs 0x0001 - 0xFFFF copied from pci_ids.h */
+
+#define	OCP_VENDOR_INVALID	0x0000
+#define	OCP_VENDOR_ARM		0x0004
+#define OCP_VENDOR_IBM		0x1014
+#define OCP_VENDOR_MOTOROLA	0x1057
+#define	OCP_VENDOR_XILINX	0x10ee
+#define	OCP_VENDOR_UNKNOWN	0xFFFF
+
+/* device identification */
+
+/* define type */
+#define OCP_FUNC_INVALID	0x0000
+
+/* system 0x0001 - 0x001F */
+#define	OCP_FUNC_UIC		0x0001
+
+/* Timers 0x0020 - 0x002F */
+#define OCP_FUNC_GPT		0x0020 	/* General purpose timers */
+#define OCP_FUNC_RTC		0x0021
+
+/* Serial 0x0030 - 0x006F*/
+#define OCP_FUNC_16550		0x0031 
+#define OCP_FUNC_SSP		0x0032 /* sync serial port */
+#define OCP_FUNC_SCP		0x0033 	/* serial controller port */
+#define OCP_FUNC_SCC		0x0034 	/* serial contoller */
+#define OCP_FUNC_SCI		0x0035 	/* Smart card */
+#define OCP_FUNC_IIC		0x0040 
+#define OCP_FUNC_USB		0x0050 
+#define OCP_FUNC_IR		0x0060		
+
+/* Memory devices 0x0090 - 0x009F */
+#define	OCP_FUNC_SDRAM		0x0091
+#define OCP_FUNC_DMA		0x0092
+
+/* Display 0x00A0 - 0x00AF */
+#define OCP_FUNC_VIDEO		0x00A0 
+#define OCP_FUNC_LED		0x00A1
+#define	OCP_FUNC_LCD		0x00A2
+
+/* Sound 0x00B0 - 0x00BF */
+#define OCP_FUNC_AUDIO		0x00B0 
+
+/* Mass Storage 0x00C0 - 0xxCF */
+#define OCP_FUNC_IDE		0x00C0 
+
+/* Misc 0x00D0 - 0x00DF*/
+#define OCP_FUNC_GPIO		0x00D0 
+#define OCP_FUNC_ZMII		0x00D1
+
+/* Network 0x0200 - 0x02FF */
+#define OCP_FUNC_EMAC		0x0200 
+
+/* Bridge devices 0xE00 - 0xEFF */
+#define OCP_FUNC_HOST		0x0E00 
+#define OCP_FUNC_DCR		0x0E01 
+#define OCP_FUNC_OPB		0x0E02
+#define OCP_FUNC_PHY		0x0E03
+#define OCP_FUNC_EXT		0x0E04
+#define	OCP_FUNC_PCI		0x0E05
+#define	OCP_FUNC_PLB		0x0E06
+
+#define OCP_FUNC_UNKNOWN	0xFFFF

include/asm-ppc/ppc4xx_pic.h

@@ -17,11 +17,12 @@
 /* External Global Variables */
 
 extern struct hw_interrupt_type *ppc4xx_pic;
-
+extern unsigned int ibm4xxPIC_NumInitSenses;
+extern unsigned char *ibm4xxPIC_InitSenses;
 
 /* Function Prototypes */
 
-extern void	 ppc4xx_pic_init(void);
-extern int	 ppc4xx_pic_get_irq(struct pt_regs *regs);
+extern void ppc4xx_pic_init(void);
+extern int ppc4xx_pic_get_irq(struct pt_regs *regs);
 
-#endif /* __PPC4XX_PIC_H__ */
+#endif				/* __PPC4XX_PIC_H__ */