Commit 80f9bfe4 authored by chen gong's avatar chen gong Committed by Alex Deucher

drm/amd/powerplay: Add mode2 mode for GPU RESET in SMU

Renoir need to use mode2 mode to implement GPU RESET
Signed-off-by: default avatarchen gong <curry.gong@amd.com>
Reviewed-by: default avatarAaron Liu <aaron.liu@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 40463bdc
...@@ -321,6 +321,13 @@ struct mclock_latency_table { ...@@ -321,6 +321,13 @@ struct mclock_latency_table {
struct mclk_latency_entries entries[MAX_REGULAR_DPM_NUM]; struct mclk_latency_entries entries[MAX_REGULAR_DPM_NUM];
}; };
enum smu_reset_mode
{
SMU_RESET_MODE_0,
SMU_RESET_MODE_1,
SMU_RESET_MODE_2,
};
enum smu_baco_state enum smu_baco_state
{ {
SMU_BACO_STATE_ENTER = 0, SMU_BACO_STATE_ENTER = 0,
...@@ -537,6 +544,7 @@ struct smu_funcs ...@@ -537,6 +544,7 @@ struct smu_funcs
enum smu_baco_state (*baco_get_state)(struct smu_context *smu); enum smu_baco_state (*baco_get_state)(struct smu_context *smu);
int (*baco_set_state)(struct smu_context *smu, enum smu_baco_state state); int (*baco_set_state)(struct smu_context *smu, enum smu_baco_state state);
int (*baco_reset)(struct smu_context *smu); int (*baco_reset)(struct smu_context *smu);
int (*mode2_reset)(struct smu_context *smu);
int (*get_dpm_ultimate_freq)(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t *min, uint32_t *max); int (*get_dpm_ultimate_freq)(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t *min, uint32_t *max);
}; };
...@@ -760,6 +768,8 @@ struct smu_funcs ...@@ -760,6 +768,8 @@ struct smu_funcs
((smu)->funcs->baco_get_state? (smu)->funcs->baco_get_state((smu), (state)) : 0) ((smu)->funcs->baco_get_state? (smu)->funcs->baco_get_state((smu), (state)) : 0)
#define smu_baco_reset(smu) \ #define smu_baco_reset(smu) \
((smu)->funcs->baco_reset? (smu)->funcs->baco_reset((smu)) : 0) ((smu)->funcs->baco_reset? (smu)->funcs->baco_reset((smu)) : 0)
#define smu_mode2_reset(smu) \
((smu)->funcs->mode2_reset? (smu)->funcs->mode2_reset((smu)) : 0)
#define smu_asic_set_performance_level(smu, level) \ #define smu_asic_set_performance_level(smu, level) \
((smu)->ppt_funcs->set_performance_level? (smu)->ppt_funcs->set_performance_level((smu), (level)) : -EINVAL); ((smu)->ppt_funcs->set_performance_level? (smu)->ppt_funcs->set_performance_level((smu), (level)) : -EINVAL);
#define smu_dump_pptable(smu) \ #define smu_dump_pptable(smu) \
......
...@@ -380,6 +380,9 @@ static int smu_v12_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk ...@@ -380,6 +380,9 @@ static int smu_v12_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk
return ret; return ret;
} }
static int smu_v12_0_mode2_reset(struct smu_context *smu){
return smu_v12_0_send_msg_with_param(smu, SMU_MSG_GfxDeviceDriverReset, SMU_RESET_MODE_2);
}
static const struct smu_funcs smu_v12_0_funcs = { static const struct smu_funcs smu_v12_0_funcs = {
.check_fw_status = smu_v12_0_check_fw_status, .check_fw_status = smu_v12_0_check_fw_status,
.check_fw_version = smu_v12_0_check_fw_version, .check_fw_version = smu_v12_0_check_fw_version,
...@@ -394,6 +397,7 @@ static const struct smu_funcs smu_v12_0_funcs = { ...@@ -394,6 +397,7 @@ static const struct smu_funcs smu_v12_0_funcs = {
.fini_smc_tables = smu_v12_0_fini_smc_tables, .fini_smc_tables = smu_v12_0_fini_smc_tables,
.populate_smc_tables = smu_v12_0_populate_smc_tables, .populate_smc_tables = smu_v12_0_populate_smc_tables,
.get_dpm_ultimate_freq = smu_v12_0_get_dpm_ultimate_freq, .get_dpm_ultimate_freq = smu_v12_0_get_dpm_ultimate_freq,
.mode2_reset = smu_v12_0_mode2_reset,
}; };
void smu_v12_0_set_smu_funcs(struct smu_context *smu) void smu_v12_0_set_smu_funcs(struct smu_context *smu)
......
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