Commit 82b98fb8 authored by Tudor Ambarus's avatar Tudor Ambarus Committed by Mark Brown

spi: s3c64xx: allow FIFO depth to be determined from the compatible

There are SoCs that use the same FIFO depth for all the instances of the
SPI IP. See the fifo_lvl_mask defined for gs101 for example:
    .fifo_lvl_mask  = { 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f,
                        0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f},

Instead of specifying the FIFO depth with the same value for all 16
nodes in this case, allow such SoCs to infer the FIFO depth from the
compatible. There are other SoCs than can benefit of this, see:
{gs101, fsd, exynos850, s3c641, s3c2443}_spi_port_config.

The FIFO depth inferred from the compatible has a higher precedence than
the one that might be specified via device tree, the driver shall know
better.
Signed-off-by: default avatarTudor Ambarus <tudor.ambarus@linaro.org>
Link: https://msgid.link/r/20240216070555.2483977-7-tudor.ambarus@linaro.orgSigned-off-by: default avatarMark Brown <broonie@kernel.org>
parent 414d7b8c
...@@ -137,6 +137,7 @@ struct s3c64xx_spi_dma_data { ...@@ -137,6 +137,7 @@ struct s3c64xx_spi_dma_data {
* struct s3c64xx_spi_port_config - SPI Controller hardware info * struct s3c64xx_spi_port_config - SPI Controller hardware info
* @fifo_lvl_mask: Bit-mask for {TX|RX}_FIFO_LVL bits in SPI_STATUS register. * @fifo_lvl_mask: Bit-mask for {TX|RX}_FIFO_LVL bits in SPI_STATUS register.
* @rx_lvl_offset: Bit offset of RX_FIFO_LVL bits in SPI_STATUS regiter. * @rx_lvl_offset: Bit offset of RX_FIFO_LVL bits in SPI_STATUS regiter.
* @fifo_depth: depth of the FIFO.
* @rx_fifomask: SPI_STATUS.RX_FIFO_LVL mask. Shifted mask defining the field's * @rx_fifomask: SPI_STATUS.RX_FIFO_LVL mask. Shifted mask defining the field's
* length and position. * length and position.
* @tx_fifomask: SPI_STATUS.TX_FIFO_LVL mask. Shifted mask defining the field's * @tx_fifomask: SPI_STATUS.TX_FIFO_LVL mask. Shifted mask defining the field's
...@@ -159,6 +160,7 @@ struct s3c64xx_spi_dma_data { ...@@ -159,6 +160,7 @@ struct s3c64xx_spi_dma_data {
struct s3c64xx_spi_port_config { struct s3c64xx_spi_port_config {
int fifo_lvl_mask[MAX_SPI_PORTS]; int fifo_lvl_mask[MAX_SPI_PORTS];
int rx_lvl_offset; int rx_lvl_offset;
unsigned int fifo_depth;
u32 rx_fifomask; u32 rx_fifomask;
u32 tx_fifomask; u32 tx_fifomask;
int tx_st_done; int tx_st_done;
...@@ -1263,8 +1265,10 @@ static int s3c64xx_spi_probe(struct platform_device *pdev) ...@@ -1263,8 +1265,10 @@ static int s3c64xx_spi_probe(struct platform_device *pdev)
sdd->port_id = pdev->id; sdd->port_id = pdev->id;
} }
if (of_property_read_u32(pdev->dev.of_node, "fifo-depth", if (sdd->port_conf->fifo_depth)
&sdd->fifo_depth)) sdd->fifo_depth = sdd->port_conf->fifo_depth;
else if (of_property_read_u32(pdev->dev.of_node, "fifo-depth",
&sdd->fifo_depth))
sdd->fifo_depth = FIFO_DEPTH(sdd); sdd->fifo_depth = FIFO_DEPTH(sdd);
s3c64xx_spi_set_fifomask(sdd); s3c64xx_spi_set_fifomask(sdd);
......
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment