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Commit 82d05736 authored by Alex Deucher's avatar Alex Deucher
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drm/amdgpu/amdgpu_psp: convert to IP version checking 

Use IP versions rather than asic_type to differentiate
IP version specific features.
Acked-by: default avatarChristian König <christian.koenig@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 9d0cb2c3
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Inline Side-by-side
Showing with 58 additions and 43 deletions
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
View file @ 82d05736
...@@ -71,17 +71,25 @@ static void psp_check_pmfw_centralized_cstate_management(struct psp_context *psp ...@@ -71,17 +71,25 @@ static void psp_check_pmfw_centralized_cstate_management(struct psp_context *psp
{ {
struct amdgpu_device *adev = psp->adev; struct amdgpu_device *adev = psp->adev;
psp->pmfw_centralized_cstate_management = false; if (amdgpu_sriov_vf(adev)) {
psp->pmfw_centralized_cstate_management = false;
if (amdgpu_sriov_vf(adev))
return;
if (adev->flags & AMD_IS_APU)
return; return;
}
if ((adev->asic_type >= CHIP_ARCTURUS) || switch (adev->ip_versions[MP0_HWIP]) {
(adev->asic_type >= CHIP_NAVI12)) case IP_VERSION(11, 0, 4):
case IP_VERSION(11, 0, 7):
case IP_VERSION(11, 0, 9):
case IP_VERSION(11, 0, 11):
case IP_VERSION(11, 0, 12):
case IP_VERSION(11, 0, 13):
case IP_VERSION(13, 0, 2):
psp->pmfw_centralized_cstate_management = true; psp->pmfw_centralized_cstate_management = true;
break;
default:
psp->pmfw_centralized_cstate_management = false;
break;
}
} }
static int psp_early_init(void *handle) static int psp_early_init(void *handle)
...@@ -89,43 +97,45 @@ static int psp_early_init(void *handle) ...@@ -89,43 +97,45 @@ static int psp_early_init(void *handle)
struct amdgpu_device *adev = (struct amdgpu_device *)handle; struct amdgpu_device *adev = (struct amdgpu_device *)handle;
struct psp_context *psp = &adev->psp; struct psp_context *psp = &adev->psp;
switch (adev->asic_type) { switch (adev->ip_versions[MP0_HWIP]) {
case CHIP_VEGA10: case IP_VERSION(9, 0, 0):
case CHIP_VEGA12:
psp_v3_1_set_psp_funcs(psp); psp_v3_1_set_psp_funcs(psp);
psp->autoload_supported = false; psp->autoload_supported = false;
break; break;
case CHIP_RAVEN: case IP_VERSION(10, 0, 0):
case IP_VERSION(10, 0, 1):
psp_v10_0_set_psp_funcs(psp); psp_v10_0_set_psp_funcs(psp);
psp->autoload_supported = false; psp->autoload_supported = false;
break; break;
case CHIP_VEGA20: case IP_VERSION(11, 0, 2):
case CHIP_ARCTURUS: case IP_VERSION(11, 0, 4):
psp_v11_0_set_psp_funcs(psp); psp_v11_0_set_psp_funcs(psp);
psp->autoload_supported = false; psp->autoload_supported = false;
break; break;
case CHIP_NAVI10: case IP_VERSION(11, 0, 0):
case CHIP_NAVI14: case IP_VERSION(11, 0, 5):
case CHIP_NAVI12: case IP_VERSION(11, 0, 9):
case CHIP_SIENNA_CICHLID: case IP_VERSION(11, 0, 7):
case CHIP_NAVY_FLOUNDER: case IP_VERSION(11, 0, 11):
case CHIP_VANGOGH: case IP_VERSION(11, 5, 0):
case CHIP_DIMGREY_CAVEFISH: case IP_VERSION(11, 0, 12):
case CHIP_BEIGE_GOBY: case IP_VERSION(11, 0, 13):
psp_v11_0_set_psp_funcs(psp); psp_v11_0_set_psp_funcs(psp);
psp->autoload_supported = true; psp->autoload_supported = true;
break; break;
case CHIP_RENOIR: case IP_VERSION(11, 0, 3):
case IP_VERSION(12, 0, 1):
psp_v12_0_set_psp_funcs(psp); psp_v12_0_set_psp_funcs(psp);
break; break;
case CHIP_ALDEBARAN: case IP_VERSION(13, 0, 2):
psp_v13_0_set_psp_funcs(psp); psp_v13_0_set_psp_funcs(psp);
break; break;
case CHIP_YELLOW_CARP: case IP_VERSION(13, 0, 1):
case IP_VERSION(13, 0, 3):
psp_v13_0_set_psp_funcs(psp); psp_v13_0_set_psp_funcs(psp);
psp->autoload_supported = true; psp->autoload_supported = true;
break; break;
case CHIP_CYAN_SKILLFISH: case IP_VERSION(11, 0, 8):
if (adev->apu_flags & AMD_APU_IS_CYAN_SKILLFISH2) { if (adev->apu_flags & AMD_APU_IS_CYAN_SKILLFISH2) {
psp_v11_0_8_set_psp_funcs(psp); psp_v11_0_8_set_psp_funcs(psp);
psp->autoload_supported = false; psp->autoload_supported = false;
...@@ -268,7 +278,8 @@ static int psp_sw_init(void *handle) ...@@ -268,7 +278,8 @@ static int psp_sw_init(void *handle)
DRM_ERROR("Failed to load psp firmware!\n"); DRM_ERROR("Failed to load psp firmware!\n");
return ret; return ret;
} }
} else if (amdgpu_sriov_vf(adev) && adev->asic_type == CHIP_ALDEBARAN) { } else if (amdgpu_sriov_vf(adev) &&
adev->ip_versions[MP0_HWIP] == IP_VERSION(13, 0, 2)) {
ret = psp_init_ta_microcode(psp, "aldebaran"); ret = psp_init_ta_microcode(psp, "aldebaran");
if (ret) { if (ret) {
DRM_ERROR("Failed to initialize ta microcode!\n"); DRM_ERROR("Failed to initialize ta microcode!\n");
...@@ -311,7 +322,8 @@ static int psp_sw_init(void *handle) ...@@ -311,7 +322,8 @@ static int psp_sw_init(void *handle)
} }
} }
if (adev->asic_type == CHIP_NAVI10 || adev->asic_type == CHIP_SIENNA_CICHLID) { if (adev->ip_versions[MP0_HWIP] == IP_VERSION(11, 0, 0) ||
adev->ip_versions[MP0_HWIP] == IP_VERSION(11, 0, 7)) {
ret= psp_sysfs_init(adev); ret= psp_sysfs_init(adev);
if (ret) { if (ret) {
return ret; return ret;
...@@ -341,8 +353,8 @@ static int psp_sw_fini(void *handle) ...@@ -341,8 +353,8 @@ static int psp_sw_fini(void *handle)
psp->ta_fw = NULL; psp->ta_fw = NULL;
} }
if (adev->asic_type == CHIP_NAVI10 || if (adev->ip_versions[MP0_HWIP] == IP_VERSION(11, 0, 0) ||
adev->asic_type == CHIP_SIENNA_CICHLID) adev->ip_versions[MP0_HWIP] == IP_VERSION(11, 0, 7))
psp_sysfs_fini(adev); psp_sysfs_fini(adev);
kfree(cmd); kfree(cmd);
...@@ -601,10 +613,10 @@ static int psp_tmr_init(struct psp_context *psp) ...@@ -601,10 +613,10 @@ static int psp_tmr_init(struct psp_context *psp)
static bool psp_skip_tmr(struct psp_context *psp) static bool psp_skip_tmr(struct psp_context *psp)
{ {
switch (psp->adev->asic_type) { switch (psp->adev->ip_versions[MP0_HWIP]) {
case CHIP_NAVI12: case IP_VERSION(11, 0, 9):
case CHIP_SIENNA_CICHLID: case IP_VERSION(11, 0, 7):
case CHIP_ALDEBARAN: case IP_VERSION(13, 0, 2):
return true; return true;
default: default:
return false; return false;
...@@ -998,8 +1010,9 @@ int psp_xgmi_terminate(struct psp_context *psp) ...@@ -998,8 +1010,9 @@ int psp_xgmi_terminate(struct psp_context *psp)
struct amdgpu_device *adev = psp->adev; struct amdgpu_device *adev = psp->adev;
/* XGMI TA unload currently is not supported on Arcturus/Aldebaran A+A */ /* XGMI TA unload currently is not supported on Arcturus/Aldebaran A+A */
if (adev->asic_type == CHIP_ARCTURUS || if (adev->ip_versions[MP0_HWIP] == IP_VERSION(11, 0, 4) ||
(adev->asic_type == CHIP_ALDEBARAN && adev->gmc.xgmi.connected_to_cpu)) (adev->ip_versions[MP0_HWIP] == IP_VERSION(13, 0, 2) &&
adev->gmc.xgmi.connected_to_cpu))
return 0; return 0;
if (!psp->xgmi_context.context.initialized) if (!psp->xgmi_context.context.initialized)
...@@ -1100,8 +1113,8 @@ int psp_xgmi_get_node_id(struct psp_context *psp, uint64_t *node_id) ...@@ -1100,8 +1113,8 @@ int psp_xgmi_get_node_id(struct psp_context *psp, uint64_t *node_id)
static bool psp_xgmi_peer_link_info_supported(struct psp_context *psp) static bool psp_xgmi_peer_link_info_supported(struct psp_context *psp)
{ {
return psp->adev->asic_type == CHIP_ALDEBARAN && return psp->adev->ip_versions[MP0_HWIP] == IP_VERSION(13, 0, 2) &&
psp->xgmi_context.context.bin_desc.feature_version >= 0x2000000b; psp->xgmi_context.context.bin_desc.feature_version >= 0x2000000b;
} }
/* /*
...@@ -2219,8 +2232,8 @@ static int psp_load_smu_fw(struct psp_context *psp) ...@@ -2219,8 +2232,8 @@ static int psp_load_smu_fw(struct psp_context *psp)
if ((amdgpu_in_reset(adev) && if ((amdgpu_in_reset(adev) &&
ras && adev->ras_enabled && ras && adev->ras_enabled &&
(adev->asic_type == CHIP_ARCTURUS || (adev->ip_versions[MP0_HWIP] == IP_VERSION(11, 0, 4) ||
adev->asic_type == CHIP_VEGA20))) { adev->ip_versions[MP0_HWIP] == IP_VERSION(11, 0, 2)))) {
ret = amdgpu_dpm_set_mp1_state(adev, PP_MP1_STATE_UNLOAD); ret = amdgpu_dpm_set_mp1_state(adev, PP_MP1_STATE_UNLOAD);
if (ret) { if (ret) {
DRM_WARN("Failed to set MP1 state prepare for reload\n"); DRM_WARN("Failed to set MP1 state prepare for reload\n");
...@@ -2317,8 +2330,9 @@ static int psp_load_non_psp_fw(struct psp_context *psp) ...@@ -2317,8 +2330,9 @@ static int psp_load_non_psp_fw(struct psp_context *psp)
continue; continue;
if (psp->autoload_supported && if (psp->autoload_supported &&
(adev->asic_type >= CHIP_SIENNA_CICHLID && (adev->ip_versions[MP0_HWIP] == IP_VERSION(11, 0, 7) ||
adev->asic_type <= CHIP_DIMGREY_CAVEFISH) && adev->ip_versions[MP0_HWIP] == IP_VERSION(11, 0, 11) ||
adev->ip_versions[MP0_HWIP] == IP_VERSION(11, 0, 12)) &&
(ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1 || (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1 ||
ucode->ucode_id == AMDGPU_UCODE_ID_SDMA2 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA2 ||
ucode->ucode_id == AMDGPU_UCODE_ID_SDMA3)) ucode->ucode_id == AMDGPU_UCODE_ID_SDMA3))
...@@ -2905,7 +2919,8 @@ static int psp_init_sos_base_fw(struct amdgpu_device *adev) ...@@ -2905,7 +2919,8 @@ static int psp_init_sos_base_fw(struct amdgpu_device *adev)
ucode_array_start_addr = (uint8_t *)sos_hdr + ucode_array_start_addr = (uint8_t *)sos_hdr +
le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes); le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes);
if (adev->gmc.xgmi.connected_to_cpu || (adev->asic_type != CHIP_ALDEBARAN)) { if (adev->gmc.xgmi.connected_to_cpu ||
(adev->ip_versions[MP0_HWIP] != IP_VERSION(13, 0, 2))) {
adev->psp.sos.fw_version = le32_to_cpu(sos_hdr->header.ucode_version); adev->psp.sos.fw_version = le32_to_cpu(sos_hdr->header.ucode_version);
adev->psp.sos.feature_version = le32_to_cpu(sos_hdr->sos.fw_version); adev->psp.sos.feature_version = le32_to_cpu(sos_hdr->sos.fw_version);
......
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