Commit 8395d932 authored by Linus Torvalds's avatar Linus Torvalds

Merge tag 'devicetree-for-6.3' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux

Pull devicetree updates from Rob Herring:
 "DT core:

   - Add node lifecycle unit tests

   - Add of_property_present() helper aligned with fwnode API

   - Print more information on reserved regions on boot

   - Update dtc to upstream v1.6.1-66-gabbd523bae6e

   - Use strscpy() to instead of strncpy() in DT core

   - Add option for schema validation on %.dtb targets

  Bindings:

   - Add/fix support for listing multiple patterns in DT_SCHEMA_FILES

   - Rework external memory controller/bus bindings to properly support
     controller specific child node properties

   - Convert loongson,ls1x-intc, fcs,fusb302, sil,sii8620, Rockchip
     RK3399 PCIe, Synquacer I2C, and Synquacer EXIU bindings to DT
     schema format

   - Add RiscV SBI PMU event mapping binding

   - Add missing contraints on Arm SCMI child node allowed properties

   - Add a bunch of missing Socionext UniPhier glue block bindings and
     example fixes

   - Various fixes for duplicate or conflicting type definitions on DT
     properties"

* tag 'devicetree-for-6.3' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux: (66 commits)
  dt-bindings: regulator: Add mps,mpq7932 power-management IC
  of: dynamic: Fix spelling mistake "kojbect" -> "kobject"
  dt-bindings: drop Sagar Kadam from SiFive binding maintainership
  dt-bindings: sram: qcom,imem: document sm8450
  dt-bindings: interrupt-controller: convert loongson,ls1x-intc.txt to json-schema
  dt-bindings: arm: Add Cortex-A715 and X3
  of: dynamic: add lifecycle docbook info to node creation functions
  of: add consistency check to of_node_release()
  of: do not use "%pOF" printk format on node with refcount of zero
  of: unittest: add node lifecycle tests
  of: update kconfig unittest help
  of: add processing of EXPECT_NOT to of_unittest_expect
  of: prepare to add processing of EXPECT_NOT to of_unittest_expect
  of: Use preferred of_property_read_* functions
  of: Use of_property_present() helper
  of: Add of_property_present() helper
  of: reserved_mem: Use proper binary prefix
  dt-bindings: Fix multi pattern support in DT_SCHEMA_FILES
  of: reserved-mem: print out reserved-mem details during boot
  dt-bindings: serial: restrict possible child node names
  ...
parents a93e884e 1ba7dfb9
......@@ -28,7 +28,7 @@ $(obj)/%.example.dts: $(src)/%.yaml check_dtschema_version FORCE
find_all_cmd = find $(srctree)/$(src) \( -name '*.yaml' ! \
-name 'processed-schema*' \)
find_cmd = $(find_all_cmd) | grep -F "$(DT_SCHEMA_FILES)"
find_cmd = $(find_all_cmd) | grep -F -e "$(subst :," -e ",$(DT_SCHEMA_FILES))"
CHK_DT_DOCS := $(shell $(find_cmd))
quiet_cmd_yamllint = LINT $(src)
......
......@@ -141,6 +141,7 @@ properties:
- arm,cortex-a78ae
- arm,cortex-a510
- arm,cortex-a710
- arm,cortex-a715
- arm,cortex-m0
- arm,cortex-m0+
- arm,cortex-m1
......@@ -151,6 +152,7 @@ properties:
- arm,cortex-r7
- arm,cortex-x1
- arm,cortex-x2
- arm,cortex-x3
- arm,neoverse-e1
- arm,neoverse-n1
- arm,neoverse-n2
......
......@@ -35,6 +35,7 @@ required:
allOf:
- $ref: pata-common.yaml#
- $ref: /schemas/memory-controllers/intel,ixp4xx-expansion-peripheral-props.yaml#
unevaluatedProperties: false
......
......@@ -30,12 +30,12 @@ properties:
- qcom,sm8250-videocc
clocks:
items:
- description: Board XO source
minItems: 1
maxItems: 3
clock-names:
items:
- const: bi_tcxo
minItems: 1
maxItems: 3
'#clock-cells':
const: 1
......@@ -68,6 +68,57 @@ required:
- '#reset-cells'
- '#power-domain-cells'
allOf:
- if:
properties:
compatible:
enum:
- qcom,sc7180-videocc
- qcom,sdm845-videocc
- qcom,sm8150-videocc
then:
properties:
clocks:
items:
- description: Board XO source
clock-names:
items:
- const: bi_tcxo
- if:
properties:
compatible:
enum:
- qcom,sc7280-videocc
then:
properties:
clocks:
items:
- description: Board XO source
- description: Board active XO source
clock-names:
items:
- const: bi_tcxo
- const: bi_tcxo_ao
- if:
properties:
compatible:
enum:
- qcom,sm8250-videocc
then:
properties:
clocks:
items:
- description: AHB
- description: Board XO source
- description: Board active XO source
clock-names:
items:
- const: iface
- const: bi_tcxo
- const: bi_tcxo_ao
additionalProperties: false
examples:
......
......@@ -8,7 +8,6 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: SiFive FU540 Power Reset Clock Interrupt Controller (PRCI)
maintainers:
- Sagar Kadam <sagar.kadam@sifive.com>
- Paul Walmsley <paul.walmsley@sifive.com>
description:
......
......@@ -61,40 +61,7 @@ required:
examples:
- |
sysctrl@61840000 {
compatible = "socionext,uniphier-sysctrl", "simple-mfd", "syscon";
reg = <0x61840000 0x4000>;
clock {
compatible = "socionext,uniphier-ld11-clock";
#clock-cells = <1>;
};
// other nodes ...
};
- |
mioctrl@59810000 {
compatible = "socionext,uniphier-mioctrl", "simple-mfd", "syscon";
reg = <0x59810000 0x800>;
clock {
compatible = "socionext,uniphier-ld11-mio-clock";
#clock-cells = <1>;
};
// other nodes ...
};
- |
perictrl@59820000 {
compatible = "socionext,uniphier-perictrl", "simple-mfd", "syscon";
reg = <0x59820000 0x200>;
clock {
compatible = "socionext,uniphier-ld11-peri-clock";
#clock-cells = <1>;
};
// other nodes ...
clock-controller {
compatible = "socionext,uniphier-ld11-clock";
#clock-cells = <1>;
};
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/bridge/sil,sii8620.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Silicon Image SiI8620 HDMI/MHL bridge
maintainers:
- Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
properties:
compatible:
const: sil,sii8620
reg:
maxItems: 1
clocks:
maxItems: 1
clock-names:
items:
- const: xtal
cvcc10-supply:
description: Digital Core Supply Voltage (1.0V)
interrupts:
maxItems: 1
iovcc18-supply:
description: I/O Supply Voltage (1.8V)
reset-gpios:
maxItems: 1
ports:
$ref: /schemas/graph.yaml#/properties/ports
unevaluatedProperties: false
properties:
port@0:
$ref: /schemas/graph.yaml#/properties/port
description:
Video port for HDMI (encoder) input
port@1:
$ref: /schemas/graph.yaml#/properties/port
description:
MHL to connector port
required:
- port@0
- port@1
required:
- compatible
- reg
- clocks
- cvcc10-supply
- interrupts
- iovcc18-supply
- reset-gpios
- ports
additionalProperties: false
examples:
- |
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
i2c {
#address-cells = <1>;
#size-cells = <0>;
bridge@39 {
reg = <0x39>;
compatible = "sil,sii8620";
cvcc10-supply = <&ldo36_reg>;
iovcc18-supply = <&ldo34_reg>;
interrupt-parent = <&gpf0>;
interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
reset-gpios = <&gpv7 0 GPIO_ACTIVE_LOW>;
clocks = <&pmu_system_controller 0>;
clock-names = "xtal";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
mhl_to_hdmi: endpoint {
remote-endpoint = <&hdmi_to_mhl>;
};
};
port@1 {
reg = <1>;
mhl_to_musb_con: endpoint {
remote-endpoint = <&musb_con_to_mhl>;
};
};
};
};
};
Silicon Image SiI8620 HDMI/MHL bridge bindings
Required properties:
- compatible: "sil,sii8620"
- reg: i2c address of the bridge
- cvcc10-supply: Digital Core Supply Voltage (1.0V)
- iovcc18-supply: I/O Supply Voltage (1.8V)
- interrupts: interrupt specifier of INT pin
- reset-gpios: gpio specifier of RESET pin
- clocks, clock-names: specification and name of "xtal" clock
- video interfaces: Device node can contain video interface port
node for HDMI encoder according to [1].
[1]: Documentation/devicetree/bindings/media/video-interfaces.txt
Example:
sii8620@39 {
reg = <0x39>;
compatible = "sil,sii8620";
cvcc10-supply = <&ldo36_reg>;
iovcc18-supply = <&ldo34_reg>;
interrupt-parent = <&gpf0>;
interrupts = <2 0>;
reset-gpio = <&gpv7 0 0>;
clocks = <&pmu_system_controller 0>;
clock-names = "xtal";
port {
mhl_to_hdmi: endpoint {
remote-endpoint = <&hdmi_to_mhl>;
};
};
};
......@@ -71,8 +71,7 @@ properties:
items:
- const: dp
operating-points-v2:
maxItems: 1
operating-points-v2: true
opp-table: true
......
......@@ -89,7 +89,7 @@ properties:
help bring the GPU out of secure mode.
properties:
memory-region:
$ref: /schemas/types.yaml#/definitions/phandle
maxItems: 1
firmware-name:
description: |
......
......@@ -59,8 +59,7 @@ properties:
iommus:
maxItems: 1
operating-points-v2:
$ref: "/schemas/types.yaml#/definitions/phandle"
operating-points-v2: true
power-domains:
items:
......
......@@ -47,8 +47,7 @@ properties:
items:
- const: dsi
operating-points-v2:
$ref: "/schemas/types.yaml#/definitions/phandle"
operating-points-v2: true
power-domains:
maxItems: 1
......
......@@ -46,8 +46,7 @@ properties:
interconnect-names:
maxItems: 4
operating-points-v2:
$ref: "/schemas/types.yaml#/definitions/phandle"
operating-points-v2: true
power-domains:
items:
......
......@@ -49,8 +49,7 @@ properties:
interconnect-names:
maxItems: 4
operating-points-v2:
$ref: "/schemas/types.yaml#/definitions/phandle"
operating-points-v2: true
power-domains:
items:
......
......@@ -51,8 +51,7 @@ properties:
minItems: 4
maxItems: 10
operating-points-v2:
$ref: "/schemas/types.yaml#/definitions/phandle"
operating-points-v2: true
power-domains:
minItems: 1
......
......@@ -50,8 +50,7 @@ properties:
items:
- const: hdmi
operating-points-v2:
$ref: "/schemas/types.yaml#/definitions/phandle"
operating-points-v2: true
power-domains:
items:
......
......@@ -90,8 +90,7 @@ properties:
items:
- const: dma-mem # read
operating-points-v2:
$ref: "/schemas/types.yaml#/definitions/phandle"
operating-points-v2: true
power-domains:
items:
......
......@@ -47,8 +47,7 @@ properties:
interconnect-names:
maxItems: 6
operating-points-v2:
$ref: "/schemas/types.yaml#/definitions/phandle"
operating-points-v2: true
power-domains:
items:
......
......@@ -30,8 +30,7 @@ properties:
items:
- description: module clock
operating-points-v2:
$ref: "/schemas/types.yaml#/definitions/phandle"
operating-points-v2: true
power-domains:
items:
......
......@@ -55,8 +55,7 @@ properties:
minItems: 4
maxItems: 5
operating-points-v2:
$ref: "/schemas/types.yaml#/definitions/phandle"
operating-points-v2: true
power-domains:
items:
......
......@@ -44,6 +44,7 @@ description: |
allOf:
- $ref: "../dma-controller.yaml#"
- $ref: /schemas/arm/keystone/ti,k3-sci-common.yaml#
properties:
"#dma-cells":
......@@ -78,14 +79,6 @@ properties:
msi-parent: true
ti,sci:
description: phandle to TI-SCI compatible System controller node
$ref: /schemas/types.yaml#/definitions/phandle
ti,sci-dev-id:
description: TI-SCI device id of UDMAP
$ref: /schemas/types.yaml#/definitions/uint32
ti,ringacc:
description: phandle to the ring accelerator node
$ref: /schemas/types.yaml#/definitions/phandle
......
......@@ -100,7 +100,9 @@ properties:
Channel specifier required when using OP-TEE transport.
protocol@11:
type: object
$ref: '#/$defs/protocol-node'
unevaluatedProperties: false
properties:
reg:
const: 0x11
......@@ -112,7 +114,9 @@ properties:
- '#power-domain-cells'
protocol@13:
type: object
$ref: '#/$defs/protocol-node'
unevaluatedProperties: false
properties:
reg:
const: 0x13
......@@ -124,7 +128,9 @@ properties:
- '#clock-cells'
protocol@14:
type: object
$ref: '#/$defs/protocol-node'
unevaluatedProperties: false
properties:
reg:
const: 0x14
......@@ -136,7 +142,9 @@ properties:
- '#clock-cells'
protocol@15:
type: object
$ref: '#/$defs/protocol-node'
unevaluatedProperties: false
properties:
reg:
const: 0x15
......@@ -148,7 +156,9 @@ properties:
- '#thermal-sensor-cells'
protocol@16:
type: object
$ref: '#/$defs/protocol-node'
unevaluatedProperties: false
properties:
reg:
const: 0x16
......@@ -160,20 +170,31 @@ properties:
- '#reset-cells'
protocol@17:
type: object
$ref: '#/$defs/protocol-node'
unevaluatedProperties: false
properties:
reg:
const: 0x17
regulators:
type: object
additionalProperties: false
description:
The list of all regulators provided by this SCMI controller.
properties:
'#address-cells':
const: 1
'#size-cells':
const: 0
patternProperties:
'^regulators@[0-9a-f]+$':
'^regulator@[0-9a-f]+$':
type: object
$ref: "../regulator/regulator.yaml#"
unevaluatedProperties: false
properties:
reg:
......@@ -184,15 +205,17 @@ properties:
- reg
protocol@18:
type: object
$ref: '#/$defs/protocol-node'
unevaluatedProperties: false
properties:
reg:
const: 0x18
additionalProperties: false
patternProperties:
'^protocol@[0-9a-f]+$':
$defs:
protocol-node:
type: object
description:
Each sub-node represents a protocol supported. If the platform
......
......@@ -44,8 +44,7 @@ properties:
items:
- const: fuse
operating-points-v2:
$ref: "/schemas/types.yaml#/definitions/phandle"
operating-points-v2: true
power-domains:
items:
......
Socionext SynQuacer I2C
Required properties:
- compatible : Must be "socionext,synquacer-i2c"
- reg : Offset and length of the register set for the device
- interrupts : A single interrupt specifier
- #address-cells : Must be <1>;
- #size-cells : Must be <0>;
- clock-names : Must contain "pclk".
- clocks : Must contain an entry for each name in clock-names.
(See the common clock bindings.)
Optional properties:
- clock-frequency : Desired I2C bus clock frequency in Hz. As only Normal and
Fast modes are supported, possible values are 100000 and
400000.
Example :
i2c@51210000 {
compatible = "socionext,synquacer-i2c";
reg = <0x51210000 0x1000>;
interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clock-names = "pclk";
clocks = <&clk_i2c>;
clock-frequency = <400000>;
};
......@@ -46,6 +46,8 @@ properties:
interrupts:
maxItems: 1
operating-points-v2: true
pinctrl-0: true
pinctrl-1: true
......
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/i2c/socionext,synquacer-i2c.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Socionext SynQuacer I2C Controller
maintainers:
- Ard Biesheuvel <ardb@kernel.org>
allOf:
- $ref: /schemas/i2c/i2c-controller.yaml#
properties:
compatible:
const: socionext,synquacer-i2c
reg:
maxItems: 1
clocks:
maxItems: 1
clock-names:
const: pclk
clock-frequency:
minimum: 100000
maximum: 400000
interrupts:
maxItems: 1
required:
- compatible
- reg
- interrupts
- clocks
- clock-names
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
i2c@51210000 {
compatible = "socionext,synquacer-i2c";
reg = <0x51210000 0x1000>;
interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clock-names = "pclk";
clocks = <&clk_i2c>;
clock-frequency = <400000>;
};
...
......@@ -109,7 +109,8 @@ properties:
for system suspend/resume.
brcm,int-fwd-mask:
$ref: /schemas/types.yaml#/definitions/uint32
$ref: /schemas/types.yaml#/definitions/uint32-array
maxItems: 1
description: >
if present, a bit mask to configure the interrupts which have a mux gate,
typically UARTs. Setting these bits will make their respective interrupt
......
Loongson ls1x Interrupt Controller
Required properties:
- compatible : should be "loongson,ls1x-intc". Valid strings are:
- reg : Specifies base physical address and size of the registers.
- interrupt-controller : Identifies the node as an interrupt controller
- #interrupt-cells : Specifies the number of cells needed to encode an
interrupt source. The value shall be 2.
- interrupts : Specifies the CPU interrupt the controller is connected to.
Example:
intc: interrupt-controller@1fd01040 {
compatible = "loongson,ls1x-intc";
reg = <0x1fd01040 0x18>;
interrupt-controller;
#interrupt-cells = <2>;
interrupt-parent = <&cpu_intc>;
interrupts = <2>;
};
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/interrupt-controller/loongson,ls1x-intc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Loongson-1 Interrupt Controller
maintainers:
- Keguang Zhang <keguang.zhang@gmail.com>
description:
Loongson-1 interrupt controller is connected to the MIPS core interrupt
controller, which controls several groups of interrupts.
properties:
compatible:
const: loongson,ls1x-intc
reg:
maxItems: 1
interrupt-controller: true
'#interrupt-cells':
const: 2
interrupts:
maxItems: 1
required:
- compatible
- reg
- interrupt-controller
- '#interrupt-cells'
- interrupts
additionalProperties: false
examples:
- |
intc0: interrupt-controller@1fd01040 {
compatible = "loongson,ls1x-intc";
reg = <0x1fd01040 0x18>;
interrupt-controller;
#interrupt-cells = <2>;
interrupt-parent = <&cpu_intc>;
interrupts = <2>;
};
......@@ -45,7 +45,6 @@ description:
from S-mode. So add thead,c900-plic to distinguish them.
maintainers:
- Sagar Kadam <sagar.kadam@sifive.com>
- Paul Walmsley <paul.walmsley@sifive.com>
- Palmer Dabbelt <palmer@dabbelt.com>
......
Socionext SynQuacer External Interrupt Unit (EXIU)
The Socionext Synquacer SoC has an external interrupt unit (EXIU)
that forwards a block of 32 configurable input lines to 32 adjacent
level-high type GICv3 SPIs.
Required properties:
- compatible : Should be "socionext,synquacer-exiu".
- reg : Specifies base physical address and size of the
control registers.
- interrupt-controller : Identifies the node as an interrupt controller.
- #interrupt-cells : Specifies the number of cells needed to encode an
interrupt source. The value must be 3.
- socionext,spi-base : The SPI number of the first SPI of the 32 adjacent
ones the EXIU forwards its interrups to.
Notes:
- Only SPIs can use the EXIU as an interrupt parent.
Example:
exiu: interrupt-controller@510c0000 {
compatible = "socionext,synquacer-exiu";
reg = <0x0 0x510c0000 0x0 0x20>;
interrupt-controller;
interrupt-parent = <&gic>;
#interrupt-cells = <3>;
socionext,spi-base = <112>;
};
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/interrupt-controller/socionext,synquacer-exiu.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Socionext SynQuacer External Interrupt Unit (EXIU)
maintainers:
- Ard Biesheuvel <ardb@kernel.org>
description: |+
The Socionext SynQuacer SoC has an external interrupt unit (EXIU)
that forwards a block of 32 configurable input lines to 32 adjacent
level-high type GICv3 SPIs.
properties:
compatible:
const: socionext,synquacer-exiu
reg:
maxItems: 1
'#interrupt-cells':
const: 3
interrupt-controller: true
socionext,spi-base:
$ref: /schemas/types.yaml#/definitions/uint32
description: The SPI number of the first SPI of the 32 adjacent ones the
EXIU forwards its interrupts to.
required:
- compatible
- reg
- '#interrupt-cells'
- interrupt-controller
- socionext,spi-base
unevaluatedProperties: false
examples:
- |
interrupt-controller@510c0000 {
compatible = "socionext,synquacer-exiu";
reg = <0x510c0000 0x20>;
interrupt-controller;
interrupt-parent = <&gic>;
#interrupt-cells = <3>;
socionext,spi-base = <112>;
};
...
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/bus/intel,ixp4xx-expansion-bus-controller.yaml#
$id: http://devicetree.org/schemas/memory-controllers/intel,ixp4xx-expansion-bus-controller.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Intel IXP4xx Expansion Bus Controller
......@@ -56,69 +56,7 @@ patternProperties:
description: Devices attached to chip selects are represented as
subnodes.
type: object
properties:
intel,ixp4xx-eb-t1:
description: Address timing, extend address phase with n cycles.
$ref: /schemas/types.yaml#/definitions/uint32
maximum: 3
intel,ixp4xx-eb-t2:
description: Setup chip select timing, extend setup phase with n cycles.
$ref: /schemas/types.yaml#/definitions/uint32
maximum: 3
intel,ixp4xx-eb-t3:
description: Strobe timing, extend strobe phase with n cycles.
$ref: /schemas/types.yaml#/definitions/uint32
maximum: 15
intel,ixp4xx-eb-t4:
description: Hold timing, extend hold phase with n cycles.
$ref: /schemas/types.yaml#/definitions/uint32
maximum: 3
intel,ixp4xx-eb-t5:
description: Recovery timing, extend recovery phase with n cycles.
$ref: /schemas/types.yaml#/definitions/uint32
maximum: 15
intel,ixp4xx-eb-cycle-type:
description: The type of cycles to use on the expansion bus for this
chip select. 0 = Intel cycles, 1 = Motorola cycles, 2 = HPI cycles.
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1, 2]
intel,ixp4xx-eb-byte-access-on-halfword:
description: Allow byte read access on half word devices.
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1]
intel,ixp4xx-eb-hpi-hrdy-pol-high:
description: Set HPI HRDY polarity to active high when using HPI.
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1]
intel,ixp4xx-eb-mux-address-and-data:
description: Multiplex address and data on the data bus.
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1]
intel,ixp4xx-eb-ahb-split-transfers:
description: Enable AHB split transfers.
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1]
intel,ixp4xx-eb-write-enable:
description: Enable write cycles.
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1]
intel,ixp4xx-eb-byte-access:
description: Expansion bus uses only 8 bits. The default is to use
16 bits.
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1]
$ref: /schemas/memory-controllers/intel,ixp4xx-expansion-peripheral-props.yaml#
required:
- compatible
......
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/memory-controllers/intel,ixp4xx-expansion-peripheral-props.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Peripheral properties for Intel IXP4xx Expansion Bus
description:
The IXP4xx expansion bus controller handles access to devices on the
memory-mapped expansion bus on the Intel IXP4xx family of system on chips,
including IXP42x, IXP43x, IXP45x and IXP46x.
maintainers:
- Linus Walleij <linus.walleij@linaro.org>
properties:
intel,ixp4xx-eb-t1:
description: Address timing, extend address phase with n cycles.
$ref: /schemas/types.yaml#/definitions/uint32
maximum: 3
intel,ixp4xx-eb-t2:
description: Setup chip select timing, extend setup phase with n cycles.
$ref: /schemas/types.yaml#/definitions/uint32
maximum: 3
intel,ixp4xx-eb-t3:
description: Strobe timing, extend strobe phase with n cycles.
$ref: /schemas/types.yaml#/definitions/uint32
maximum: 15
intel,ixp4xx-eb-t4:
description: Hold timing, extend hold phase with n cycles.
$ref: /schemas/types.yaml#/definitions/uint32
maximum: 3
intel,ixp4xx-eb-t5:
description: Recovery timing, extend recovery phase with n cycles.
$ref: /schemas/types.yaml#/definitions/uint32
maximum: 15
intel,ixp4xx-eb-cycle-type:
description: The type of cycles to use on the expansion bus for this
chip select. 0 = Intel cycles, 1 = Motorola cycles, 2 = HPI cycles.
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1, 2]
intel,ixp4xx-eb-byte-access-on-halfword:
description: Allow byte read access on half word devices.
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1]
intel,ixp4xx-eb-hpi-hrdy-pol-high:
description: Set HPI HRDY polarity to active high when using HPI.
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1]
intel,ixp4xx-eb-mux-address-and-data:
description: Multiplex address and data on the data bus.
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1]
intel,ixp4xx-eb-ahb-split-transfers:
description: Enable AHB split transfers.
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1]
intel,ixp4xx-eb-write-enable:
description: Enable write cycles.
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1]
intel,ixp4xx-eb-byte-access:
description: Expansion bus uses only 8 bits. The default is to use
16 bits.
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1]
additionalProperties: true
......@@ -34,5 +34,6 @@ required:
# The controller specific properties go here.
allOf:
- $ref: st,stm32-fmc2-ebi-props.yaml#
- $ref: intel,ixp4xx-expansion-peripheral-props.yaml#
additionalProperties: true
......@@ -90,7 +90,7 @@ properties:
interrupt-controller:
description: |
The GPMC driver implements and interrupt controller for
The GPMC driver implements an interrupt controller for
the NAND events "fifoevent" and "termcount" plus the
rising/falling edges on the GPMC_WAIT pins.
The interrupt number mapping is as follows
......
......@@ -82,8 +82,7 @@ properties:
iommus:
maxItems: 1
operating-points-v2:
$ref: "/schemas/types.yaml#/definitions/phandle"
operating-points-v2: true
power-domains:
items:
......
......@@ -15,6 +15,7 @@ description: |
allOf:
- $ref: "mtd.yaml#"
- $ref: /schemas/memory-controllers/mc-peripheral-props.yaml#
properties:
compatible:
......
......@@ -31,65 +31,56 @@ unevaluatedProperties: false
examples:
- |
// The UniPhier eFuse should be a subnode of a "soc-glue" node.
efuse@100 {
compatible = "socionext,uniphier-efuse";
reg = <0x100 0x28>;
};
soc-glue@5f900000 {
compatible = "simple-mfd";
efuse@200 {
compatible = "socionext,uniphier-efuse";
reg = <0x200 0x68>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x5f900000 0x2000>;
efuse@100 {
compatible = "socionext,uniphier-efuse";
reg = <0x100 0x28>;
/* Data cells */
usb_rterm0: trim@54,4 {
reg = <0x54 1>;
bits = <4 2>;
};
efuse@200 {
compatible = "socionext,uniphier-efuse";
reg = <0x200 0x68>;
#address-cells = <1>;
#size-cells = <1>;
/* Data cells */
usb_rterm0: trim@54,4 {
reg = <0x54 1>;
bits = <4 2>;
};
usb_rterm1: trim@55,4 {
reg = <0x55 1>;
bits = <4 2>;
};
usb_rterm2: trim@58,4 {
reg = <0x58 1>;
bits = <4 2>;
};
usb_rterm3: trim@59,4 {
reg = <0x59 1>;
bits = <4 2>;
};
usb_sel_t0: trim@54,0 {
reg = <0x54 1>;
bits = <0 4>;
};
usb_sel_t1: trim@55,0 {
reg = <0x55 1>;
bits = <0 4>;
};
usb_sel_t2: trim@58,0 {
reg = <0x58 1>;
bits = <0 4>;
};
usb_sel_t3: trim@59,0 {
reg = <0x59 1>;
bits = <0 4>;
};
usb_hs_i0: trim@56,0 {
reg = <0x56 1>;
bits = <0 4>;
};
usb_hs_i2: trim@5a,0 {
reg = <0x5a 1>;
bits = <0 4>;
};
usb_rterm1: trim@55,4 {
reg = <0x55 1>;
bits = <4 2>;
};
usb_rterm2: trim@58,4 {
reg = <0x58 1>;
bits = <4 2>;
};
usb_rterm3: trim@59,4 {
reg = <0x59 1>;
bits = <4 2>;
};
usb_sel_t0: trim@54,0 {
reg = <0x54 1>;
bits = <0 4>;
};
usb_sel_t1: trim@55,0 {
reg = <0x55 1>;
bits = <0 4>;
};
usb_sel_t2: trim@58,0 {
reg = <0x58 1>;
bits = <0 4>;
};
usb_sel_t3: trim@59,0 {
reg = <0x59 1>;
bits = <0 4>;
};
usb_hs_i0: trim@56,0 {
reg = <0x56 1>;
bits = <0 4>;
};
usb_hs_i2: trim@5a,0 {
reg = <0x5a 1>;
bits = <0 4>;
};
};
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pci/rockchip,rk3399-pcie-common.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Rockchip AXI PCIe Bridge Common Properties
maintainers:
- Shawn Lin <shawn.lin@rock-chips.com>
properties:
reg:
maxItems: 2
clocks:
maxItems: 4
clock-names:
items:
- const: aclk
- const: aclk-perf
- const: hclk
- const: pm
num-lanes:
maximum: 4
phys:
oneOf:
- maxItems: 1
- maxItems: 4
phy-names:
oneOf:
- const: pcie-phy
- items:
- const: pcie-phy-0
- const: pcie-phy-1
- const: pcie-phy-2
- const: pcie-phy-3
resets:
maxItems: 7
reset-names:
items:
- const: core
- const: mgmt
- const: mgmt-sticky
- const: pipe
- const: pm
- const: pclk
- const: aclk
required:
- compatible
- reg
- reg-names
- clocks
- clock-names
- phys
- phy-names
- resets
- reset-names
additionalProperties: true
...
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pci/rockchip,rk3399-pcie-ep.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Rockchip AXI PCIe Endpoint
maintainers:
- Shawn Lin <shawn.lin@rock-chips.com>
allOf:
- $ref: /schemas/pci/pci-ep.yaml#
- $ref: rockchip,rk3399-pcie-common.yaml#
properties:
compatible:
const: rockchip,rk3399-pcie-ep
reg: true
reg-names:
items:
- const: apb-base
- const: mem-base
rockchip,max-outbound-regions:
description: Maximum number of outbound regions
$ref: /schemas/types.yaml#/definitions/uint32
maximum: 32
default: 32
required:
- rockchip,max-outbound-regions
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/clock/rk3399-cru.h>
bus {
#address-cells = <2>;
#size-cells = <2>;
pcie-ep@f8000000 {
compatible = "rockchip,rk3399-pcie-ep";
reg = <0x0 0xfd000000 0x0 0x1000000>, <0x0 0x80000000 0x0 0x20000>;
reg-names = "apb-base", "mem-base";
clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>,
<&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>;
clock-names = "aclk", "aclk-perf",
"hclk", "pm";
max-functions = /bits/ 8 <8>;
num-lanes = <4>;
resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>,
<&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE> ,
<&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>, <&cru SRST_A_PCIE>;
reset-names = "core", "mgmt", "mgmt-sticky", "pipe",
"pm", "pclk", "aclk";
phys = <&pcie_phy 0>, <&pcie_phy 1>, <&pcie_phy 2>, <&pcie_phy 3>;
phy-names = "pcie-phy-0", "pcie-phy-1", "pcie-phy-2", "pcie-phy-3";
rockchip,max-outbound-regions = <16>;
};
};
...
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pci/rockchip,rk3399-pcie.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Rockchip AXI PCIe Root Port Bridge Host
maintainers:
- Shawn Lin <shawn.lin@rock-chips.com>
allOf:
- $ref: /schemas/pci/pci-bus.yaml#
- $ref: rockchip,rk3399-pcie-common.yaml#
properties:
compatible:
const: rockchip,rk3399-pcie
reg: true
reg-names:
items:
- const: axi-base
- const: apb-base
interrupts:
maxItems: 3
interrupt-names:
items:
- const: sys
- const: legacy
- const: client
aspm-no-l0s:
description: This property is needed if using 24MHz OSC for RC's PHY.
ep-gpios:
description: pre-reset GPIO
vpcie12v-supply:
description: The 12v regulator to use for PCIe.
vpcie3v3-supply:
description: The 3.3v regulator to use for PCIe.
vpcie1v8-supply:
description: The 1.8v regulator to use for PCIe.
vpcie0v9-supply:
description: The 0.9v regulator to use for PCIe.
interrupt-controller:
type: object
additionalProperties: false
properties:
'#address-cells':
const: 0
'#interrupt-cells':
const: 1
interrupt-controller: true
required:
- ranges
- "#interrupt-cells"
- interrupts
- interrupt-controller
- interrupt-map
- interrupt-map-mask
- msi-map
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/clock/rk3399-cru.h>
bus {
#address-cells = <2>;
#size-cells = <2>;
pcie@f8000000 {
compatible = "rockchip,rk3399-pcie";
device_type = "pci";
#address-cells = <3>;
#size-cells = <2>;
clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>,
<&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>;
clock-names = "aclk", "aclk-perf",
"hclk", "pm";
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH 0>;
interrupt-names = "sys", "legacy", "client";
ep-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>;
ranges = <0x83000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x600000
0x81000000 0x0 0xfa600000 0x0 0xfa600000 0x0 0x100000>;
num-lanes = <4>;
msi-map = <0x0 &its 0x0 0x1000>;
reg = <0x0 0xf8000000 0x0 0x2000000>, <0x0 0xfd000000 0x0 0x1000000>;
reg-names = "axi-base", "apb-base";
resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>,
<&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE> ,
<&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>, <&cru SRST_A_PCIE>;
reset-names = "core", "mgmt", "mgmt-sticky", "pipe",
"pm", "pclk", "aclk";
/* deprecated legacy PHY model */
phys = <&pcie_phy>;
phy-names = "pcie-phy";
pinctrl-names = "default";
pinctrl-0 = <&pcie_clkreq>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0 0 0 1 &pcie0_intc 0>,
<0 0 0 2 &pcie0_intc 1>,
<0 0 0 3 &pcie0_intc 2>,
<0 0 0 4 &pcie0_intc 3>;
pcie0_intc: interrupt-controller {
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <1>;
};
};
};
...
* Rockchip AXI PCIe Endpoint Controller DT description
Required properties:
- compatible: Should contain "rockchip,rk3399-pcie-ep"
- reg: Two register ranges as listed in the reg-names property
- reg-names: Must include the following names
- "apb-base"
- "mem-base"
- clocks: Must contain an entry for each entry in clock-names.
See ../clocks/clock-bindings.txt for details.
- clock-names: Must include the following entries:
- "aclk"
- "aclk-perf"
- "hclk"
- "pm"
- resets: Must contain seven entries for each entry in reset-names.
See ../reset/reset.txt for details.
- reset-names: Must include the following names
- "core"
- "mgmt"
- "mgmt-sticky"
- "pipe"
- "pm"
- "aclk"
- "pclk"
- pinctrl-names : The pin control state names
- pinctrl-0: The "default" pinctrl state
- phys: Must contain an phandle to a PHY for each entry in phy-names.
- phy-names: Must include 4 entries for all 4 lanes even if some of
them won't be used for your cases. Entries are of the form "pcie-phy-N":
where N ranges from 0 to 3.
(see example below and you MUST also refer to ../phy/rockchip-pcie-phy.txt
for changing the #phy-cells of phy node to support it)
- rockchip,max-outbound-regions: Maximum number of outbound regions
Optional Property:
- num-lanes: number of lanes to use
- max-functions: Maximum number of functions that can be configured (default 1).
pcie0-ep: pcie@f8000000 {
compatible = "rockchip,rk3399-pcie-ep";
#address-cells = <3>;
#size-cells = <2>;
rockchip,max-outbound-regions = <16>;
clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>,
<&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>;
clock-names = "aclk", "aclk-perf",
"hclk", "pm";
max-functions = /bits/ 8 <8>;
num-lanes = <4>;
reg = <0x0 0xfd000000 0x0 0x1000000>, <0x0 0x80000000 0x0 0x20000>;
reg-names = "apb-base", "mem-base";
resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>,
<&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE> ,
<&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>, <&cru SRST_A_PCIE>;
reset-names = "core", "mgmt", "mgmt-sticky", "pipe",
"pm", "pclk", "aclk";
phys = <&pcie_phy 0>, <&pcie_phy 1>, <&pcie_phy 2>, <&pcie_phy 3>;
phy-names = "pcie-phy-0", "pcie-phy-1", "pcie-phy-2", "pcie-phy-3";
pinctrl-names = "default";
pinctrl-0 = <&pcie_clkreq>;
};
* Rockchip AXI PCIe Root Port Bridge DT description
Required properties:
- #address-cells: Address representation for root ports, set to <3>
- #size-cells: Size representation for root ports, set to <2>
- #interrupt-cells: specifies the number of cells needed to encode an
interrupt source. The value must be 1.
- compatible: Should contain "rockchip,rk3399-pcie"
- reg: Two register ranges as listed in the reg-names property
- reg-names: Must include the following names
- "axi-base"
- "apb-base"
- clocks: Must contain an entry for each entry in clock-names.
See ../clocks/clock-bindings.txt for details.
- clock-names: Must include the following entries:
- "aclk"
- "aclk-perf"
- "hclk"
- "pm"
- msi-map: Maps a Requester ID to an MSI controller and associated
msi-specifier data. See ./pci-msi.txt
- interrupts: Three interrupt entries must be specified.
- interrupt-names: Must include the following names
- "sys"
- "legacy"
- "client"
- resets: Must contain seven entries for each entry in reset-names.
See ../reset/reset.txt for details.
- reset-names: Must include the following names
- "core"
- "mgmt"
- "mgmt-sticky"
- "pipe"
- "pm"
- "aclk"
- "pclk"
- pinctrl-names : The pin control state names
- pinctrl-0: The "default" pinctrl state
- #interrupt-cells: specifies the number of cells needed to encode an
interrupt source. The value must be 1.
- interrupt-map-mask and interrupt-map: standard PCI properties
Required properties for legacy PHY model (deprecated):
- phys: From PHY bindings: Phandle for the Generic PHY for PCIe.
- phy-names: MUST be "pcie-phy".
Required properties for per-lane PHY model (preferred):
- phys: Must contain an phandle to a PHY for each entry in phy-names.
- phy-names: Must include 4 entries for all 4 lanes even if some of
them won't be used for your cases. Entries are of the form "pcie-phy-N":
where N ranges from 0 to 3.
(see example below and you MUST also refer to ../phy/rockchip-pcie-phy.txt
for changing the #phy-cells of phy node to support it)
Optional Property:
- aspm-no-l0s: RC won't support ASPM L0s. This property is needed if
using 24MHz OSC for RC's PHY.
- ep-gpios: contain the entry for pre-reset GPIO
- num-lanes: number of lanes to use
- vpcie12v-supply: The phandle to the 12v regulator to use for PCIe.
- vpcie3v3-supply: The phandle to the 3.3v regulator to use for PCIe.
- vpcie1v8-supply: The phandle to the 1.8v regulator to use for PCIe.
- vpcie0v9-supply: The phandle to the 0.9v regulator to use for PCIe.
*Interrupt controller child node*
The core controller provides a single interrupt for legacy INTx. The PCIe node
should contain an interrupt controller node as a target for the PCI
'interrupt-map' property. This node represents the domain at which the four
INTx interrupts are decoded and routed.
Required properties for Interrupt controller child node:
- interrupt-controller: identifies the node as an interrupt controller
- #address-cells: specifies the number of cells needed to encode an
address. The value must be 0.
- #interrupt-cells: specifies the number of cells needed to encode an
interrupt source. The value must be 1.
Example:
pcie0: pcie@f8000000 {
compatible = "rockchip,rk3399-pcie";
#address-cells = <3>;
#size-cells = <2>;
clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>,
<&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>;
clock-names = "aclk", "aclk-perf",
"hclk", "pm";
bus-range = <0x0 0x1>;
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH 0>;
interrupt-names = "sys", "legacy", "client";
assigned-clocks = <&cru SCLK_PCIEPHY_REF>;
assigned-clock-parents = <&cru SCLK_PCIEPHY_REF100M>;
assigned-clock-rates = <100000000>;
ep-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>;
ranges = <0x83000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x600000
0x81000000 0x0 0xfa600000 0x0 0xfa600000 0x0 0x100000>;
num-lanes = <4>;
msi-map = <0x0 &its 0x0 0x1000>;
reg = <0x0 0xf8000000 0x0 0x2000000>, <0x0 0xfd000000 0x0 0x1000000>;
reg-names = "axi-base", "apb-base";
resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>,
<&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE> ,
<&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>, <&cru SRST_A_PCIE>;
reset-names = "core", "mgmt", "mgmt-sticky", "pipe",
"pm", "pclk", "aclk";
/* deprecated legacy PHY model */
phys = <&pcie_phy>;
phy-names = "pcie-phy";
pinctrl-names = "default";
pinctrl-0 = <&pcie_clkreq>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0 0 0 1 &pcie0_intc 0>,
<0 0 0 2 &pcie0_intc 1>,
<0 0 0 3 &pcie0_intc 2>,
<0 0 0 4 &pcie0_intc 3>;
pcie0_intc: interrupt-controller {
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <1>;
};
};
pcie0: pcie@f8000000 {
...
/* preferred per-lane PHY model */
phys = <&pcie_phy 0>, <&pcie_phy 1>, <&pcie_phy 2>, <&pcie_phy 3>;
phy-names = "pcie-phy-0", "pcie-phy-1", "pcie-phy-2", "pcie-phy-3";
...
};
......@@ -66,15 +66,11 @@ properties:
const: 0x104c
device-id:
oneOf:
- items:
- const: 0xb00d
- items:
- const: 0xb00f
- items:
- const: 0xb010
- items:
- const: 0xb013
enum:
- 0xb00d
- 0xb00f
- 0xb010
- 0xb013
msi-map: true
......
# SPDX-License-Identifier: BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/perf/riscv,pmu.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: RISC-V SBI PMU events
maintainers:
- Atish Patra <atishp@rivosinc.com>
description: |
The SBI PMU extension allows supervisor software to configure, start and
stop any performance counter at anytime. Thus, a user can leverage all
capabilities of performance analysis tools, such as perf, if the SBI PMU
extension is enabled. The following constraints apply:
The platform must provide information about PMU event to counter mappings
either via device tree or another way, specific to the platform.
Without the event to counter mappings, the SBI PMU extension cannot be used.
Platforms should provide information about the PMU event selector values
that should be encoded in the expected value of MHPMEVENTx while configuring
MHPMCOUNTERx for that specific event. The can either be done via device tree
or another way, specific to the platform.
The exact value to be written to MHPMEVENTx is completely dependent on the
platform.
For information on the SBI specification see the section "Performance
Monitoring Unit Extension" of:
https://github.com/riscv-non-isa/riscv-sbi-doc/blob/master/riscv-sbi.adoc
properties:
compatible:
const: riscv,pmu
riscv,event-to-mhpmevent:
$ref: /schemas/types.yaml#/definitions/uint32-matrix
description:
Represents an ONE-to-ONE mapping between a PMU event and the event
selector value that the platform expects to be written to the MHPMEVENTx
CSR for that event.
The mapping is encoded in an matrix format where each element represents
an event.
This property shouldn't encode any raw hardware event.
items:
items:
- description: event_idx, a 20-bit wide encoding of the event type and
code. Refer to the SBI specification for a complete description of
the event types and codes.
- description: upper 32 bits of the event selector value for MHPMEVENTx
- description: lower 32 bits of the event selector value for MHPMEVENTx
riscv,event-to-mhpmcounters:
$ref: /schemas/types.yaml#/definitions/uint32-matrix
description:
Represents a MANY-to-MANY mapping between a range of events and all the
MHPMCOUNTERx in a bitmap format that can be used to monitor these range
of events. The information is encoded in an matrix format where each
element represents a certain range of events and corresponding counters.
This property shouldn't encode any raw event.
items:
items:
- description: first event_idx of the range of events
- description: last event_idx of the range of events
- description: bitmap of MHPMCOUNTERx for this event
riscv,raw-event-to-mhpmcounters:
$ref: /schemas/types.yaml#/definitions/uint32-matrix
description:
Represents an ONE-to-MANY or MANY-to-MANY mapping between the rawevent(s)
and all the MHPMCOUNTERx in a bitmap format that can be used to monitor
that raw event.
The encoding of the raw events are platform specific. The information is
encoded in a matrix format where each element represents the specific raw
event(s).
If a platform directly encodes each raw PMU event as a unique ID, the
value of variant must be 0xffffffff_ffffffff.
items:
items:
- description:
upper 32 invariant bits for the range of events
- description:
lower 32 invariant bits for the range of events
- description:
upper 32 bits of the variant bit mask for the range of events
- description:
lower 32 bits of the variant bit mask for the range of events
- description:
bitmap of all MHPMCOUNTERx that can monitor the range of events
dependencies:
"riscv,event-to-mhpmevent": [ "riscv,event-to-mhpmcounters" ]
"riscv,event-to-mhpmcounters": [ "riscv,event-to-mhpmevent" ]
required:
- compatible
additionalProperties: false
examples:
- |
pmu {
compatible = "riscv,pmu";
riscv,event-to-mhpmevent = <0x0000B 0x0000 0x0001>;
riscv,event-to-mhpmcounters = <0x00001 0x00001 0x00000001>,
<0x00002 0x00002 0x00000004>,
<0x00003 0x0000A 0x00000ff8>,
<0x10000 0x10033 0x000ff000>;
riscv,raw-event-to-mhpmcounters =
/* For event ID 0x0002 */
<0x0000 0x0002 0xffffffff 0xffffffff 0x00000f8>,
/* For event ID 0-4 */
<0x0 0x0 0xffffffff 0xfffffff0 0x00000ff0>,
/* For event ID 0xffffffff0000000f - 0xffffffff000000ff */
<0xffffffff 0x0 0xffffffff 0xffffff0f 0x00000ff0>;
};
- |
/*
* For HiFive Unmatched board the encodings can be found here
* https://sifive.cdn.prismic.io/sifive/1a82e600-1f93-4f41-b2d8-86ed8b16acba_fu740-c000-manual-v1p6.pdf
*
* This example also binds standard SBI PMU hardware IDs to U74 PMU event
* codes, U74 uses a bitfield for events encoding, so several U74 events
* can be bound to a single perf ID.
* See SBI PMU hardware IDs in arch/riscv/include/asm/sbi.h
*/
pmu {
compatible = "riscv,pmu";
riscv,event-to-mhpmevent =
/* SBI_PMU_HW_CACHE_REFERENCES -> Instruction or Data cache/ITIM busy */
<0x00003 0x00000000 0x1801>,
/* SBI_PMU_HW_CACHE_MISSES -> Instruction or Data cache miss or MMIO access */
<0x00004 0x00000000 0x0302>,
/* SBI_PMU_HW_BRANCH_INSTRUCTIONS -> Conditional branch retired */
<0x00005 0x00000000 0x4000>,
/* SBI_PMU_HW_BRANCH_MISSES -> Branch or jump misprediction */
<0x00006 0x00000000 0x6001>,
/* L1D_READ_MISS -> Data cache miss or MMIO access */
<0x10001 0x00000000 0x0202>,
/* L1D_WRITE_ACCESS -> Data cache write-back */
<0x10002 0x00000000 0x0402>,
/* L1I_READ_ACCESS -> Instruction cache miss */
<0x10009 0x00000000 0x0102>,
/* LL_READ_MISS -> UTLB miss */
<0x10011 0x00000000 0x2002>,
/* DTLB_READ_MISS -> Data TLB miss */
<0x10019 0x00000000 0x1002>,
/* ITLB_READ_MISS-> Instruction TLB miss */
<0x10021 0x00000000 0x0802>;
riscv,event-to-mhpmcounters = <0x00003 0x00006 0x18>,
<0x10001 0x10002 0x18>,
<0x10009 0x10009 0x18>,
<0x10011 0x10011 0x18>,
<0x10019 0x10019 0x18>,
<0x10021 0x10021 0x18>;
riscv,raw-event-to-mhpmcounters = <0x0 0x0 0xffffffff 0xfc0000ff 0x18>,
<0x0 0x1 0xffffffff 0xfff800ff 0x18>,
<0x0 0x2 0xffffffff 0xffffe0ff 0x18>;
};
......@@ -27,7 +27,8 @@ properties:
description: phandle of syscon used to control usb tcxo.
hisilicon,eye-diagram-param:
$ref: /schemas/types.yaml#/definitions/uint32
$ref: /schemas/types.yaml#/definitions/uint32-array
maxItems: 1
description: Eye diagram for phy.
required:
......
......@@ -32,7 +32,8 @@ properties:
description: phandle of syscon used to control phy deep sleep.
hisilicon,eye-diagram-param:
$ref: /schemas/types.yaml#/definitions/uint32
$ref: /schemas/types.yaml#/definitions/uint32-array
maxItems: 1
description: Eye diagram for phy.
hisilicon,tx-vboost-lvl:
......
......@@ -117,20 +117,12 @@ additionalProperties: false
examples:
- |
ahci-glue@65700000 {
compatible = "socionext,uniphier-pxs3-ahci-glue",
"simple-mfd";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x65700000 0x100>;
ahci_phy: phy@10 {
compatible = "socionext,uniphier-pxs3-ahci-phy";
reg = <0x10 0x10>;
#phy-cells = <0>;
clock-names = "link", "phy";
clocks = <&sys_clk 28>, <&sys_clk 30>;
reset-names = "link", "phy";
resets = <&sys_rst 28>, <&sys_rst 30>;
};
ahci_phy: phy@10 {
compatible = "socionext,uniphier-pxs3-ahci-phy";
reg = <0x10 0x10>;
#phy-cells = <0>;
clock-names = "link", "phy";
clocks = <&sys_clk 28>, <&sys_clk 30>;
reset-names = "link", "phy";
resets = <&sys_rst 28>, <&sys_rst 30>;
};
......@@ -61,28 +61,23 @@ examples:
- |
// The UniPhier usb2-phy should be a subnode of a "syscon" compatible node.
soc-glue@5f800000 {
compatible = "socionext,uniphier-ld11-soc-glue", "simple-mfd", "syscon";
reg = <0x5f800000 0x2000>;
usb-controller {
compatible = "socionext,uniphier-ld11-usb2-phy";
#address-cells = <1>;
#size-cells = <0>;
usb_phy0: phy@0 {
reg = <0>;
#phy-cells = <0>;
};
usb_phy1: phy@1 {
reg = <1>;
#phy-cells = <0>;
};
usb_phy2: phy@2 {
reg = <2>;
#phy-cells = <0>;
};
usb-hub {
compatible = "socionext,uniphier-ld11-usb2-phy";
#address-cells = <1>;
#size-cells = <0>;
usb_phy0: phy@0 {
reg = <0>;
#phy-cells = <0>;
};
usb_phy1: phy@1 {
reg = <1>;
#phy-cells = <0>;
};
usb_phy2: phy@2 {
reg = <2>;
#phy-cells = <0>;
};
};
......@@ -146,22 +146,15 @@ additionalProperties: false
examples:
- |
usb-glue@65b00000 {
compatible = "socionext,uniphier-ld20-dwc3-glue", "simple-mfd";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x65b00000 0x400>;
usb_hsphy0: hs-phy@200 {
compatible = "socionext,uniphier-ld20-usb3-hsphy";
reg = <0x200 0x10>;
#phy-cells = <0>;
clock-names = "link", "phy";
clocks = <&sys_clk 14>, <&sys_clk 16>;
reset-names = "link", "phy";
resets = <&sys_rst 14>, <&sys_rst 16>;
vbus-supply = <&usb_vbus0>;
nvmem-cell-names = "rterm", "sel_t", "hs_i";
nvmem-cells = <&usb_rterm0>, <&usb_sel_t0>, <&usb_hs_i0>;
};
usb_hsphy0: phy@200 {
compatible = "socionext,uniphier-ld20-usb3-hsphy";
reg = <0x200 0x10>;
#phy-cells = <0>;
clock-names = "link", "phy";
clocks = <&sys_clk 14>, <&sys_clk 16>;
reset-names = "link", "phy";
resets = <&sys_rst 14>, <&sys_rst 16>;
vbus-supply = <&usb_vbus0>;
nvmem-cell-names = "rterm", "sel_t", "hs_i";
nvmem-cells = <&usb_rterm0>, <&usb_sel_t0>, <&usb_hs_i0>;
};
......@@ -131,21 +131,13 @@ additionalProperties: false
examples:
- |
usb-glue@65b00000 {
compatible = "socionext,uniphier-ld20-dwc3-glue",
"simple-mfd";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x65b00000 0x400>;
usb_ssphy0: ss-phy@300 {
compatible = "socionext,uniphier-ld20-usb3-ssphy";
reg = <0x300 0x10>;
#phy-cells = <0>;
clock-names = "link", "phy";
clocks = <&sys_clk 14>, <&sys_clk 16>;
reset-names = "link", "phy";
resets = <&sys_rst 14>, <&sys_rst 16>;
vbus-supply = <&usb_vbus0>;
};
usb_ssphy0: phy@300 {
compatible = "socionext,uniphier-ld20-usb3-ssphy";
reg = <0x300 0x10>;
#phy-cells = <0>;
clock-names = "link", "phy";
clocks = <&sys_clk 14>, <&sys_clk 16>;
reset-names = "link", "phy";
resets = <&sys_rst 14>, <&sys_rst 16>;
vbus-supply = <&usb_vbus0>;
};
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/socionext,uniphier-pinctrl.yaml#
......@@ -69,11 +70,17 @@ examples:
- |
// The UniPhier pinctrl should be a subnode of a "syscon" compatible node.
soc-glue@5f800000 {
compatible = "socionext,uniphier-pro4-soc-glue", "simple-mfd", "syscon";
reg = <0x5f800000 0x2000>;
pinctrl {
compatible = "socionext,uniphier-ld20-pinctrl";
pinctrl_ether_rgmii: ether-rgmii {
groups = "ether_rgmii";
function = "ether_rgmii";
pinctrl: pinctrl {
compatible = "socionext,uniphier-pro4-pinctrl";
tx {
pins = "RGMII_TXCLK", "RGMII_TXD0", "RGMII_TXD1",
"RGMII_TXD2", "RGMII_TXD3", "RGMII_TXCTL";
drive-strength = <9>;
};
};
};
......@@ -43,9 +43,6 @@ properties:
domain would be considered as capable of being powered-on or powered-off.
operating-points-v2:
$ref: /schemas/types.yaml#/definitions/phandle-array
items:
maxItems: 1
description:
Phandles to the OPP tables of power domains provided by a power domain
provider. If the provider provides a single power domain only or all
......
......@@ -63,8 +63,7 @@ properties:
pinctrl-1:
description: configuration for the sleep state
operating-points-v2:
$ref: /schemas/types.yaml#/definitions/phandle
operating-points-v2: true
power-domains:
items:
......
......@@ -8,7 +8,6 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: SiFive PWM controller
maintainers:
- Sagar Kadam <sagar.kadam@sifive.com>
- Paul Walmsley <paul.walmsley@sifive.com>
description:
......
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/regulator/mps,mpq7932.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Monolithic Power System MPQ7932 PMIC
maintainers:
- Saravanan Sekar <saravanan@linumiz.com>
properties:
compatible:
enum:
- mps,mpq7932
reg:
maxItems: 1
regulators:
type: object
description: |
list of regulators provided by this controller, must be named
after their hardware counterparts BUCK[1-6]
patternProperties:
"^buck[1-6]$":
type: object
$ref: regulator.yaml#
unevaluatedProperties: false
additionalProperties: false
required:
- compatible
- reg
- regulators
additionalProperties: false
examples:
- |
i2c {
#address-cells = <1>;
#size-cells = <0>;
pmic@3 {
compatible = "mps,mpq7932";
reg = <0x3>;
regulators {
buck1 {
regulator-name = "buck1";
regulator-min-microvolt = <1600000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
};
buck2 {
regulator-name = "buck2";
regulator-min-microvolt = <1700000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
};
};
};
};
...
......@@ -89,18 +89,11 @@ required:
examples:
- |
usb-glue@65b00000 {
compatible = "simple-mfd";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x65b00000 0x400>;
usb_vbus0: regulators@100 {
compatible = "socionext,uniphier-ld20-usb3-regulator";
reg = <0x100 0x10>;
clock-names = "link";
clocks = <&sys_clk 14>;
reset-names = "link";
resets = <&sys_rst 14>;
};
usb_vbus0: regulators@100 {
compatible = "socionext,uniphier-ld20-usb3-regulator";
reg = <0x100 0x10>;
clock-names = "link";
clocks = <&sys_clk 14>;
reset-names = "link";
resets = <&sys_rst 14>;
};
......@@ -31,17 +31,17 @@ properties:
reg: true
size:
$ref: /schemas/types.yaml#/definitions/uint32-array
minItems: 1
maxItems: 2
oneOf:
- $ref: /schemas/types.yaml#/definitions/uint32
- $ref: /schemas/types.yaml#/definitions/uint64
description: >
Length based on parent's \#size-cells. Size in bytes of memory to
reserve.
alignment:
$ref: /schemas/types.yaml#/definitions/uint32-array
minItems: 1
maxItems: 2
oneOf:
- $ref: /schemas/types.yaml#/definitions/uint32
- $ref: /schemas/types.yaml#/definitions/uint64
description: >
Length based on parent's \#size-cells. Address boundary for
alignment of allocation.
......
......@@ -95,19 +95,12 @@ required:
examples:
- |
usb-glue@65b00000 {
compatible = "simple-mfd";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x65b00000 0x400>;
usb_rst: reset@0 {
compatible = "socionext,uniphier-ld20-usb3-reset";
reg = <0x0 0x4>;
#reset-cells = <1>;
clock-names = "link";
clocks = <&sys_clk 14>;
reset-names = "link";
resets = <&sys_rst 14>;
};
usb_rst: reset-controller@0 {
compatible = "socionext,uniphier-ld20-usb3-reset";
reg = <0x0 0x4>;
#reset-cells = <1>;
clock-names = "link";
clocks = <&sys_clk 14>;
reset-names = "link";
resets = <&sys_rst 14>;
};
......@@ -66,53 +66,7 @@ required:
examples:
- |
sysctrl@61840000 {
compatible = "socionext,uniphier-sysctrl", "simple-mfd", "syscon";
reg = <0x61840000 0x4000>;
reset {
compatible = "socionext,uniphier-ld11-reset";
#reset-cells = <1>;
};
// other nodes ...
};
- |
mioctrl@59810000 {
compatible = "socionext,uniphier-mioctrl", "simple-mfd", "syscon";
reg = <0x59810000 0x800>;
reset {
compatible = "socionext,uniphier-ld11-mio-reset";
#reset-cells = <1>;
};
// other nodes ...
};
- |
perictrl@59820000 {
compatible = "socionext,uniphier-perictrl", "simple-mfd", "syscon";
reg = <0x59820000 0x200>;
reset {
compatible = "socionext,uniphier-ld11-peri-reset";
#reset-cells = <1>;
};
// other nodes ...
};
- |
adamv@57920000 {
compatible = "socionext,uniphier-ld11-adamv", "simple-mfd", "syscon";
reg = <0x57920000 0x1000>;
reset {
compatible = "socionext,uniphier-ld11-adamv-reset";
#reset-cells = <1>;
};
// other nodes ...
reset-controller {
compatible = "socionext,uniphier-ld11-reset";
#reset-cells = <1>;
};
......@@ -8,8 +8,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: SiFive Composable Cache Controller
maintainers:
- Sagar Kadam <sagar.kadam@sifive.com>
- Paul Walmsley <paul.walmsley@sifive.com>
- Paul Walmsley <paul.walmsley@sifive.com>
description:
The SiFive Composable Cache Controller is used to provide access to fast copies
......
......@@ -11,6 +11,7 @@ maintainers:
allOf:
- $ref: serial.yaml#
- $ref: /schemas/memory-controllers/mc-peripheral-props.yaml#
- if:
anyOf:
- required:
......
......@@ -96,7 +96,7 @@ then:
rts-gpios: false
patternProperties:
".*":
"^bluetooth|gnss|gps|mcu$":
if:
type: object
then:
......
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/soc/socionext/socionext,uniphier-adamv.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Socionext UniPhier ADAMV block
maintainers:
- Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
description: |+
ADAMV block implemented on Socionext UniPhier SoCs is an analog signal
amplifier that is a part of the external video and audio I/O system.
This block is defined for controlling audio I/O reset only.
properties:
compatible:
items:
- enum:
- socionext,uniphier-ld11-adamv
- socionext,uniphier-ld20-adamv
- const: simple-mfd
- const: syscon
reg:
maxItems: 1
reset-controller:
$ref: /schemas/reset/socionext,uniphier-reset.yaml#
required:
- compatible
- reg
additionalProperties: false
examples:
- |
syscon@57920000 {
compatible = "socionext,uniphier-ld20-adamv",
"simple-mfd", "syscon";
reg = <0x57920000 0x1000>;
reset-controller {
compatible = "socionext,uniphier-ld20-adamv-reset";
#reset-cells = <1>;
};
};
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/soc/socionext/socionext,uniphier-ahci-glue.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Socionext UniPhier SoC AHCI glue layer
maintainers:
- Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
description: |+
AHCI glue layer implemented on Socionext UniPhier SoCs is a sideband
logic handling signals to AHCI host controller inside AHCI component.
properties:
compatible:
items:
- enum:
- socionext,uniphier-pro4-ahci-glue
- socionext,uniphier-pxs2-ahci-glue
- socionext,uniphier-pxs3-ahci-glue
- const: simple-mfd
reg:
maxItems: 1
"#address-cells":
const: 1
"#size-cells":
const: 1
ranges: true
patternProperties:
"^reset-controller@[0-9a-f]+$":
$ref: /schemas/reset/socionext,uniphier-glue-reset.yaml#
"phy@[0-9a-f]+$":
$ref: /schemas/phy/socionext,uniphier-ahci-phy.yaml#
required:
- compatible
- reg
additionalProperties: false
examples:
- |
sata-controller@65700000 {
compatible = "socionext,uniphier-pxs3-ahci-glue", "simple-mfd";
reg = <0x65b00000 0x400>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x65700000 0x100>;
reset-controller@0 {
compatible = "socionext,uniphier-pxs3-ahci-reset";
reg = <0x0 0x4>;
clock-names = "link";
clocks = <&sys_clk 28>;
reset-names = "link";
resets = <&sys_rst 28>;
#reset-cells = <1>;
};
phy@10 {
compatible = "socionext,uniphier-pxs3-ahci-phy";
reg = <0x10 0x10>;
clock-names = "link", "phy";
clocks = <&sys_clk 28>, <&sys_clk 30>;
reset-names = "link", "phy";
resets = <&sys_rst 28>, <&sys_rst 30>;
#phy-cells = <0>;
};
};
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/soc/socionext/socionext,uniphier-dwc3-glue.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Socionext UniPhier SoC DWC3 USB3.0 glue layer
maintainers:
- Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
description: |+
DWC3 USB3.0 glue layer implemented on Socionext UniPhier SoCs is
a sideband logic handling signals to DWC3 host controller inside
USB3.0 component.
properties:
compatible:
items:
- enum:
- socionext,uniphier-pro4-dwc3-glue
- socionext,uniphier-pro5-dwc3-glue
- socionext,uniphier-pxs2-dwc3-glue
- socionext,uniphier-ld20-dwc3-glue
- socionext,uniphier-pxs3-dwc3-glue
- socionext,uniphier-nx1-dwc3-glue
- const: simple-mfd
reg:
maxItems: 1
"#address-cells":
const: 1
"#size-cells":
const: 1
ranges: true
patternProperties:
"^reset-controller@[0-9a-f]+$":
$ref: /schemas/reset/socionext,uniphier-glue-reset.yaml#
"^regulator@[0-9a-f]+$":
$ref: /schemas/regulator/socionext,uniphier-regulator.yaml#
"^phy@[0-9a-f]+$":
oneOf:
- $ref: /schemas/phy/socionext,uniphier-usb3hs-phy.yaml#
- $ref: /schemas/phy/socionext,uniphier-usb3ss-phy.yaml#
required:
- compatible
- reg
additionalProperties: false
examples:
- |
usb@65b00000 {
compatible = "socionext,uniphier-ld20-dwc3-glue", "simple-mfd";
reg = <0x65b00000 0x400>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x65b00000 0x400>;
reset-controller@0 {
compatible = "socionext,uniphier-ld20-usb3-reset";
reg = <0x0 0x4>;
#reset-cells = <1>;
clock-names = "link";
clocks = <&sys_clk 14>;
reset-names = "link";
resets = <&sys_rst 14>;
};
regulator@100 {
compatible = "socionext,uniphier-ld20-usb3-regulator";
reg = <0x100 0x10>;
clock-names = "link";
clocks = <&sys_clk 14>;
reset-names = "link";
resets = <&sys_rst 14>;
};
phy@200 {
compatible = "socionext,uniphier-ld20-usb3-hsphy";
reg = <0x200 0x10>;
#phy-cells = <0>;
clock-names = "link", "phy";
clocks = <&sys_clk 14>, <&sys_clk 16>;
reset-names = "link", "phy";
resets = <&sys_rst 14>, <&sys_rst 16>;
};
phy@300 {
compatible = "socionext,uniphier-ld20-usb3-ssphy";
reg = <0x300 0x10>;
#phy-cells = <0>;
clock-names = "link", "phy";
clocks = <&sys_clk 14>, <&sys_clk 18>;
reset-names = "link", "phy";
resets = <&sys_rst 14>, <&sys_rst 18>;
};
};
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/soc/socionext/socionext,uniphier-mioctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Socionext UniPhier media I/O block (MIO) controller
maintainers:
- Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
description: |+
Media I/O block implemented on Socionext UniPhier SoCs is a legacy
integrated component of the stream type peripherals including USB2.0,
SD/eMMC, and MIO-DMAC.
Media I/O block has a common logic to control the component.
Recent SoCs have SD interface logic specialized only for SD functions
as a subset of media I/O block. See socionext,uniphier-sdctrl.yaml.
properties:
compatible:
items:
- enum:
- socionext,uniphier-ld4-mioctrl
- socionext,uniphier-pro4-mioctrl
- socionext,uniphier-sld8-mioctrl
- socionext,uniphier-ld11-mioctrl
- const: simple-mfd
- const: syscon
reg:
maxItems: 1
clock-controller:
$ref: /schemas/clock/socionext,uniphier-clock.yaml#
reset-controller:
$ref: /schemas/reset/socionext,uniphier-reset.yaml#
required:
- compatible
- reg
additionalProperties: false
examples:
- |
syscon@5b3e0000 {
compatible = "socionext,uniphier-ld11-mioctrl",
"simple-mfd", "syscon";
reg = <0x5b3e0000 0x800>;
clock-controller {
compatible = "socionext,uniphier-ld11-mio-clock";
#clock-cells = <1>;
};
reset-controller {
compatible = "socionext,uniphier-ld11-mio-reset";
#reset-cells = <1>;
resets = <&sys_rst 7>;
};
};
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/soc/socionext/socionext,uniphier-perictrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Socionext UniPhier peripheral block controller
maintainers:
- Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
description: |+
Peripheral block implemented on Socionext UniPhier SoCs is an integrated
component of the peripherals including UART, I2C/FI2C, and SCSSI.
Peripheral block controller is a logic to control the component.
properties:
compatible:
items:
- enum:
- socionext,uniphier-ld4-perictrl
- socionext,uniphier-pro4-perictrl
- socionext,uniphier-pro5-perictrl
- socionext,uniphier-pxs2-perictrl
- socionext,uniphier-sld8-perictrl
- socionext,uniphier-ld11-perictrl
- socionext,uniphier-ld20-perictrl
- socionext,uniphier-pxs3-perictrl
- socionext,uniphier-nx1-perictrl
- const: simple-mfd
- const: syscon
reg:
maxItems: 1
clock-controller:
$ref: /schemas/clock/socionext,uniphier-clock.yaml#
reset-controller:
$ref: /schemas/reset/socionext,uniphier-reset.yaml#
required:
- compatible
- reg
additionalProperties: false
examples:
- |
syscon@59820000 {
compatible = "socionext,uniphier-ld20-perictrl",
"simple-mfd", "syscon";
reg = <0x59820000 0x200>;
clock-controller {
compatible = "socionext,uniphier-ld20-peri-clock";
#clock-cells = <1>;
};
reset-controller {
compatible = "socionext,uniphier-ld20-peri-reset";
#reset-cells = <1>;
};
};
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/soc/socionext/socionext,uniphier-sdctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Socionext UniPhier SD interface logic
maintainers:
- Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
description: |+
SD interface logic implemented on Socionext UniPhier SoCs is
attached outside SDHC, and has some SD related functions such as
clock control, reset control, mode switch, and so on.
properties:
compatible:
items:
- enum:
- socionext,uniphier-pro5-sdctrl
- socionext,uniphier-pxs2-sdctrl
- socionext,uniphier-ld11-sdctrl
- socionext,uniphier-ld20-sdctrl
- socionext,uniphier-pxs3-sdctrl
- socionext,uniphier-nx1-sdctrl
- const: simple-mfd
- const: syscon
reg:
maxItems: 1
clock-controller:
$ref: /schemas/clock/socionext,uniphier-clock.yaml#
reset-controller:
$ref: /schemas/reset/socionext,uniphier-reset.yaml#
required:
- compatible
- reg
additionalProperties: false
examples:
- |
syscon@59810000 {
compatible = "socionext,uniphier-ld20-sdctrl",
"simple-mfd", "syscon";
reg = <0x59810000 0x400>;
clock-controller {
compatible = "socionext,uniphier-ld20-sd-clock";
#clock-cells = <1>;
};
reset-controller {
compatible = "socionext,uniphier-ld20-sd-reset";
#reset-cells = <1>;
};
};
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/soc/socionext/socionext,uniphier-soc-glue-debug.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Socionext UniPhier SoC-glue logic debug part
maintainers:
- Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
description: |+
SoC-glue logic debug part implemented on Socionext UniPhier SoCs is
a collection of miscellaneous function registers handling signals outside
system components for debug and monitor use.
properties:
compatible:
items:
- enum:
- socionext,uniphier-ld4-soc-glue-debug
- socionext,uniphier-pro4-soc-glue-debug
- socionext,uniphier-pro5-soc-glue-debug
- socionext,uniphier-pxs2-soc-glue-debug
- socionext,uniphier-sld8-soc-glue-debug
- socionext,uniphier-ld11-soc-glue-debug
- socionext,uniphier-ld20-soc-glue-debug
- socionext,uniphier-pxs3-soc-glue-debug
- socionext,uniphier-nx1-soc-glue-debug
- const: simple-mfd
- const: syscon
reg:
maxItems: 1
"#address-cells":
const: 1
"#size-cells":
const: 1
ranges: true
patternProperties:
"^efuse@[0-9a-f]+$":
$ref: /schemas/nvmem/socionext,uniphier-efuse.yaml#
required:
- compatible
- reg
additionalProperties: false
examples:
- |
syscon@5f900000 {
compatible = "socionext,uniphier-pxs2-soc-glue-debug",
"simple-mfd", "syscon";
reg = <0x5f900000 0x2000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x5f900000 0x2000>;
efuse@100 {
compatible = "socionext,uniphier-efuse";
reg = <0x100 0x28>;
};
};
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/soc/socionext/socionext,uniphier-soc-glue.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Socionext UniPhier SoC-glue logic
maintainers:
- Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
description: |+
SoC-glue logic implemented on Socionext UniPhier SoCs is a collection of
miscellaneous function registers handling signals outside system components.
properties:
compatible:
items:
- enum:
- socionext,uniphier-ld4-soc-glue
- socionext,uniphier-pro4-soc-glue
- socionext,uniphier-pro5-soc-glue
- socionext,uniphier-pxs2-soc-glue
- socionext,uniphier-sld8-soc-glue
- socionext,uniphier-ld11-soc-glue
- socionext,uniphier-ld20-soc-glue
- socionext,uniphier-pxs3-soc-glue
- socionext,uniphier-nx1-soc-glue
- const: simple-mfd
- const: syscon
reg:
maxItems: 1
pinctrl:
$ref: /schemas/pinctrl/socionext,uniphier-pinctrl.yaml#
usb-hub:
$ref: /schemas/phy/socionext,uniphier-usb2-phy.yaml#
clock-controller:
$ref: /schemas/clock/socionext,uniphier-clock.yaml#
allOf:
- if:
not:
properties:
compatible:
contains:
enum:
- socionext,uniphier-pro4-soc-glue
- socionext,uniphier-ld11-soc-glue
then:
properties:
usb-hub: false
- if:
not:
properties:
compatible:
contains:
const: socionext,uniphier-pro4-soc-glue
then:
properties:
clock-controller: false
required:
- compatible
- reg
additionalProperties: false
examples:
- |
syscon@5f800000 {
compatible = "socionext,uniphier-pro4-soc-glue",
"simple-mfd", "syscon";
reg = <0x5f800000 0x2000>;
pinctrl {
compatible = "socionext,uniphier-pro4-pinctrl";
};
usb-hub {
compatible = "socionext,uniphier-pro4-usb2-phy";
#address-cells = <1>;
#size-cells = <0>;
phy@0 {
reg = <0>;
#phy-cells = <0>;
};
phy@1 {
reg = <1>;
#phy-cells = <0>;
};
phy@2 {
reg = <2>;
#phy-cells = <0>;
};
phy@3 {
reg = <3>;
#phy-cells = <0>;
};
};
clock-controller {
compatible = "socionext,uniphier-pro4-sg-clock";
#clock-cells = <1>;
};
};
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/soc/socionext/socionext,uniphier-sysctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Socionext UniPhier system controller
maintainers:
- Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
description: |+
System controller implemented on Socionext UniPhier SoCs has multiple
functions such as clock control, reset control, internal watchdog timer,
thermal management, and so on.
properties:
compatible:
items:
- enum:
- socionext,uniphier-ld4-sysctrl
- socionext,uniphier-pro4-sysctrl
- socionext,uniphier-pro5-sysctrl
- socionext,uniphier-pxs2-sysctrl
- socionext,uniphier-sld8-sysctrl
- socionext,uniphier-ld11-sysctrl
- socionext,uniphier-ld20-sysctrl
- socionext,uniphier-pxs3-sysctrl
- socionext,uniphier-nx1-sysctrl
- const: simple-mfd
- const: syscon
reg:
maxItems: 1
clock-controller:
$ref: /schemas/clock/socionext,uniphier-clock.yaml#
reset-controller:
$ref: /schemas/reset/socionext,uniphier-reset.yaml#
watchdog:
$ref: /schemas/watchdog/socionext,uniphier-wdt.yaml#
thermal-sensor:
$ref: /schemas/thermal/socionext,uniphier-thermal.yaml#
allOf:
- if:
properties:
compatible:
contains:
const: socionext,uniphier-ld4-sysctrl
then:
properties:
watchdog: false
- if:
properties:
compatible:
contains:
enum:
- socionext,uniphier-ld4-sysctrl
- socionext,uniphier-pro4-sysctrl
- socionext,uniphier-sld8-sysctrl
- socionext,uniphier-ld11-sysctrl
then:
properties:
thermal-sensor: false
additionalProperties: false
required:
- compatible
- reg
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
syscon@61840000 {
compatible = "socionext,uniphier-ld20-sysctrl",
"simple-mfd", "syscon";
reg = <0x61840000 0x4000>;
clock-controller {
compatible = "socionext,uniphier-ld20-clock";
#clock-cells = <1>;
};
reset-controller {
compatible = "socionext,uniphier-ld20-reset";
#reset-cells = <1>;
};
watchdog {
compatible = "socionext,uniphier-wdt";
};
thermal-sensor {
compatible = "socionext,uniphier-ld20-thermal";
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
#thermal-sensor-cells = <0>;
};
};
......@@ -25,6 +25,9 @@ description: |
The Ring Accelerator is a hardware module that is responsible for accelerating
management of the packet queues. The K3 SoCs can have more than one RA instances
allOf:
- $ref: /schemas/arm/keystone/ti,k3-sci-common.yaml#
properties:
compatible:
items:
......@@ -54,14 +57,6 @@ properties:
$ref: /schemas/types.yaml#/definitions/uint32
description: TI-SCI RM subtype for GP ring range
ti,sci:
$ref: /schemas/types.yaml#/definitions/phandle-array
description: phandle on TI-SCI compatible System controller node
ti,sci-dev-id:
$ref: /schemas/types.yaml#/definitions/uint32
description: TI-SCI device id of the ring accelerator
required:
- compatible
- reg
......@@ -72,7 +67,7 @@ required:
- ti,sci
- ti,sci-dev-id
additionalProperties: false
unevaluatedProperties: false
examples:
- |
......
......@@ -26,6 +26,7 @@ properties:
- qcom,sdm845-imem
- qcom,sdx55-imem
- qcom,sdx65-imem
- qcom,sm8450-imem
- const: syscon
- const: simple-mfd
......
......@@ -46,14 +46,9 @@ examples:
- |
// The UniPhier thermal should be a subnode of a "syscon" compatible node.
sysctrl@61840000 {
compatible = "socionext,uniphier-ld20-sysctrl",
"simple-mfd", "syscon";
reg = <0x61840000 0x10000>;
pvtctl: thermal {
compatible = "socionext,uniphier-ld20-thermal";
interrupts = <0 3 1>;
#thermal-sensor-cells = <0>;
};
#include <dt-bindings/interrupt-controller/arm-gic.h>
pvtctl: thermal-sensor {
compatible = "socionext,uniphier-ld20-thermal";
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
#thermal-sensor-cells = <0>;
};
......@@ -74,6 +74,9 @@ properties:
minItems: 1
maxItems: 2
required-opps:
maxItems: 1
resets:
maxItems: 1
......
Fairchild FUSB302 Type-C Port controllers
Required properties :
- compatible : "fcs,fusb302"
- reg : I2C slave address
- interrupts : Interrupt specifier
Required sub-node:
- connector : The "usb-c-connector" attached to the FUSB302 IC. The bindings
of the connector node are specified in:
Documentation/devicetree/bindings/connector/usb-connector.yaml
Example:
fusb302: typec-portc@54 {
compatible = "fcs,fusb302";
reg = <0x54>;
interrupt-parent = <&nmi_intc>;
interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
usb_con: connector {
compatible = "usb-c-connector";
label = "USB-C";
power-role = "dual";
try-power-role = "sink";
source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)
PDO_VAR(3000, 12000, 3000)
PDO_PPS_APDO(3000, 11000, 3000)>;
op-sink-microwatt = <10000000>;
};
};
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/usb/fcs,fusb302.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Fairchild FUSB302 Type-C Port controller
maintainers:
- Rob Herring <robh@kernel.org>
properties:
compatible:
const: fcs,fusb302
reg:
maxItems: 1
interrupts:
maxItems: 1
vbus-supply:
description: VBUS power supply
connector:
type: object
$ref: /schemas/connector/usb-connector.yaml#
unevaluatedProperties: false
required:
- compatible
- reg
- interrupts
- vbus-supply
- connector
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/usb/pd.h>
i2c {
#address-cells = <1>;
#size-cells = <0>;
typec-portc@54 {
compatible = "fcs,fusb302";
reg = <0x54>;
interrupt-parent = <&nmi_intc>;
interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
vbus-supply = <&vbus_typec>;
connector {
compatible = "usb-c-connector";
label = "USB-C";
power-role = "dual";
try-power-role = "sink";
source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)
PDO_VAR(3000, 12000, 3000)
PDO_PPS_APDO(3000, 11000, 3000)>;
op-sink-microwatt = <10000000>;
};
};
};
......@@ -741,6 +741,8 @@ patternProperties:
description: Lichee Pi
"^linaro,.*":
description: Linaro Limited
"^lineartechnology,.*":
description: Linear Technology
"^linksprite,.*":
description: LinkSprite Technologies, Inc.
"^linksys,.*":
......
......@@ -8,6 +8,7 @@ title: Maxim 63xx Watchdog Timers
allOf:
- $ref: "watchdog.yaml#"
- $ref: /schemas/memory-controllers/mc-peripheral-props.yaml#
maintainers:
- Marc Zyngier <maz@kernel.org>
......
......@@ -25,12 +25,6 @@ examples:
- |
// The UniPhier watchdog should be a subnode of a "syscon" compatible node.
sysctrl@61840000 {
compatible = "socionext,uniphier-ld11-sysctrl",
"simple-mfd", "syscon";
reg = <0x61840000 0x10000>;
watchdog {
compatible = "socionext,uniphier-wdt";
};
watchdog {
compatible = "socionext,uniphier-wdt";
};
......@@ -2265,7 +2265,7 @@ M: Krzysztof Halasa <khalasa@piap.pl>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
S: Maintained
F: Documentation/devicetree/bindings/arm/intel-ixp4xx.yaml
F: Documentation/devicetree/bindings/bus/intel,ixp4xx-expansion-bus-controller.yaml
F: Documentation/devicetree/bindings/memory-controllers/intel,ixp4xx-expansion*
F: Documentation/devicetree/bindings/gpio/intel,ixp4xx-gpio.txt
F: Documentation/devicetree/bindings/interrupt-controller/intel,ixp4xx-interrupt.yaml
F: Documentation/devicetree/bindings/timer/intel,ixp4xx-timer.yaml
......@@ -2963,6 +2963,7 @@ S: Maintained
F: Documentation/devicetree/bindings/arm/socionext/uniphier.yaml
F: Documentation/devicetree/bindings/gpio/socionext,uniphier-gpio.yaml
F: Documentation/devicetree/bindings/pinctrl/socionext,uniphier-pinctrl.yaml
F: Documentation/devicetree/bindings/soc/socionext/socionext,uniphier*.yaml
F: arch/arm/boot/dts/uniphier*
F: arch/arm/include/asm/hardware/cache-uniphier.h
F: arch/arm/mach-uniphier/
......@@ -16270,7 +16271,7 @@ M: Shawn Lin <shawn.lin@rock-chips.com>
L: linux-pci@vger.kernel.org
L: linux-rockchip@lists.infradead.org
S: Maintained
F: Documentation/devicetree/bindings/pci/rockchip-pcie*
F: Documentation/devicetree/bindings/pci/rockchip,rk3399-pcie*
F: drivers/pci/controller/pcie-rockchip*
PCIE DRIVER FOR SOCIONEXT UNIPHIER
......@@ -19297,7 +19298,7 @@ SOCIONEXT SYNQUACER I2C DRIVER
M: Ard Biesheuvel <ardb@kernel.org>
L: linux-i2c@vger.kernel.org
S: Maintained
F: Documentation/devicetree/bindings/i2c/i2c-synquacer.txt
F: Documentation/devicetree/bindings/i2c/socionext,synquacer-i2c.yaml
F: drivers/i2c/busses/i2c-synquacer.c
SOCIONEXT UNIPHIER SOUND DRIVER
......
......@@ -1493,7 +1493,10 @@ dtbs_prepare: include/config/kernel.release scripts_dtc
ifneq ($(filter dtbs_check, $(MAKECMDGOALS)),)
export CHECK_DTBS=y
dtbs: dt_binding_check
endif
ifneq ($(CHECK_DTBS),)
dtbs_prepare: dt_binding_check
endif
dtbs_check: dtbs
......@@ -1792,6 +1795,10 @@ help:
@echo ' 3: more obscure warnings, can most likely be ignored'
@echo ' e: warnings are being treated as errors'
@echo ' Multiple levels can be combined with W=12 or W=123'
@$(if $(dtstree), \
echo ' make CHECK_DTBS=1 [targets] Check all generated dtb files against schema'; \
echo ' This can be applied both to "dtbs" and to individual "foo.dtb" targets' ; \
)
@echo ''
@echo 'Execute "make" or "make all" to build all targets marked with [*] '
@echo 'For further info see the ./README file'
......
......@@ -23,7 +23,19 @@ config OF_UNITTEST
that are executed once at boot time, and the results dumped to the
console.
If unsure, say N here, but this option is safe to enable.
This option should only be enabled for a development kernel. The tests
will taint the kernel with TAINT_TEST. The tests will cause ERROR and
WARNING messages to print on the console. The tests will cause stack
traces to print on the console. It is possible that the tests will
leave the devicetree in a corrupted state.
The unittest output will be verbose. Copy the output to a file
via capturing the console output or via the dmesg command. Process
this file with scripts/dtc/of_unittest_expect to reduce the
verbosity, test whether expected output is present, and to
summarize the results.
If unsure, say N here. This option is not safe to enable.
config OF_ALL_DTBS
bool "Build all Device Tree Blobs"
......
......@@ -1884,8 +1884,7 @@ static void of_alias_add(struct alias_prop *ap, struct device_node *np,
{
ap->np = np;
ap->id = id;
strncpy(ap->stem, stem, stem_len);
ap->stem[stem_len] = 0;
strscpy(ap->stem, stem, stem_len + 1);
list_add_tail(&ap->link, &aliases_lookup);
pr_debug("adding DT alias:%s: stem=%s id=%i node=%pOF\n",
ap->alias, ap->stem, ap->id, np);
......
......@@ -329,10 +329,30 @@ void of_node_release(struct kobject *kobj)
{
struct device_node *node = kobj_to_device_node(kobj);
/*
* can not use '"%pOF", node' in pr_err() calls from this function
* because an of_node_get(node) when refcount is already zero
* will result in an error and a stack dump
*/
/* We should never be releasing nodes that haven't been detached. */
if (!of_node_check_flag(node, OF_DETACHED)) {
pr_err("ERROR: Bad of_node_put() on %pOF\n", node);
dump_stack();
pr_err("ERROR: %s() detected bad of_node_put() on %pOF/%s\n",
__func__, node->parent, node->full_name);
/*
* of unittests will test this path. Do not print the stack
* trace when the error is caused by unittest so that we do
* not display what a normal developer might reasonably
* consider a real bug.
*/
if (!IS_ENABLED(CONFIG_OF_UNITTEST) ||
strcmp(node->parent->full_name, "testcase-data")) {
dump_stack();
pr_err("ERROR: next of_node_put() on this node will result in a kobject warning 'refcount_t: underflow; use-after-free.'\n");
}
return;
}
if (!of_node_check_flag(node, OF_DYNAMIC))
......@@ -357,6 +377,10 @@ void of_node_release(struct kobject *kobj)
__func__, node);
}
if (node->child)
pr_err("ERROR: %s() unexpected children for %pOF/%s\n",
__func__, node->parent, node->full_name);
property_list_free(node->properties);
property_list_free(node->deadprops);
fwnode_links_purge(of_fwnode_handle(node));
......@@ -419,7 +443,8 @@ struct property *__of_prop_dup(const struct property *prop, gfp_t allocflags)
* another node. The node data are dynamically allocated and all the node
* flags have the OF_DYNAMIC & OF_DETACHED bits set.
*
* Return: The newly allocated node or NULL on out of memory error.
* Return: The newly allocated node or NULL on out of memory error. Use
* of_node_put() on it when done to free the memory allocated for it.
*/
struct device_node *__of_node_dup(const struct device_node *np,
const char *full_name)
......
......@@ -438,10 +438,16 @@ int of_irq_get(struct device_node *dev, int index)
return rc;
domain = irq_find_host(oirq.np);
if (!domain)
return -EPROBE_DEFER;
if (!domain) {
rc = -EPROBE_DEFER;
goto out;
}
return irq_create_of_mapping(&oirq);
rc = irq_create_of_mapping(&oirq);
out:
of_node_put(oirq.np);
return rc;
}
EXPORT_SYMBOL_GPL(of_irq_get);
......
......@@ -24,7 +24,7 @@ static void of_node_release(struct kobject *kobj)
}
#endif /* CONFIG_OF_DYNAMIC */
struct kobj_type of_node_ktype = {
const struct kobj_type of_node_ktype = {
.release = of_node_release,
};
......
......@@ -285,6 +285,16 @@ void __init fdt_init_reserved_mem(void)
else
memblock_phys_free(rmem->base,
rmem->size);
} else {
phys_addr_t end = rmem->base + rmem->size - 1;
bool reusable =
(of_get_flat_dt_prop(node, "reusable", NULL)) != NULL;
pr_info("%pa..%pa (%lu KiB) %s %s %s\n",
&rmem->base, &end, (unsigned long)(rmem->size / SZ_1K),
nomap ? "nomap" : "map",
reusable ? "reusable" : "non-reusable",
rmem->name ? rmem->name : "unknown");
}
}
}
......
......@@ -1121,7 +1121,7 @@ static int node_overlaps_later_cs(struct overlay_changeset *remove_ovcs,
* The topmost check is done by exploiting this property. For each
* affected device node in the log list we check if this overlay is
* the one closest to the tail. If another overlay has affected this
* device node and is closest to the tail, then removal is not permited.
* device node and is closest to the tail, then removal is not permitted.
*/
static int overlay_removal_is_ok(struct overlay_changeset *remove_ovcs)
{
......
......@@ -222,7 +222,6 @@ static struct amba_device *of_amba_device_create(struct device_node *node,
struct device *parent)
{
struct amba_device *dev;
const void *prop;
int ret;
pr_debug("Creating amba device %pOF\n", node);
......@@ -250,9 +249,7 @@ static struct amba_device *of_amba_device_create(struct device_node *node,
of_device_make_bus_id(&dev->dev);
/* Allow the HW Peripheral ID to be overridden */
prop = of_get_property(node, "arm,primecell-periphid", NULL);
if (prop)
dev->periphid = of_read_ulong(prop, 1);
of_property_read_u32(node, "arm,primecell-periphid", &dev->periphid);
ret = of_address_to_resource(node, 0, &dev->res);
if (ret) {
......@@ -529,7 +526,7 @@ static int __init of_platform_default_populate_init(void)
int ret;
/* Check if we have a MacOS display without a node spec */
if (of_get_property(of_chosen, "linux,bootx-noscreen", NULL)) {
if (of_property_present(of_chosen, "linux,bootx-noscreen")) {
/*
* The old code tried to work out which node was the MacOS
* display based on the address. I'm dropping that since the
......
......@@ -1072,7 +1072,7 @@ static struct device_node *of_get_compat_node(struct device_node *np)
np = NULL;
}
if (of_find_property(np, "compatible", NULL))
if (of_property_present(np, "compatible"))
break;
np = of_get_next_parent(np);
......@@ -1300,7 +1300,7 @@ static struct device_node *parse_gpio_compat(struct device_node *np,
* Ignore node with gpio-hog property since its gpios are all provided
* by its parent.
*/
if (of_find_property(np, "gpio-hog", NULL))
if (of_property_read_bool(np, "gpio-hog"))
return NULL;
if (of_parse_phandle_with_args(np, prop_name, "#gpio-cells", index,
......
......@@ -17,3 +17,4 @@ node-remove {
#include "tests-address.dtsi"
#include "tests-platform.dtsi"
#include "tests-overlay.dtsi"
#include "tests-lifecycle.dtsi"
// SPDX-License-Identifier: GPL-2.0
/ {
testcase-data {
refcount-node {
};
};
};
......@@ -54,8 +54,9 @@ static struct unittest_results {
* Print the expected message only if the current loglevel will allow
* the actual message to print.
*
* Do not use EXPECT_BEGIN() or EXPECT_END() for messages generated by
* pr_debug().
* Do not use EXPECT_BEGIN(), EXPECT_END(), EXPECT_NOT_BEGIN(), or
* EXPECT_NOT_END() to report messages expected to be reported or not
* reported by pr_debug().
*/
#define EXPECT_BEGIN(level, fmt, ...) \
printk(level pr_fmt("EXPECT \\ : ") fmt, ##__VA_ARGS__)
......@@ -63,6 +64,12 @@ static struct unittest_results {
#define EXPECT_END(level, fmt, ...) \
printk(level pr_fmt("EXPECT / : ") fmt, ##__VA_ARGS__)
#define EXPECT_NOT_BEGIN(level, fmt, ...) \
printk(level pr_fmt("EXPECT_NOT \\ : ") fmt, ##__VA_ARGS__)
#define EXPECT_NOT_END(level, fmt, ...) \
printk(level pr_fmt("EXPECT_NOT / : ") fmt, ##__VA_ARGS__)
static void __init of_unittest_find_node_by_name(void)
{
struct device_node *np;
......@@ -1488,6 +1495,7 @@ static int __init unittest_data_add(void)
struct device_node *next = np->sibling;
np->parent = of_root;
/* this will clear OF_DETACHED in np and children */
attach_node_and_children(np);
np = next;
}
......@@ -2998,6 +3006,143 @@ static void __init of_unittest_overlay(void)
static inline void __init of_unittest_overlay(void) { }
#endif
static void __init of_unittest_lifecycle(void)
{
#ifdef CONFIG_OF_DYNAMIC
unsigned int refcount;
int found_refcount_one = 0;
int put_count = 0;
struct device_node *np;
struct device_node *prev_sibling, *next_sibling;
const char *refcount_path = "/testcase-data/refcount-node";
const char *refcount_parent_path = "/testcase-data";
/*
* Node lifecycle tests, non-dynamic node:
*
* - Decrementing refcount to zero via of_node_put() should cause the
* attempt to free the node memory by of_node_release() to fail
* because the node is not a dynamic node.
*
* - Decrementing refcount past zero should result in additional
* errors reported.
*/
np = of_find_node_by_path(refcount_path);
unittest(np, "find refcount_path \"%s\"\n", refcount_path);
if (np == NULL)
goto out_skip_tests;
while (!found_refcount_one) {
if (put_count++ > 10) {
unittest(0, "guardrail to avoid infinite loop\n");
goto out_skip_tests;
}
refcount = kref_read(&np->kobj.kref);
if (refcount == 1)
found_refcount_one = 1;
else
of_node_put(np);
}
EXPECT_BEGIN(KERN_INFO, "OF: ERROR: of_node_release() detected bad of_node_put() on /testcase-data/refcount-node");
/*
* refcount is now one, decrementing to zero will result in a call to
* of_node_release() to free the node's memory, which should result
* in an error
*/
unittest(1, "/testcase-data/refcount-node is one");
of_node_put(np);
EXPECT_END(KERN_INFO, "OF: ERROR: of_node_release() detected bad of_node_put() on /testcase-data/refcount-node");
/*
* expect stack trace for subsequent of_node_put():
* __refcount_sub_and_test() calls:
* refcount_warn_saturate(r, REFCOUNT_SUB_UAF)
*
* Not capturing entire WARN_ONCE() trace with EXPECT_*(), just
* the first three lines, and the last line.
*/
EXPECT_BEGIN(KERN_INFO, "------------[ cut here ]------------");
EXPECT_BEGIN(KERN_INFO, "WARNING: <<all>>");
EXPECT_BEGIN(KERN_INFO, "refcount_t: underflow; use-after-free.");
EXPECT_BEGIN(KERN_INFO, "---[ end trace <<int>> ]---");
/* refcount is now zero, this should fail */
unittest(1, "/testcase-data/refcount-node is zero");
of_node_put(np);
EXPECT_END(KERN_INFO, "---[ end trace <<int>> ]---");
EXPECT_END(KERN_INFO, "refcount_t: underflow; use-after-free.");
EXPECT_END(KERN_INFO, "WARNING: <<all>>");
EXPECT_END(KERN_INFO, "------------[ cut here ]------------");
/*
* Q. do we expect to get yet another warning?
* A. no, the WARNING is from WARN_ONCE()
*/
EXPECT_NOT_BEGIN(KERN_INFO, "------------[ cut here ]------------");
EXPECT_NOT_BEGIN(KERN_INFO, "WARNING: <<all>>");
EXPECT_NOT_BEGIN(KERN_INFO, "refcount_t: underflow; use-after-free.");
EXPECT_NOT_BEGIN(KERN_INFO, "---[ end trace <<int>> ]---");
unittest(1, "/testcase-data/refcount-node is zero, second time");
of_node_put(np);
EXPECT_NOT_END(KERN_INFO, "---[ end trace <<int>> ]---");
EXPECT_NOT_END(KERN_INFO, "refcount_t: underflow; use-after-free.");
EXPECT_NOT_END(KERN_INFO, "WARNING: <<all>>");
EXPECT_NOT_END(KERN_INFO, "------------[ cut here ]------------");
/*
* refcount of zero will trigger stack traces from any further
* attempt to of_node_get() node "refcount-node". One example of
* this is where of_unittest_check_node_linkage() will recursively
* scan the tree, with 'for_each_child_of_node()' doing an
* of_node_get() of the children of a node.
*
* Prevent the stack trace by removing node "refcount-node" from
* its parent's child list.
*
* WARNING: EVIL, EVIL, EVIL:
*
* Directly manipulate the child list of node /testcase-data to
* remove child refcount-node. This is ignoring all proper methods
* of removing a child and will leak a small amount of memory.
*/
np = of_find_node_by_path(refcount_parent_path);
unittest(np, "find refcount_parent_path \"%s\"\n", refcount_parent_path);
unittest(np, "ERROR: devicetree live tree left in a 'bad state' if test fail\n");
if (np == NULL)
return;
prev_sibling = np->child;
next_sibling = prev_sibling->sibling;
if (!strcmp(prev_sibling->full_name, "refcount-node")) {
np->child = next_sibling;
next_sibling = next_sibling->sibling;
}
while (next_sibling) {
if (!strcmp(next_sibling->full_name, "refcount-node"))
prev_sibling->sibling = next_sibling->sibling;
prev_sibling = next_sibling;
next_sibling = next_sibling->sibling;
}
of_node_put(np);
return;
out_skip_tests:
#endif
unittest(0, "One or more lifecycle tests skipped\n");
}
#ifdef CONFIG_OF_OVERLAY
/*
......@@ -3502,6 +3647,7 @@ static int __init of_unittest(void)
of_unittest_match_node();
of_unittest_platform_populate();
of_unittest_overlay();
of_unittest_lifecycle();
/* Double check linkage after removing testcase data */
of_unittest_check_tree_linkage();
......
/* SPDX-License-Identifier: GPL-2.0 */
/* SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) */
/*
* This header provides constants for most GPIO bindings.
*
......
......@@ -100,8 +100,19 @@ struct of_reconfig_data {
struct property *old_prop;
};
/**
* of_node_init - initialize a devicetree node
* @node: Pointer to device node that has been created by kzalloc()
* @phandle_name: Name of property holding a phandle value
*
* On return the device_node refcount is set to one. Use of_node_put()
* on @node when done to free the memory allocated for it. If the node
* is NOT a dynamic node the memory will not be freed. The decision of
* whether to free the memory will be done by node->release(), which is
* of_node_release().
*/
/* initialize a node */
extern struct kobj_type of_node_ktype;
extern const struct kobj_type of_node_ktype;
extern const struct fwnode_operations of_fwnode_ops;
static inline void of_node_init(struct device_node *node)
{
......@@ -1180,7 +1191,8 @@ static inline int of_property_read_string_index(const struct device_node *np,
* @np: device node from which the property value is to be read.
* @propname: name of the property to be searched.
*
* Search for a property in a device node.
* Search for a boolean property in a device node. Usage on non-boolean
* property types is deprecated.
*
* Return: true if the property exists false otherwise.
*/
......@@ -1192,6 +1204,20 @@ static inline bool of_property_read_bool(const struct device_node *np,
return prop ? true : false;
}
/**
* of_property_present - Test if a property is present in a node
* @np: device node to search for the property.
* @propname: name of the property to be searched.
*
* Test for a property present in a device node.
*
* Return: true if the property exists false otherwise.
*/
static inline bool of_property_present(const struct device_node *np, const char *propname)
{
return of_property_read_bool(np, propname);
}
/**
* of_property_read_u8_array - Find and read an array of u8 from a property.
*
......
......@@ -404,9 +404,14 @@ arrayprefix:
* within the mask to one (i.e. | in the
* mask), all bits are one.
*/
if (($2 > mask) && (($2 | mask) != -1ULL))
ERROR(&@2, "Value out of range for"
" %d-bit array element", $1.bits);
if (($2 > mask) && (($2 | mask) != -1ULL)) {
char *loc = srcpos_string(&@2);
fprintf(stderr,
"WARNING: %s: Value 0x%016" PRIx64
" truncated to 0x%0*" PRIx64 "\n",
loc, $2, $1.bits / 4, ($2 & mask));
free(loc);
}
}
$$.data = data_append_integer($1.data, $2, $1.bits);
......
......@@ -35,14 +35,14 @@ struct fdt_reserve_entry {
struct fdt_node_header {
fdt32_t tag;
char name[0];
char name[];
};
struct fdt_property {
fdt32_t tag;
fdt32_t len;
fdt32_t nameoff;
char data[0];
char data[];
};
#endif /* !__ASSEMBLY */
......
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