Commit 83aa3c45 authored by Dave Hansen's avatar Dave Hansen Committed by Ingo Molnar

x86/fpu: Rework YMM definition

We are about to rework all of the "extended state" definitions.
This makes the 'ymm' naming consistent with the AVX-512 types
we will introduce later.

We also add a convenience type: "reg_128_bit" so that we do
not have to spell out our arithmetic.
Signed-off-by: default avatarDave Hansen <dave.hansen@linux.intel.com>
Cc: Andy Lutomirski <luto@amacapital.net>
Cc: Borislav Petkov <bp@alien8.de>
Cc: Brian Gerst <brgerst@gmail.com>
Cc: Denys Vlasenko <dvlasenk@redhat.com>
Cc: Fenghua Yu <fenghua.yu@intel.com>
Cc: H. Peter Anvin <hpa@zytor.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Tim Chen <tim.c.chen@linux.intel.com>
Cc: dave@sr71.net
Cc: linux-kernel@vger.kernel.org
Link: http://lkml.kernel.org/r/20150902233129.B4EB045F@viggo.jf.intel.comSigned-off-by: default avatarIngo Molnar <mingo@kernel.org>
parent 1126cb45
...@@ -128,17 +128,23 @@ enum xfeature { ...@@ -128,17 +128,23 @@ enum xfeature {
#define FIRST_EXTENDED_XFEATURE XFEATURE_YMM #define FIRST_EXTENDED_XFEATURE XFEATURE_YMM
struct reg_128_bit {
u8 regbytes[128/8];
};
/* /*
* State component 2:
*
* There are 16x 256-bit AVX registers named YMM0-YMM15. * There are 16x 256-bit AVX registers named YMM0-YMM15.
* The low 128 bits are aliased to the 16 SSE registers (XMM0-XMM15) * The low 128 bits are aliased to the 16 SSE registers (XMM0-XMM15)
* and are stored in 'struct fxregs_state::xmm_space[]'. * and are stored in 'struct fxregs_state::xmm_space[]' in the
* "legacy" area.
* *
* The high 128 bits are stored here: * The high 128 bits are stored here.
* 16x 128 bits == 256 bytes.
*/ */
struct ymmh_struct { struct ymmh_struct {
u8 ymmh_space[256]; struct reg_128_bit hi_ymm[16];
}; } __packed;
/* Intel MPX support: */ /* Intel MPX support: */
......
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