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Commit 83b7f0b8 authored by Dmitry Osipenko's avatar Dmitry Osipenko Committed by Thierry Reding
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ARM: tegra: Add OPP tables and power domains to Tegra20 device-trees 

Add OPP tables and power domains to all peripheral devices which
support power management on Tegra20 SoC.

Tested-by: Paul Fertser <fercerpav@gmail.com> # PAZ00 T20
Tested-by: Nicolas Chauvet <kwizart@gmail.com> # PAZ00 T20
Signed-off-by: default avatarDmitry Osipenko <digetx@gmail.com>
Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
parent 3478494d
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Showing with 1033 additions and 5 deletions
arch/arm/boot/dts/tegra20-acer-a500-picasso.dts
View file @ 83b7f0b8
......@@ -718,6 +718,7 @@ pmc@7000e400 {
nvidia,core-pwr-good-time = <3845 3845>;
nvidia,core-pwr-off-time = <458>;
nvidia,sys-clock-req-active-high;
core-supply = <&vdd_core>;
};
usb@c5000000 {
......
arch/arm/boot/dts/tegra20-colibri.dtsi
View file @ 83b7f0b8
......@@ -497,7 +497,7 @@ reg_3v3_vsys: sys {
regulator-always-on;
};
sm0 {
vdd_core: sm0 {
regulator-name = "VDD_CORE_1.2V";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
......@@ -603,6 +603,7 @@ pmc@7000e400 {
nvidia,core-pwr-good-time = <3845 3845>;
nvidia,core-pwr-off-time = <3875>;
nvidia,sys-clock-req-active-high;
core-supply = <&vdd_core>;
/* Set SLEEP MODE bit in SUPPLYENE register of TPS658643 PMIC */
i2c-thermtrip {
......
arch/arm/boot/dts/tegra20-harmony.dts
View file @ 83b7f0b8
......@@ -339,7 +339,7 @@ sys_reg: sys {
regulator-always-on;
};
sm0 {
vdd_core: sm0 {
regulator-name = "vdd_sm0,vdd_core";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
......@@ -565,6 +565,7 @@ pmc@7000e400 {
nvidia,core-pwr-good-time = <3845 3845>;
nvidia,core-pwr-off-time = <3875>;
nvidia,sys-clock-req-active-high;
core-supply = <&vdd_core>;
};
pcie@80003000 {
......
arch/arm/boot/dts/tegra20-paz00.dts
View file @ 83b7f0b8
......@@ -519,6 +519,7 @@ pmc@7000e400 {
nvidia,core-pwr-good-time = <3845 3845>;
nvidia,core-pwr-off-time = <0>;
nvidia,sys-clock-req-active-high;
core-supply = <&core_vdd_reg>;
};
usb@c5000000 {
......
arch/arm/boot/dts/tegra20-seaboard.dts
View file @ 83b7f0b8
......@@ -444,7 +444,7 @@ sys_reg: sys {
regulator-always-on;
};
sm0 {
vdd_core: sm0 {
regulator-name = "vdd_sm0,vdd_core";
regulator-min-microvolt = <1300000>;
regulator-max-microvolt = <1300000>;
......@@ -689,6 +689,7 @@ pmc@7000e400 {
nvidia,core-pwr-good-time = <3845 3845>;
nvidia,core-pwr-off-time = <3875>;
nvidia,sys-clock-req-active-high;
core-supply = <&vdd_core>;
};
memory-controller@7000f400 {
......
arch/arm/boot/dts/tegra20-tamonten.dtsi
View file @ 83b7f0b8
......@@ -357,7 +357,7 @@ sys_reg: sys {
regulator-always-on;
};
sm0 {
vdd_core: sm0 {
regulator-name = "vdd_sys_sm0,vdd_core";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
......@@ -477,6 +477,7 @@ pmc@7000e400 {
nvidia,core-pwr-good-time = <3845 3845>;
nvidia,core-pwr-off-time = <3875>;
nvidia,sys-clock-req-active-high;
core-supply = <&vdd_core>;
};
pcie@80003000 {
......
arch/arm/boot/dts/tegra20-trimslice.dts
View file @ 83b7f0b8
......@@ -322,6 +322,7 @@ pmc@7000e400 {
nvidia,core-pwr-good-time = <3845 3845>;
nvidia,core-pwr-off-time = <3875>;
nvidia,sys-clock-req-active-high;
core-supply = <&vdd_core>;
};
pcie@80003000 {
......@@ -443,6 +444,14 @@ pci_vdd_reg: regulator-pcivdd {
regulator-always-on;
};
vdd_core: regulator-core {
compatible = "regulator-fixed";
regulator-name = "vdd_core";
regulator-min-microvolt = <1300000>;
regulator-max-microvolt = <1300000>;
regulator-always-on;
};
sound {
compatible = "nvidia,tegra-audio-trimslice";
nvidia,i2s-controller = <&tegra_i2s1>;
......
arch/arm/boot/dts/tegra20-ventana.dts
View file @ 83b7f0b8
......@@ -544,6 +544,7 @@ pmc@7000e400 {
nvidia,core-pwr-good-time = <3845 3845>;
nvidia,core-pwr-off-time = <458>;
nvidia,sys-clock-req-active-high;
core-supply = <&vdd_core>;
};
usb@c5000000 {
......
arch/arm/boot/dts/tegra20.dtsi
View file @ 83b7f0b8
......@@ -42,6 +42,8 @@ host1x@50000000 {
clock-names = "host1x";
resets = <&tegra_car 28>;
reset-names = "host1x";
power-domains = <&pd_core>;
operating-points-v2 = <&host1x_dvfs_opp_table>;
#address-cells = <1>;
#size-cells = <1>;
......@@ -55,6 +57,8 @@ mpe@54040000 {
clocks = <&tegra_car TEGRA20_CLK_MPE>;
resets = <&tegra_car 60>;
reset-names = "mpe";
power-domains = <&pd_mpe>;
operating-points-v2 = <&mpe_dvfs_opp_table>;
};
vi@54080000 {
......@@ -64,6 +68,8 @@ vi@54080000 {
clocks = <&tegra_car TEGRA20_CLK_VI>;
resets = <&tegra_car 20>;
reset-names = "vi";
power-domains = <&pd_venc>;
operating-points-v2 = <&vi_dvfs_opp_table>;
};
epp@540c0000 {
......@@ -73,6 +79,8 @@ epp@540c0000 {
clocks = <&tegra_car TEGRA20_CLK_EPP>;
resets = <&tegra_car 19>;
reset-names = "epp";
power-domains = <&pd_core>;
operating-points-v2 = <&epp_dvfs_opp_table>;
};
isp@54100000 {
......@@ -82,6 +90,7 @@ isp@54100000 {
clocks = <&tegra_car TEGRA20_CLK_ISP>;
resets = <&tegra_car 23>;
reset-names = "isp";
power-domains = <&pd_venc>;
};
gr2d@54140000 {
......@@ -91,6 +100,8 @@ gr2d@54140000 {
clocks = <&tegra_car TEGRA20_CLK_GR2D>;
resets = <&tegra_car 21>;
reset-names = "2d";
power-domains = <&pd_core>;
operating-points-v2 = <&gr2d_dvfs_opp_table>;
};
gr3d@54180000 {
......@@ -99,6 +110,8 @@ gr3d@54180000 {
clocks = <&tegra_car TEGRA20_CLK_GR3D>;
resets = <&tegra_car 24>;
reset-names = "3d";
power-domains = <&pd_3d>;
operating-points-v2 = <&gr3d_dvfs_opp_table>;
};
dc@54200000 {
......@@ -110,6 +123,8 @@ dc@54200000 {
clock-names = "dc", "parent";
resets = <&tegra_car 27>;
reset-names = "dc";
power-domains = <&pd_core>;
operating-points-v2 = <&disp1_dvfs_opp_table>;
nvidia,head = <0>;
......@@ -138,6 +153,8 @@ dc@54240000 {
clock-names = "dc", "parent";
resets = <&tegra_car 26>;
reset-names = "dc";
power-domains = <&pd_core>;
operating-points-v2 = <&disp2_dvfs_opp_table>;
nvidia,head = <1>;
......@@ -166,6 +183,8 @@ hdmi@54280000 {
clock-names = "hdmi", "parent";
resets = <&tegra_car 51>;
reset-names = "hdmi";
power-domains = <&pd_core>;
operating-points-v2 = <&hdmi_dvfs_opp_table>;
status = "disabled";
};
......@@ -174,6 +193,8 @@ tvo@542c0000 {
reg = <0x542c0000 0x00040000>;
interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA20_CLK_TVO>;
power-domains = <&pd_core>;
operating-points-v2 = <&tvo_dvfs_opp_table>;
status = "disabled";
};
......@@ -185,6 +206,8 @@ dsi@54300000 {
clock-names = "dsi", "parent";
resets = <&tegra_car 48>;
reset-names = "dsi";
power-domains = <&pd_core>;
operating-points-v2 = <&dsi_dvfs_opp_table>;
status = "disabled";
};
};
......@@ -242,6 +265,13 @@ tegra_car: clock@60006000 {
reg = <0x60006000 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
sclk {
compatible = "nvidia,tegra20-sclk";
clocks = <&tegra_car TEGRA20_CLK_SCLK>;
power-domains = <&pd_core>;
operating-points-v2 = <&sclk_dvfs_opp_table>;
};
};
flow-controller@60007000 {
......@@ -319,6 +349,8 @@ vde@6001a000 {
clocks = <&tegra_car TEGRA20_CLK_VDE>;
reset-names = "vde", "mc";
resets = <&tegra_car 61>, <&mc TEGRA20_MC_RESET_VDE>;
power-domains = <&pd_vde>;
operating-points-v2 = <&vde_dvfs_opp_table>;
};
apbmisc@70000800 {
......@@ -460,6 +492,8 @@ nand-controller@70008000 {
reset-names = "nand";
assigned-clocks = <&tegra_car TEGRA20_CLK_NDFLASH>;
assigned-clock-rates = <150000000>;
power-domains = <&pd_core>;
operating-points-v2 = <&ndflash_dvfs_opp_table>;
status = "disabled";
};
......@@ -473,6 +507,8 @@ gmi@70009000 {
clock-names = "gmi";
resets = <&tegra_car 42>;
reset-names = "gmi";
power-domains = <&pd_core>;
operating-points-v2 = <&nor_dvfs_opp_table>;
status = "disabled";
};
......@@ -643,6 +679,52 @@ tegra_pmc: pmc@7000e400 {
clocks = <&tegra_car TEGRA20_CLK_PCLK>, <&clk32k_in>;
clock-names = "pclk", "clk32k_in";
#clock-cells = <1>;
pd_core: core-domain {
#power-domain-cells = <0>;
operating-points-v2 = <&core_opp_table>;
};
powergates {
pd_3d: td {
clocks = <&tegra_car TEGRA20_CLK_GR3D>;
resets = <&mc TEGRA20_MC_RESET_3D>,
<&tegra_car TEGRA20_CLK_GR3D>;
power-domains = <&pd_core>;
#power-domain-cells = <0>;
};
pd_venc: venc {
clocks = <&tegra_car TEGRA20_CLK_ISP>,
<&tegra_car TEGRA20_CLK_VI>,
<&tegra_car TEGRA20_CLK_CSI>;
resets = <&mc TEGRA20_MC_RESET_ISP>,
<&mc TEGRA20_MC_RESET_VI>,
<&tegra_car TEGRA20_CLK_ISP>,
<&tegra_car 20 /* VI */>,
<&tegra_car TEGRA20_CLK_CSI>;
power-domains = <&pd_core>;
#power-domain-cells = <0>;
};
pd_vde: vdec {
clocks = <&tegra_car TEGRA20_CLK_VDE>;
resets = <&mc TEGRA20_MC_RESET_VDE>,
<&tegra_car TEGRA20_CLK_VDE>;
power-domains = <&pd_core>;
#power-domain-cells = <0>;
};
pd_mpe: mpe {
clocks = <&tegra_car TEGRA20_CLK_MPE>;
resets = <&mc TEGRA20_MC_RESET_MPEA>,
<&mc TEGRA20_MC_RESET_MPEB>,
<&mc TEGRA20_MC_RESET_MPEC>,
<&tegra_car TEGRA20_CLK_MPE>;
power-domains = <&pd_core>;
#power-domain-cells = <0>;
};
};
};
mc: memory-controller@7000f000 {
......@@ -662,12 +744,13 @@ emc: memory-controller@7000f400 {
reg = <0x7000f400 0x400>;
interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA20_CLK_EMC>;
power-domains = <&pd_core>;
#address-cells = <1>;
#size-cells = <0>;
#interconnect-cells = <0>;
operating-points-v2 = <&emc_icc_dvfs_opp_table>;
nvidia,memory-controller = <&mc>;
operating-points-v2 = <&emc_icc_dvfs_opp_table>;
};
fuse@7000f800 {
......@@ -712,6 +795,9 @@ pcie@80003000 {
<&tegra_car 72>,
<&tegra_car 74>;
reset-names = "pex", "afi", "pcie_x";
power-domains = <&pd_core>;
operating-points-v2 = <&pcie_dvfs_opp_table>;
status = "disabled";
pci@1,0 {
......@@ -753,6 +839,8 @@ usb@c5000000 {
reset-names = "usb";
nvidia,needs-double-reset;
nvidia,phy = <&phy1>;
power-domains = <&pd_core>;
operating-points-v2 = <&usbd_dvfs_opp_table>;
status = "disabled";
};
......@@ -792,6 +880,8 @@ usb@c5004000 {
resets = <&tegra_car 58>;
reset-names = "usb";
nvidia,phy = <&phy2>;
power-domains = <&pd_core>;
operating-points-v2 = <&usb2_dvfs_opp_table>;
status = "disabled";
};
......@@ -820,6 +910,8 @@ usb@c5008000 {
resets = <&tegra_car 59>;
reset-names = "usb";
nvidia,phy = <&phy3>;
power-domains = <&pd_core>;
operating-points-v2 = <&usb3_dvfs_opp_table>;
status = "disabled";
};
......@@ -856,6 +948,8 @@ mmc@c8000000 {
clock-names = "sdhci";
resets = <&tegra_car 14>;
reset-names = "sdhci";
power-domains = <&pd_core>;
operating-points-v2 = <&sdmmc1_dvfs_opp_table>;
status = "disabled";
};
......@@ -867,6 +961,8 @@ mmc@c8000200 {
clock-names = "sdhci";
resets = <&tegra_car 9>;
reset-names = "sdhci";
power-domains = <&pd_core>;
operating-points-v2 = <&sdmmc2_dvfs_opp_table>;
status = "disabled";
};
......@@ -878,6 +974,8 @@ mmc@c8000400 {
clock-names = "sdhci";
resets = <&tegra_car 69>;
reset-names = "sdhci";
power-domains = <&pd_core>;
operating-points-v2 = <&sdmmc3_dvfs_opp_table>;
status = "disabled";
};
......@@ -889,6 +987,8 @@ mmc@c8000600 {
clock-names = "sdhci";
resets = <&tegra_car 15>;
reset-names = "sdhci";
power-domains = <&pd_core>;
operating-points-v2 = <&sdmmc4_dvfs_opp_table>;
status = "disabled";
};
......
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