Commit 849ee6ac authored by Lorenzo Bianconi's avatar Lorenzo Bianconi Committed by Felix Fietkau

mt76: mt7921: fix mt7921_queues_acq implementation

Fix mt7921_queues_acq implementation according to the vendor sdk.

Fixes: 474a9f21 ("mt76: mt7921: add debugfs support")
Signed-off-by: default avatarLorenzo Bianconi <lorenzo@kernel.org>
Signed-off-by: default avatarFelix Fietkau <nbd@nbd.name>
parent e907341d
...@@ -129,23 +129,22 @@ mt7921_queues_acq(struct seq_file *s, void *data) ...@@ -129,23 +129,22 @@ mt7921_queues_acq(struct seq_file *s, void *data)
mt7921_mutex_acquire(dev); mt7921_mutex_acquire(dev);
for (i = 0; i < 16; i++) { for (i = 0; i < 4; i++) {
int j, acs = i / 4, index = i % 4;
u32 ctrl, val, qlen = 0; u32 ctrl, val, qlen = 0;
int j;
val = mt76_rr(dev, MT_PLE_AC_QEMPTY(acs, index)); val = mt76_rr(dev, MT_PLE_AC_QEMPTY(i));
ctrl = BIT(31) | BIT(15) | (acs << 8); ctrl = BIT(31) | BIT(11) | (i << 24);
for (j = 0; j < 32; j++) { for (j = 0; j < 32; j++) {
if (val & BIT(j)) if (val & BIT(j))
continue; continue;
mt76_wr(dev, MT_PLE_FL_Q0_CTRL, mt76_wr(dev, MT_PLE_FL_Q0_CTRL, ctrl | j);
ctrl | (j + (index << 5)));
qlen += mt76_get_field(dev, MT_PLE_FL_Q3_CTRL, qlen += mt76_get_field(dev, MT_PLE_FL_Q3_CTRL,
GENMASK(11, 0)); GENMASK(11, 0));
} }
seq_printf(s, "AC%d%d: queued=%d\n", acs, index, qlen); seq_printf(s, "AC%d: queued=%d\n", i, qlen);
} }
mt7921_mutex_release(dev); mt7921_mutex_release(dev);
......
...@@ -17,13 +17,12 @@ ...@@ -17,13 +17,12 @@
#define MT_PLE_BASE 0x820c0000 #define MT_PLE_BASE 0x820c0000
#define MT_PLE(ofs) (MT_PLE_BASE + (ofs)) #define MT_PLE(ofs) (MT_PLE_BASE + (ofs))
#define MT_PLE_FL_Q0_CTRL MT_PLE(0x1b0) #define MT_PLE_FL_Q0_CTRL MT_PLE(0x3e0)
#define MT_PLE_FL_Q1_CTRL MT_PLE(0x1b4) #define MT_PLE_FL_Q1_CTRL MT_PLE(0x3e4)
#define MT_PLE_FL_Q2_CTRL MT_PLE(0x1b8) #define MT_PLE_FL_Q2_CTRL MT_PLE(0x3e8)
#define MT_PLE_FL_Q3_CTRL MT_PLE(0x1bc) #define MT_PLE_FL_Q3_CTRL MT_PLE(0x3ec)
#define MT_PLE_AC_QEMPTY(ac, n) MT_PLE(0x300 + 0x10 * (ac) + \ #define MT_PLE_AC_QEMPTY(_n) MT_PLE(0x500 + 0x40 * (_n))
((n) << 2))
#define MT_PLE_AMSDU_PACK_MSDU_CNT(n) MT_PLE(0x10e0 + ((n) << 2)) #define MT_PLE_AMSDU_PACK_MSDU_CNT(n) MT_PLE(0x10e0 + ((n) << 2))
#define MT_MDP_BASE 0x820cd000 #define MT_MDP_BASE 0x820cd000
......
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