Commit 84e1b0e6 authored by Daniel Vetter's avatar Daniel Vetter Committed by Ben Hutchings

drm/i915: Do no set Stencil Cache eviction LRA w/a on gen7+

commit 2e7a4481 upstream.

I've flagged this while reviewing the first version and Ken Graunke
fixed it up in v2, but unfortunately Dave Airlie picked up the wrong
version.

Cc: Dave Airlie <airlied@redhat.com>
Cc: Kenneth Graunke <kenneth@whitecape.org>
Signed-Off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: default avatarBen Hutchings <ben@decadent.org.uk>
parent 071d3744
...@@ -414,10 +414,8 @@ static int init_render_ring(struct intel_ring_buffer *ring) ...@@ -414,10 +414,8 @@ static int init_render_ring(struct intel_ring_buffer *ring)
return ret; return ret;
} }
if (INTEL_INFO(dev)->gen >= 6) {
I915_WRITE(INSTPM,
INSTPM_FORCE_ORDERING << 16 | INSTPM_FORCE_ORDERING);
if (IS_GEN6(dev)) {
/* From the Sandybridge PRM, volume 1 part 3, page 24: /* From the Sandybridge PRM, volume 1 part 3, page 24:
* "If this bit is set, STCunit will have LRA as replacement * "If this bit is set, STCunit will have LRA as replacement
* policy. [...] This bit must be reset. LRA replacement * policy. [...] This bit must be reset. LRA replacement
...@@ -427,6 +425,11 @@ static int init_render_ring(struct intel_ring_buffer *ring) ...@@ -427,6 +425,11 @@ static int init_render_ring(struct intel_ring_buffer *ring)
CM0_STC_EVICT_DISABLE_LRA_SNB << CM0_MASK_SHIFT); CM0_STC_EVICT_DISABLE_LRA_SNB << CM0_MASK_SHIFT);
} }
if (INTEL_INFO(dev)->gen >= 6) {
I915_WRITE(INSTPM,
INSTPM_FORCE_ORDERING << 16 | INSTPM_FORCE_ORDERING);
}
return ret; return ret;
} }
......
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