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Kirill Smelkov
linux
Commits
885d21e4
Commit
885d21e4
authored
Jan 23, 2020
by
Tony Lindgren
Browse files
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Merge branch 'omap-for-v5.6/ti-sysc-omap45-rng' into omap-for-v5.6/ti-sysc-drop-pdata
parents
a25e29bd
ddf664da
Changes
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21 changed files
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426 additions
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196 deletions
+426
-196
Documentation/devicetree/bindings/clock/ti-clkctrl.txt
Documentation/devicetree/bindings/clock/ti-clkctrl.txt
+8
-3
Documentation/devicetree/bindings/clock/ti/dra7-atl.txt
Documentation/devicetree/bindings/clock/ti/dra7-atl.txt
+2
-2
arch/arm/boot/dts/dra7-evm-common.dtsi
arch/arm/boot/dts/dra7-evm-common.dtsi
+1
-1
arch/arm/boot/dts/dra72-evm-common.dtsi
arch/arm/boot/dts/dra72-evm-common.dtsi
+1
-1
arch/arm/boot/dts/dra7xx-clocks.dtsi
arch/arm/boot/dts/dra7xx-clocks.dtsi
+14
-0
arch/arm/boot/dts/motorola-mapphone-common.dtsi
arch/arm/boot/dts/motorola-mapphone-common.dtsi
+5
-0
arch/arm/boot/dts/omap4-l4.dtsi
arch/arm/boot/dts/omap4-l4.dtsi
+46
-3
arch/arm/boot/dts/omap4.dtsi
arch/arm/boot/dts/omap4.dtsi
+80
-30
arch/arm/boot/dts/omap44xx-clocks.dtsi
arch/arm/boot/dts/omap44xx-clocks.dtsi
+8
-3
arch/arm/boot/dts/omap5-l4.dtsi
arch/arm/boot/dts/omap5-l4.dtsi
+17
-3
arch/arm/boot/dts/omap54xx-clocks.dtsi
arch/arm/boot/dts/omap54xx-clocks.dtsi
+8
-2
arch/arm/mach-omap2/omap_hwmod_44xx_data.c
arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+0
-135
drivers/clk/ti/clk-44xx.c
drivers/clk/ti/clk-44xx.c
+13
-0
drivers/clk/ti/clk-54xx.c
drivers/clk/ti/clk-54xx.c
+28
-0
drivers/clk/ti/clk-7xx.c
drivers/clk/ti/clk-7xx.c
+61
-1
drivers/clk/ti/clk.c
drivers/clk/ti/clk.c
+3
-1
drivers/clk/ti/clkctrl.c
drivers/clk/ti/clkctrl.c
+85
-11
include/dt-bindings/clock/dra7.h
include/dt-bindings/clock/dra7.h
+23
-0
include/dt-bindings/clock/omap4.h
include/dt-bindings/clock/omap4.h
+11
-0
include/dt-bindings/clock/omap5.h
include/dt-bindings/clock/omap5.h
+12
-0
include/dt-bindings/clock/ti-dra7-atl.h
include/dt-bindings/clock/ti-dra7-atl.h
+0
-0
No files found.
Documentation/devicetree/bindings/clock/ti-clkctrl.txt
View file @
885d21e4
...
@@ -16,18 +16,23 @@ For more information, please see the Linux clock framework binding at
...
@@ -16,18 +16,23 @@ For more information, please see the Linux clock framework binding at
Documentation/devicetree/bindings/clock/clock-bindings.txt.
Documentation/devicetree/bindings/clock/clock-bindings.txt.
Required properties :
Required properties :
- compatible : shall be "ti,clkctrl"
- compatible : shall be "ti,clkctrl" or a clock domain specific name:
"ti,clkctrl-l4-cfg"
"ti,clkctrl-l4-per"
"ti,clkctrl-l4-secure"
"ti,clkctrl-l4-wkup"
- #clock-cells : shall contain 2 with the first entry being the instance
- #clock-cells : shall contain 2 with the first entry being the instance
offset from the clock domain base and the second being the
offset from the clock domain base and the second being the
clock index
clock index
- reg : clock registers
Example: Clock controller node on omap 4430:
Example: Clock controller node on omap 4430:
&cm2 {
&cm2 {
l4per: cm@1400 {
l4per: cm@1400 {
cm_l4per@0 {
cm_l4per@0 {
cm_l4per_clkctrl: clk@20 {
cm_l4per_clkctrl: cl
oc
k@20 {
compatible = "ti,clkctrl";
compatible = "ti,clkctrl
-l4-per", "ti,clkctrl
";
reg = <0x20 0x1b0>;
reg = <0x20 0x1b0>;
#clock-cells = <2>;
#clock-cells = <2>;
};
};
...
...
Documentation/devicetree/bindings/clock/ti/dra7-atl.txt
View file @
885d21e4
...
@@ -43,7 +43,7 @@ Configuration of ATL instances:
...
@@ -43,7 +43,7 @@ Configuration of ATL instances:
- aws : Audio word select signal selection
- aws : Audio word select signal selection
};
};
For valid word select signals, see the dt-bindings/clk/ti-dra7-atl.h include
For valid word select signals, see the dt-bindings/cl
oc
k/ti-dra7-atl.h include
file.
file.
Examples:
Examples:
...
@@ -83,7 +83,7 @@ atl: atl@4843c000 {
...
@@ -83,7 +83,7 @@ atl: atl@4843c000 {
clock-names = "fck";
clock-names = "fck";
};
};
#include <dt-bindings/clk/ti-dra7-atl.h>
#include <dt-bindings/cl
oc
k/ti-dra7-atl.h>
&atl {
&atl {
...
...
arch/arm/boot/dts/dra7-evm-common.dtsi
View file @
885d21e4
...
@@ -4,7 +4,7 @@
...
@@ -4,7 +4,7 @@
*/
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/clk/ti-dra7-atl.h>
#include <dt-bindings/cl
oc
k/ti-dra7-atl.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/input/input.h>
/ {
/ {
...
...
arch/arm/boot/dts/dra72-evm-common.dtsi
View file @
885d21e4
...
@@ -6,7 +6,7 @@
...
@@ -6,7 +6,7 @@
#include "dra72x.dtsi"
#include "dra72x.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/clk/ti-dra7-atl.h>
#include <dt-bindings/cl
oc
k/ti-dra7-atl.h>
/ {
/ {
compatible = "ti,dra72-evm", "ti,dra722", "ti,dra72", "ti,dra7";
compatible = "ti,dra72-evm", "ti,dra722", "ti,dra72", "ti,dra7";
...
...
arch/arm/boot/dts/dra7xx-clocks.dtsi
View file @
885d21e4
...
@@ -1734,6 +1734,20 @@ dss_clkctrl: dss-clkctrl@20 {
...
@@ -1734,6 +1734,20 @@ dss_clkctrl: dss-clkctrl@20 {
};
};
};
};
gpu_cm: gpu-cm@1200 {
compatible = "ti,omap4-cm";
reg = <0x1200 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x1200 0x100>;
gpu_clkctrl: gpu-clkctrl@20 {
compatible = "ti,clkctrl";
reg = <0x20 0x4>;
#clock-cells = <2>;
};
};
l3init_cm: l3init-cm@1300 {
l3init_cm: l3init-cm@1300 {
compatible = "ti,omap4-cm";
compatible = "ti,omap4-cm";
reg = <0x1300 0x100>;
reg = <0x1300 0x100>;
...
...
arch/arm/boot/dts/motorola-mapphone-common.dtsi
View file @
885d21e4
...
@@ -650,6 +650,11 @@ OMAP4_IOPAD(0x040, PIN_OUTPUT_PULLDOWN | MUX_MODE3)
...
@@ -650,6 +650,11 @@ OMAP4_IOPAD(0x040, PIN_OUTPUT_PULLDOWN | MUX_MODE3)
};
};
};
};
/* RNG is used by secure mode and not accessible */
&rng_target {
status = "disabled";
};
/* Configure pwm clock source for timers 8 & 9 */
/* Configure pwm clock source for timers 8 & 9 */
&timer8 {
&timer8 {
assigned-clocks = <&abe_clkctrl OMAP4_TIMER8_CLKCTRL 24>;
assigned-clocks = <&abe_clkctrl OMAP4_TIMER8_CLKCTRL 24>;
...
...
arch/arm/boot/dts/omap4-l4.dtsi
View file @
885d21e4
...
@@ -1990,12 +1990,26 @@ timer11: timer@0 {
...
@@ -1990,12 +1990,26 @@ timer11: timer@0 {
};
};
};
};
target-module@90000 { /* 0x48090000, ap 57 2a.0 */
rng_target: target-module@90000 { /* 0x48090000, ap 57 2a.0 */
compatible = "ti,sysc";
compatible = "ti,sysc-omap2", "ti,sysc";
status = "disabled";
reg = <0x91fe0 0x4>,
<0x91fe4 0x4>;
reg-names = "rev", "sysc";
ti,sysc-mask = <(SYSC_OMAP2_AUTOIDLE)>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>;
/* Domains (P, C): l4per_pwrdm, l4_secure_clkdm */
clocks = <&l4_secure_clkctrl OMAP4_RNG_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
#address-cells = <1>;
#size-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x90000 0x2000>;
ranges = <0x0 0x90000 0x2000>;
rng: rng@0 {
compatible = "ti,omap4-rng";
reg = <0x0 0x2000>;
interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
};
};
};
target-module@96000 { /* 0x48096000, ap 37 26.0 */
target-module@96000 { /* 0x48096000, ap 37 26.0 */
...
@@ -2159,6 +2173,35 @@ target-module@a4000 { /* 0x480a4000, ap 59 34.0 */
...
@@ -2159,6 +2173,35 @@ target-module@a4000 { /* 0x480a4000, ap 59 34.0 */
<0x00001000 0x000a5000 0x00001000>;
<0x00001000 0x000a5000 0x00001000>;
};
};
des_target: target-module@a5000 { /* 0x480a5000 */
compatible = "ti,sysc-omap2", "ti,sysc";
reg = <0xa5030 0x4>,
<0xa5034 0x4>,
<0xa5038 0x4>;
reg-names = "rev", "sysc", "syss";
ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
SYSC_OMAP2_AUTOIDLE)>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>,
<SYSC_IDLE_SMART_WKUP>;
ti,syss-mask = <1>;
/* Domains (P, C): l4per_pwrdm, l4_secure_clkdm */
clocks = <&l4_secure_clkctrl OMAP4_DES3DES_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0xa5000 0x00001000>;
des: des@0 {
compatible = "ti,omap4-des";
reg = <0 0xa0>;
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&sdma 117>, <&sdma 116>;
dma-names = "tx", "rx";
};
};
target-module@a8000 { /* 0x480a8000, ap 61 3e.0 */
target-module@a8000 { /* 0x480a8000, ap 61 3e.0 */
compatible = "ti,sysc";
compatible = "ti,sysc";
status = "disabled";
status = "disabled";
...
...
arch/arm/boot/dts/omap4.dtsi
View file @
885d21e4
...
@@ -278,40 +278,90 @@ emif2: emif@4d000000 {
...
@@ -278,40 +278,90 @@ emif2: emif@4d000000 {
hw-caps-temp-alert;
hw-caps-temp-alert;
};
};
aes1: aes@4b501000 {
aes1_target: target-module@4b501000 {
compatible = "ti,omap4-aes";
compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "aes1";
reg = <0x4b501080 0x4>,
reg = <0x4b501000 0xa0>;
<0x4b501084 0x4>,
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
<0x4b501088 0x4>;
dmas = <&sdma 111>, <&sdma 110>;
reg-names = "rev", "sysc", "syss";
dma-names = "tx", "rx";
ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
};
SYSC_OMAP2_AUTOIDLE)>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
aes2: aes@4b701000 {
<SYSC_IDLE_NO>,
compatible = "ti,omap4-aes";
<SYSC_IDLE_SMART>,
ti,hwmods = "aes2";
<SYSC_IDLE_SMART_WKUP>;
reg = <0x4b701000 0xa0>;
ti,syss-mask = <1>;
interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
/* Domains (P, C): l4per_pwrdm, l4_secure_clkdm */
dmas = <&sdma 114>, <&sdma 113>;
clocks = <&l4_secure_clkctrl OMAP4_AES1_CLKCTRL 0>;
dma-names = "tx", "rx";
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x4b501000 0x1000>;
aes1: aes@0 {
compatible = "ti,omap4-aes";
reg = <0 0xa0>;
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&sdma 111>, <&sdma 110>;
dma-names = "tx", "rx";
};
};
};
des: des@480a5000 {
aes2_target: target-module@4b701000 {
compatible = "ti,omap4-des";
compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "des";
reg = <0x4b701080 0x4>,
reg = <0x480a5000 0xa0>;
<0x4b701084 0x4>,
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
<0x4b701088 0x4>;
dmas = <&sdma 117>, <&sdma 116>;
reg-names = "rev", "sysc", "syss";
dma-names = "tx", "rx";
ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
SYSC_OMAP2_AUTOIDLE)>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>,
<SYSC_IDLE_SMART_WKUP>;
ti,syss-mask = <1>;
/* Domains (P, C): l4per_pwrdm, l4_secure_clkdm */
clocks = <&l4_secure_clkctrl OMAP4_AES2_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x4b701000 0x1000>;
aes2: aes@0 {
compatible = "ti,omap4-aes";
reg = <0 0xa0>;
interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&sdma 114>, <&sdma 113>;
dma-names = "tx", "rx";
};
};
};
sham: sham@4b100000 {
sham_target: target-module@4b100000 {
compatible = "ti,omap4-sham";
compatible = "ti,sysc-omap3-sham", "ti,sysc";
ti,hwmods = "sham";
reg = <0x4b100100 0x4>,
reg = <0x4b100000 0x300>;
<0x4b100110 0x4>,
interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
<0x4b100114 0x4>;
dmas = <&sdma 119>;
reg-names = "rev", "sysc", "syss";
dma-names = "rx";
ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
SYSC_OMAP2_AUTOIDLE)>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>;
ti,syss-mask = <1>;
/* Domains (P, C): l4per_pwrdm, l4_secure_clkdm */
clocks = <&l4_secure_clkctrl OMAP4_SHA2MD5_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x4b100000 0x1000>;
sham: sham@0 {
compatible = "ti,omap4-sham";
reg = <0 0x300>;
interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&sdma 119>;
dma-names = "rx";
};
};
};
abb_mpu: regulator-abb-mpu {
abb_mpu: regulator-abb-mpu {
...
...
arch/arm/boot/dts/omap44xx-clocks.dtsi
View file @
885d21e4
...
@@ -1279,13 +1279,18 @@ l4_per_cm: l4_per_cm@1400 {
...
@@ -1279,13 +1279,18 @@ l4_per_cm: l4_per_cm@1400 {
#size-cells = <1>;
#size-cells = <1>;
ranges = <0 0x1400 0x200>;
ranges = <0 0x1400 0x200>;
l4_per_clkctrl: clk@20 {
l4_per_clkctrl: cl
oc
k@20 {
compatible = "ti,clkctrl";
compatible = "ti,clkctrl
-l4-per", "ti,clkctrl
";
reg = <0x20 0x144>;
reg = <0x20 0x144>;
#clock-cells = <2>;
#clock-cells = <2>;
};
};
};
l4_secure_clkctrl: clock@1a0 {
compatible = "ti,clkctrl-l4-secure", "ti,clkctrl";
reg = <0x1a0 0x3c>;
#clock-cells = <2>;
};
};
};
};
&prm {
&prm {
...
...
arch/arm/boot/dts/omap5-l4.dtsi
View file @
885d21e4
...
@@ -1764,12 +1764,26 @@ timer11: timer@0 {
...
@@ -1764,12 +1764,26 @@ timer11: timer@0 {
};
};
};
};
target-module@90000 { /* 0x48090000, ap 55 1a.0 */
rng_target: target-module@90000 { /* 0x48090000, ap 55 1a.0 */
compatible = "ti,sysc";
compatible = "ti,sysc-omap2", "ti,sysc";
status = "disabled";
reg = <0x91fe0 0x4>,
<0x91fe4 0x4>;
reg-names = "rev", "sysc";
ti,sysc-mask = <(SYSC_OMAP2_AUTOIDLE)>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>;
/* Domains (P, C): l4per_pwrdm, l4sec_clkdm */
clocks = <&l4sec_clkctrl OMAP5_RNG_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
#address-cells = <1>;
#size-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x90000 0x2000>;
ranges = <0x0 0x90000 0x2000>;
rng: rng@0 {
compatible = "ti,omap4-rng";
reg = <0x0 0x2000>;
interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
};
};
};
target-module@98000 { /* 0x48098000, ap 47 08.0 */
target-module@98000 { /* 0x48098000, ap 47 08.0 */
...
...
arch/arm/boot/dts/omap54xx-clocks.dtsi
View file @
885d21e4
...
@@ -1125,11 +1125,17 @@ l4per_cm: l4per_cm@1000 {
...
@@ -1125,11 +1125,17 @@ l4per_cm: l4per_cm@1000 {
#size-cells = <1>;
#size-cells = <1>;
ranges = <0 0x1000 0x200>;
ranges = <0 0x1000 0x200>;
l4per_clkctrl: clk@20 {
l4per_clkctrl: cl
oc
k@20 {
compatible = "ti,clkctrl";
compatible = "ti,clkctrl
-l4per", "ti,clkctrl
";
reg = <0x20 0x15c>;
reg = <0x20 0x15c>;
#clock-cells = <2>;
#clock-cells = <2>;
};
};
l4sec_clkctrl: clock@1a0 {
compatible = "ti,clkctrl-l4sec", "ti,clkctrl";
reg = <0x1a0 0x3c>;
#clock-cells = <2>;
};
};
};
dss_cm: dss_cm@1400 {
dss_cm: dss_cm@1400 {
...
...
arch/arm/mach-omap2/omap_hwmod_44xx_data.c
View file @
885d21e4
...
@@ -653,32 +653,6 @@ static struct omap_hwmod omap44xx_dss_venc_hwmod = {
...
@@ -653,32 +653,6 @@ static struct omap_hwmod omap44xx_dss_venc_hwmod = {
.
opt_clks_cnt
=
ARRAY_SIZE
(
dss_venc_opt_clks
),
.
opt_clks_cnt
=
ARRAY_SIZE
(
dss_venc_opt_clks
),
};
};
/* sha0 HIB2 (the 'P' (public) device) */
static
struct
omap_hwmod_class_sysconfig
omap44xx_sha0_sysc
=
{
.
rev_offs
=
0x100
,
.
sysc_offs
=
0x110
,
.
syss_offs
=
0x114
,
.
sysc_flags
=
SYSS_HAS_RESET_STATUS
,
};
static
struct
omap_hwmod_class
omap44xx_sha0_hwmod_class
=
{
.
name
=
"sham"
,
.
sysc
=
&
omap44xx_sha0_sysc
,
};
static
struct
omap_hwmod
omap44xx_sha0_hwmod
=
{
.
name
=
"sham"
,
.
class
=
&
omap44xx_sha0_hwmod_class
,
.
clkdm_name
=
"l4_secure_clkdm"
,
.
main_clk
=
"l3_div_ck"
,
.
prcm
=
{
.
omap4
=
{
.
clkctrl_offs
=
OMAP4_CM_L4SEC_SHA2MD51_CLKCTRL_OFFSET
,
.
context_offs
=
OMAP4_RM_L4SEC_SHA2MD51_CONTEXT_OFFSET
,
.
modulemode
=
MODULEMODE_SWCTRL
,
},
},
};
/*
/*
...
@@ -727,103 +701,6 @@ static struct omap_hwmod omap44xx_emif2_hwmod = {
...
@@ -727,103 +701,6 @@ static struct omap_hwmod omap44xx_emif2_hwmod = {
},
},
};
};
/*
Crypto modules AES0/1 belong to:
PD_L4_PER power domain
CD_L4_SEC clock domain
On the L3, the AES modules are mapped to
L3_CLK2: Peripherals and multimedia sub clock domain
*/
static
struct
omap_hwmod_class_sysconfig
omap44xx_aes_sysc
=
{
.
rev_offs
=
0x80
,
.
sysc_offs
=
0x84
,
.
syss_offs
=
0x88
,
.
sysc_flags
=
SYSS_HAS_RESET_STATUS
,
};
static
struct
omap_hwmod_class
omap44xx_aes_hwmod_class
=
{
.
name
=
"aes"
,
.
sysc
=
&
omap44xx_aes_sysc
,
};
static
struct
omap_hwmod
omap44xx_aes1_hwmod
=
{
.
name
=
"aes1"
,
.
class
=
&
omap44xx_aes_hwmod_class
,
.
clkdm_name
=
"l4_secure_clkdm"
,
.
main_clk
=
"l3_div_ck"
,
.
prcm
=
{
.
omap4
=
{
.
context_offs
=
OMAP4_RM_L4SEC_AES1_CONTEXT_OFFSET
,
.
clkctrl_offs
=
OMAP4_CM_L4SEC_AES1_CLKCTRL_OFFSET
,
.
modulemode
=
MODULEMODE_SWCTRL
,
},
},
};
static
struct
omap_hwmod_ocp_if
omap44xx_l3_main_2__aes1
=
{
.
master
=
&
omap44xx_l4_per_hwmod
,
.
slave
=
&
omap44xx_aes1_hwmod
,
.
clk
=
"l3_div_ck"
,
.
user
=
OCP_USER_MPU
|
OCP_USER_SDMA
,
};
static
struct
omap_hwmod
omap44xx_aes2_hwmod
=
{
.
name
=
"aes2"
,
.
class
=
&
omap44xx_aes_hwmod_class
,
.
clkdm_name
=
"l4_secure_clkdm"
,
.
main_clk
=
"l3_div_ck"
,
.
prcm
=
{
.
omap4
=
{
.
context_offs
=
OMAP4_RM_L4SEC_AES2_CONTEXT_OFFSET
,
.
clkctrl_offs
=
OMAP4_CM_L4SEC_AES2_CLKCTRL_OFFSET
,
.
modulemode
=
MODULEMODE_SWCTRL
,
},
},
};
static
struct
omap_hwmod_ocp_if
omap44xx_l3_main_2__aes2
=
{
.
master
=
&
omap44xx_l4_per_hwmod
,
.
slave
=
&
omap44xx_aes2_hwmod
,
.
clk
=
"l3_div_ck"
,
.
user
=
OCP_USER_MPU
|
OCP_USER_SDMA
,
};
/*
* 'des' class for DES3DES module
*/
static
struct
omap_hwmod_class_sysconfig
omap44xx_des_sysc
=
{
.
rev_offs
=
0x30
,
.
sysc_offs
=
0x34
,
.
syss_offs
=
0x38
,
.
sysc_flags
=
SYSS_HAS_RESET_STATUS
,
};
static
struct
omap_hwmod_class
omap44xx_des_hwmod_class
=
{
.
name
=
"des"
,
.
sysc
=
&
omap44xx_des_sysc
,
};
static
struct
omap_hwmod
omap44xx_des_hwmod
=
{
.
name
=
"des"
,
.
class
=
&
omap44xx_des_hwmod_class
,
.
clkdm_name
=
"l4_secure_clkdm"
,
.
main_clk
=
"l3_div_ck"
,
.
prcm
=
{
.
omap4
=
{
.
context_offs
=
OMAP4_RM_L4SEC_DES3DES_CONTEXT_OFFSET
,
.
clkctrl_offs
=
OMAP4_CM_L4SEC_DES3DES_CLKCTRL_OFFSET
,
.
modulemode
=
MODULEMODE_SWCTRL
,
},
},
};
static
struct
omap_hwmod_ocp_if
omap44xx_l3_main_2__des
=
{
.
master
=
&
omap44xx_l3_main_2_hwmod
,
.
slave
=
&
omap44xx_des_hwmod
,
.
clk
=
"l3_div_ck"
,
.
user
=
OCP_USER_MPU
|
OCP_USER_SDMA
,
};
/*
/*
* 'gpmc' class
* 'gpmc' class
* general purpose memory controller
* general purpose memory controller
...
@@ -1735,14 +1612,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_venc = {
...
@@ -1735,14 +1612,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_venc = {
.
user
=
OCP_USER_MPU
,
.
user
=
OCP_USER_MPU
,
};
};
/* l3_main_2 -> sham */
static
struct
omap_hwmod_ocp_if
omap44xx_l3_main_2__sha0
=
{
.
master
=
&
omap44xx_l3_main_2_hwmod
,
.
slave
=
&
omap44xx_sha0_hwmod
,
.
clk
=
"l3_div_ck"
,
.
user
=
OCP_USER_MPU
|
OCP_USER_SDMA
,
};
/* l3_main_2 -> gpmc */
/* l3_main_2 -> gpmc */
static
struct
omap_hwmod_ocp_if
omap44xx_l3_main_2__gpmc
=
{
static
struct
omap_hwmod_ocp_if
omap44xx_l3_main_2__gpmc
=
{
.
master
=
&
omap44xx_l3_main_2_hwmod
,
.
master
=
&
omap44xx_l3_main_2_hwmod
,
...
@@ -1958,10 +1827,6 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
...
@@ -1958,10 +1827,6 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
&
omap44xx_l4_cfg__usb_tll_hs
,
&
omap44xx_l4_cfg__usb_tll_hs
,
&
omap44xx_mpu__emif1
,
&
omap44xx_mpu__emif1
,
&
omap44xx_mpu__emif2
,
&
omap44xx_mpu__emif2
,
&
omap44xx_l3_main_2__aes1
,
&
omap44xx_l3_main_2__aes2
,
&
omap44xx_l3_main_2__des
,
&
omap44xx_l3_main_2__sha0
,
NULL
,
NULL
,
};
};
...
...
drivers/clk/ti/clk-44xx.c
View file @
885d21e4
...
@@ -604,6 +604,18 @@ static const struct omap_clkctrl_reg_data omap4_l4_per_clkctrl_regs[] __initcons
...
@@ -604,6 +604,18 @@ static const struct omap_clkctrl_reg_data omap4_l4_per_clkctrl_regs[] __initcons
{
0
},
{
0
},
};
};
static
const
struct
omap_clkctrl_reg_data
omap4_l4_secure_clkctrl_regs
[]
__initconst
=
{
{
OMAP4_AES1_CLKCTRL
,
NULL
,
CLKF_SW_SUP
,
""
},
{
OMAP4_AES2_CLKCTRL
,
NULL
,
CLKF_SW_SUP
,
""
},
{
OMAP4_DES3DES_CLKCTRL
,
NULL
,
CLKF_SW_SUP
,
""
},
{
OMAP4_PKA_CLKCTRL
,
NULL
,
CLKF_SW_SUP
,
""
},
{
OMAP4_RNG_CLKCTRL
,
NULL
,
CLKF_HW_SUP
|
CLKF_SOC_NONSEC
,
""
},
{
OMAP4_SHA2MD5_CLKCTRL
,
NULL
,
CLKF_SW_SUP
,
""
},
{
OMAP4_CRYPTODMA_CLKCTRL
,
NULL
,
CLKF_HW_SUP
|
CLKF_SOC_NONSEC
,
""
},
{
0
},
};
static
const
struct
omap_clkctrl_bit_data
omap4_gpio1_bit_data
[]
__initconst
=
{
static
const
struct
omap_clkctrl_bit_data
omap4_gpio1_bit_data
[]
__initconst
=
{
{
8
,
TI_CLK_GATE
,
omap4_gpio2_dbclk_parents
,
NULL
},
{
8
,
TI_CLK_GATE
,
omap4_gpio2_dbclk_parents
,
NULL
},
{
0
},
{
0
},
...
@@ -691,6 +703,7 @@ const struct omap_clkctrl_data omap4_clkctrl_data[] __initconst = {
...
@@ -691,6 +703,7 @@ const struct omap_clkctrl_data omap4_clkctrl_data[] __initconst = {
{
0x4a009220
,
omap4_l3_gfx_clkctrl_regs
},
{
0x4a009220
,
omap4_l3_gfx_clkctrl_regs
},
{
0x4a009320
,
omap4_l3_init_clkctrl_regs
},
{
0x4a009320
,
omap4_l3_init_clkctrl_regs
},
{
0x4a009420
,
omap4_l4_per_clkctrl_regs
},
{
0x4a009420
,
omap4_l4_per_clkctrl_regs
},
{
0x4a0095a0
,
omap4_l4_secure_clkctrl_regs
},
{
0x4a307820
,
omap4_l4_wkup_clkctrl_regs
},
{
0x4a307820
,
omap4_l4_wkup_clkctrl_regs
},
{
0x4a307a20
,
omap4_emu_sys_clkctrl_regs
},
{
0x4a307a20
,
omap4_emu_sys_clkctrl_regs
},
{
0
},
{
0
},
...
...
drivers/clk/ti/clk-54xx.c
View file @
885d21e4
...
@@ -35,6 +35,20 @@ static const struct omap_clkctrl_reg_data omap5_dsp_clkctrl_regs[] __initconst =
...
@@ -35,6 +35,20 @@ static const struct omap_clkctrl_reg_data omap5_dsp_clkctrl_regs[] __initconst =
{
0
},
{
0
},
};
};
static
const
char
*
const
omap5_aess_fclk_parents
[]
__initconst
=
{
"abe_clk"
,
NULL
,
};
static
const
struct
omap_clkctrl_div_data
omap5_aess_fclk_data
__initconst
=
{
.
max_div
=
2
,
};
static
const
struct
omap_clkctrl_bit_data
omap5_aess_bit_data
[]
__initconst
=
{
{
24
,
TI_CLK_DIVIDER
,
omap5_aess_fclk_parents
,
&
omap5_aess_fclk_data
},
{
0
},
};
static
const
char
*
const
omap5_dmic_gfclk_parents
[]
__initconst
=
{
static
const
char
*
const
omap5_dmic_gfclk_parents
[]
__initconst
=
{
"abe_cm:clk:0018:26"
,
"abe_cm:clk:0018:26"
,
"pad_clks_ck"
,
"pad_clks_ck"
,
...
@@ -122,6 +136,7 @@ static const struct omap_clkctrl_bit_data omap5_timer8_bit_data[] __initconst =
...
@@ -122,6 +136,7 @@ static const struct omap_clkctrl_bit_data omap5_timer8_bit_data[] __initconst =
static
const
struct
omap_clkctrl_reg_data
omap5_abe_clkctrl_regs
[]
__initconst
=
{
static
const
struct
omap_clkctrl_reg_data
omap5_abe_clkctrl_regs
[]
__initconst
=
{
{
OMAP5_L4_ABE_CLKCTRL
,
NULL
,
0
,
"abe_iclk"
},
{
OMAP5_L4_ABE_CLKCTRL
,
NULL
,
0
,
"abe_iclk"
},
{
OMAP5_AESS_CLKCTRL
,
omap5_aess_bit_data
,
CLKF_SW_SUP
,
"abe_cm:clk:0008:24"
},
{
OMAP5_MCPDM_CLKCTRL
,
NULL
,
CLKF_SW_SUP
,
"pad_clks_ck"
},
{
OMAP5_MCPDM_CLKCTRL
,
NULL
,
CLKF_SW_SUP
,
"pad_clks_ck"
},
{
OMAP5_DMIC_CLKCTRL
,
omap5_dmic_bit_data
,
CLKF_SW_SUP
,
"abe_cm:clk:0018:24"
},
{
OMAP5_DMIC_CLKCTRL
,
omap5_dmic_bit_data
,
CLKF_SW_SUP
,
"abe_cm:clk:0018:24"
},
{
OMAP5_MCBSP1_CLKCTRL
,
omap5_mcbsp1_bit_data
,
CLKF_SW_SUP
,
"abe_cm:clk:0028:24"
},
{
OMAP5_MCBSP1_CLKCTRL
,
omap5_mcbsp1_bit_data
,
CLKF_SW_SUP
,
"abe_cm:clk:0028:24"
},
...
@@ -286,6 +301,18 @@ static const struct omap_clkctrl_reg_data omap5_l4per_clkctrl_regs[] __initconst
...
@@ -286,6 +301,18 @@ static const struct omap_clkctrl_reg_data omap5_l4per_clkctrl_regs[] __initconst
{
0
},
{
0
},
};
};
static
const
struct
omap_clkctrl_reg_data
omap5_l4_secure_clkctrl_regs
[]
__initconst
=
{
{
OMAP5_AES1_CLKCTRL
,
NULL
,
CLKF_HW_SUP
,
""
},
{
OMAP5_AES2_CLKCTRL
,
NULL
,
CLKF_HW_SUP
,
""
},
{
OMAP5_DES3DES_CLKCTRL
,
NULL
,
CLKF_HW_SUP
,
""
},
{
OMAP5_FPKA_CLKCTRL
,
NULL
,
CLKF_SW_SUP
,
""
},
{
OMAP5_RNG_CLKCTRL
,
NULL
,
CLKF_HW_SUP
|
CLKF_SOC_NONSEC
,
""
},
{
OMAP5_SHA2MD5_CLKCTRL
,
NULL
,
CLKF_HW_SUP
,
""
},
{
OMAP5_DMA_CRYPTO_CLKCTRL
,
NULL
,
CLKF_HW_SUP
|
CLKF_SOC_NONSEC
,
""
},
{
0
},
};
static
const
struct
omap_clkctrl_reg_data
omap5_iva_clkctrl_regs
[]
__initconst
=
{
static
const
struct
omap_clkctrl_reg_data
omap5_iva_clkctrl_regs
[]
__initconst
=
{
{
OMAP5_IVA_CLKCTRL
,
NULL
,
CLKF_HW_SUP
,
"dpll_iva_h12x2_ck"
},
{
OMAP5_IVA_CLKCTRL
,
NULL
,
CLKF_HW_SUP
,
"dpll_iva_h12x2_ck"
},
{
OMAP5_SL2IF_CLKCTRL
,
NULL
,
CLKF_HW_SUP
,
"dpll_iva_h12x2_ck"
},
{
OMAP5_SL2IF_CLKCTRL
,
NULL
,
CLKF_HW_SUP
,
"dpll_iva_h12x2_ck"
},
...
@@ -508,6 +535,7 @@ const struct omap_clkctrl_data omap5_clkctrl_data[] __initconst = {
...
@@ -508,6 +535,7 @@ const struct omap_clkctrl_data omap5_clkctrl_data[] __initconst = {
{
0x4a008d20
,
omap5_l4cfg_clkctrl_regs
},
{
0x4a008d20
,
omap5_l4cfg_clkctrl_regs
},
{
0x4a008e20
,
omap5_l3instr_clkctrl_regs
},
{
0x4a008e20
,
omap5_l3instr_clkctrl_regs
},
{
0x4a009020
,
omap5_l4per_clkctrl_regs
},
{
0x4a009020
,
omap5_l4per_clkctrl_regs
},
{
0x4a0091a0
,
omap5_l4_secure_clkctrl_regs
},
{
0x4a009220
,
omap5_iva_clkctrl_regs
},
{
0x4a009220
,
omap5_iva_clkctrl_regs
},
{
0x4a009420
,
omap5_dss_clkctrl_regs
},
{
0x4a009420
,
omap5_dss_clkctrl_regs
},
{
0x4a009520
,
omap5_gpu_clkctrl_regs
},
{
0x4a009520
,
omap5_gpu_clkctrl_regs
},
...
...
drivers/clk/ti/clk-7xx.c
View file @
885d21e4
...
@@ -146,6 +146,29 @@ static const struct omap_clkctrl_reg_data dra7_rtc_clkctrl_regs[] __initconst =
...
@@ -146,6 +146,29 @@ static const struct omap_clkctrl_reg_data dra7_rtc_clkctrl_regs[] __initconst =
{
0
},
{
0
},
};
};
static
const
char
*
const
dra7_cam_gfclk_mux_parents
[]
__initconst
=
{
"l3_iclk_div"
,
"core_iss_main_clk"
,
NULL
,
};
static
const
struct
omap_clkctrl_bit_data
dra7_cam_bit_data
[]
__initconst
=
{
{
24
,
TI_CLK_MUX
,
dra7_cam_gfclk_mux_parents
,
NULL
},
{
0
},
};
static
const
struct
omap_clkctrl_reg_data
dra7_cam_clkctrl_regs
[]
__initconst
=
{
{
DRA7_CAM_VIP1_CLKCTRL
,
dra7_cam_bit_data
,
CLKF_HW_SUP
,
"l3_iclk_div"
},
{
DRA7_CAM_VIP2_CLKCTRL
,
dra7_cam_bit_data
,
CLKF_HW_SUP
,
"l3_iclk_div"
},
{
DRA7_CAM_VIP3_CLKCTRL
,
dra7_cam_bit_data
,
CLKF_HW_SUP
,
"l3_iclk_div"
},
{
0
},
};
static
const
struct
omap_clkctrl_reg_data
dra7_vpe_clkctrl_regs
[]
__initconst
=
{
{
DRA7_VPE_VPE_CLKCTRL
,
NULL
,
CLKF_HW_SUP
,
"dpll_core_h23x2_ck"
},
{
0
},
};
static
const
struct
omap_clkctrl_reg_data
dra7_coreaon_clkctrl_regs
[]
__initconst
=
{
static
const
struct
omap_clkctrl_reg_data
dra7_coreaon_clkctrl_regs
[]
__initconst
=
{
{
DRA7_COREAON_SMARTREFLEX_MPU_CLKCTRL
,
NULL
,
CLKF_SW_SUP
,
"wkupaon_iclk_mux"
},
{
DRA7_COREAON_SMARTREFLEX_MPU_CLKCTRL
,
NULL
,
CLKF_SW_SUP
,
"wkupaon_iclk_mux"
},
{
DRA7_COREAON_SMARTREFLEX_CORE_CLKCTRL
,
NULL
,
CLKF_SW_SUP
,
"wkupaon_iclk_mux"
},
{
DRA7_COREAON_SMARTREFLEX_CORE_CLKCTRL
,
NULL
,
CLKF_SW_SUP
,
"wkupaon_iclk_mux"
},
...
@@ -275,6 +298,40 @@ static const struct omap_clkctrl_reg_data dra7_dss_clkctrl_regs[] __initconst =
...
@@ -275,6 +298,40 @@ static const struct omap_clkctrl_reg_data dra7_dss_clkctrl_regs[] __initconst =
{
0
},
{
0
},
};
};
static
const
char
*
const
dra7_gpu_core_mux_parents
[]
__initconst
=
{
"dpll_core_h14x2_ck"
,
"dpll_per_h14x2_ck"
,
"dpll_gpu_m2_ck"
,
NULL
,
};
static
const
char
*
const
dra7_gpu_hyd_mux_parents
[]
__initconst
=
{
"dpll_core_h14x2_ck"
,
"dpll_per_h14x2_ck"
,
"dpll_gpu_m2_ck"
,
NULL
,
};
static
const
char
*
const
dra7_gpu_sys_clk_parents
[]
__initconst
=
{
"sys_clkin"
,
NULL
,
};
static
const
struct
omap_clkctrl_div_data
dra7_gpu_sys_clk_data
__initconst
=
{
.
max_div
=
2
,
};
static
const
struct
omap_clkctrl_bit_data
dra7_gpu_core_bit_data
[]
__initconst
=
{
{
24
,
TI_CLK_MUX
,
dra7_gpu_core_mux_parents
,
NULL
,
},
{
26
,
TI_CLK_MUX
,
dra7_gpu_hyd_mux_parents
,
NULL
,
},
{
0
},
};
static
const
struct
omap_clkctrl_reg_data
dra7_gpu_clkctrl_regs
[]
__initconst
=
{
{
DRA7_GPU_CLKCTRL
,
dra7_gpu_core_bit_data
,
CLKF_SW_SUP
,
"gpu_cm:clk:0000:24"
,
},
{
0
},
};
static
const
char
*
const
dra7_mmc1_fclk_mux_parents
[]
__initconst
=
{
static
const
char
*
const
dra7_mmc1_fclk_mux_parents
[]
__initconst
=
{
"func_128m_clk"
,
"func_128m_clk"
,
"dpll_per_m2x2_ck"
,
"dpll_per_m2x2_ck"
,
...
@@ -405,7 +462,7 @@ static const struct omap_clkctrl_bit_data dra7_gmac_bit_data[] __initconst = {
...
@@ -405,7 +462,7 @@ static const struct omap_clkctrl_bit_data dra7_gmac_bit_data[] __initconst = {
};
};
static
const
struct
omap_clkctrl_reg_data
dra7_gmac_clkctrl_regs
[]
__initconst
=
{
static
const
struct
omap_clkctrl_reg_data
dra7_gmac_clkctrl_regs
[]
__initconst
=
{
{
DRA7_GMAC_GMAC_CLKCTRL
,
dra7_gmac_bit_data
,
CLKF_SW_SUP
,
"
dpll_gmac_c
k"
},
{
DRA7_GMAC_GMAC_CLKCTRL
,
dra7_gmac_bit_data
,
CLKF_SW_SUP
,
"
gmac_main_cl
k"
},
{
0
},
{
0
},
};
};
...
@@ -769,6 +826,7 @@ const struct omap_clkctrl_data dra7_clkctrl_data[] __initconst = {
...
@@ -769,6 +826,7 @@ const struct omap_clkctrl_data dra7_clkctrl_data[] __initconst = {
{
0x4a005550
,
dra7_ipu_clkctrl_regs
},
{
0x4a005550
,
dra7_ipu_clkctrl_regs
},
{
0x4a005620
,
dra7_dsp2_clkctrl_regs
},
{
0x4a005620
,
dra7_dsp2_clkctrl_regs
},
{
0x4a005720
,
dra7_rtc_clkctrl_regs
},
{
0x4a005720
,
dra7_rtc_clkctrl_regs
},
{
0x4a005760
,
dra7_vpe_clkctrl_regs
},
{
0x4a008620
,
dra7_coreaon_clkctrl_regs
},
{
0x4a008620
,
dra7_coreaon_clkctrl_regs
},
{
0x4a008720
,
dra7_l3main1_clkctrl_regs
},
{
0x4a008720
,
dra7_l3main1_clkctrl_regs
},
{
0x4a008920
,
dra7_ipu2_clkctrl_regs
},
{
0x4a008920
,
dra7_ipu2_clkctrl_regs
},
...
@@ -777,7 +835,9 @@ const struct omap_clkctrl_data dra7_clkctrl_data[] __initconst = {
...
@@ -777,7 +835,9 @@ const struct omap_clkctrl_data dra7_clkctrl_data[] __initconst = {
{
0x4a008c00
,
dra7_atl_clkctrl_regs
},
{
0x4a008c00
,
dra7_atl_clkctrl_regs
},
{
0x4a008d20
,
dra7_l4cfg_clkctrl_regs
},
{
0x4a008d20
,
dra7_l4cfg_clkctrl_regs
},
{
0x4a008e20
,
dra7_l3instr_clkctrl_regs
},
{
0x4a008e20
,
dra7_l3instr_clkctrl_regs
},
{
0x4a009020
,
dra7_cam_clkctrl_regs
},
{
0x4a009120
,
dra7_dss_clkctrl_regs
},
{
0x4a009120
,
dra7_dss_clkctrl_regs
},
{
0x4a009220
,
dra7_gpu_clkctrl_regs
},
{
0x4a009320
,
dra7_l3init_clkctrl_regs
},
{
0x4a009320
,
dra7_l3init_clkctrl_regs
},
{
0x4a0093b0
,
dra7_pcie_clkctrl_regs
},
{
0x4a0093b0
,
dra7_pcie_clkctrl_regs
},
{
0x4a0093d0
,
dra7_gmac_clkctrl_regs
},
{
0x4a0093d0
,
dra7_gmac_clkctrl_regs
},
...
...
drivers/clk/ti/clk.c
View file @
885d21e4
...
@@ -171,7 +171,9 @@ void __init ti_dt_clocks_register(struct ti_dt_clk oclks[])
...
@@ -171,7 +171,9 @@ void __init ti_dt_clocks_register(struct ti_dt_clk oclks[])
node
=
of_find_node_by_name
(
NULL
,
buf
);
node
=
of_find_node_by_name
(
NULL
,
buf
);
if
(
num_args
&&
compat_mode
)
{
if
(
num_args
&&
compat_mode
)
{
parent
=
node
;
parent
=
node
;
node
=
of_get_child_by_name
(
parent
,
"clk"
);
node
=
of_get_child_by_name
(
parent
,
"clock"
);
if
(
!
node
)
node
=
of_get_child_by_name
(
parent
,
"clk"
);
of_node_put
(
parent
);
of_node_put
(
parent
);
}
}
...
...
drivers/clk/ti/clkctrl.c
View file @
885d21e4
...
@@ -440,6 +440,63 @@ static void __init _clkctrl_add_provider(void *data,
...
@@ -440,6 +440,63 @@ static void __init _clkctrl_add_provider(void *data,
of_clk_add_hw_provider
(
np
,
_ti_omap4_clkctrl_xlate
,
data
);
of_clk_add_hw_provider
(
np
,
_ti_omap4_clkctrl_xlate
,
data
);
}
}
/* Get clock name based on compatible string for clkctrl */
static
char
*
__init
clkctrl_get_name
(
struct
device_node
*
np
)
{
struct
property
*
prop
;
const
int
prefix_len
=
11
;
const
char
*
compat
;
char
*
name
;
of_property_for_each_string
(
np
,
"compatible"
,
prop
,
compat
)
{
if
(
!
strncmp
(
"ti,clkctrl-"
,
compat
,
prefix_len
))
{
/* Two letter minimum name length for l3, l4 etc */
if
(
strnlen
(
compat
+
prefix_len
,
16
)
<
2
)
continue
;
name
=
kasprintf
(
GFP_KERNEL
,
"%s"
,
compat
+
prefix_len
);
if
(
!
name
)
continue
;
strreplace
(
name
,
'-'
,
'_'
);
return
name
;
}
}
of_node_put
(
np
);
return
NULL
;
}
/* Get clkctrl clock base name based on clkctrl_name or dts node */
static
const
char
*
__init
clkctrl_get_clock_name
(
struct
device_node
*
np
,
const
char
*
clkctrl_name
,
int
offset
,
int
index
,
bool
legacy_naming
)
{
char
*
clock_name
;
/* l4per-clkctrl:1234:0 style naming based on clkctrl_name */
if
(
clkctrl_name
&&
!
legacy_naming
)
{
clock_name
=
kasprintf
(
GFP_KERNEL
,
"%s-clkctrl:%04x:%d"
,
clkctrl_name
,
offset
,
index
);
strreplace
(
clock_name
,
'_'
,
'-'
);
return
clock_name
;
}
/* l4per:1234:0 old style naming based on clkctrl_name */
if
(
clkctrl_name
)
return
kasprintf
(
GFP_KERNEL
,
"%s_cm:clk:%04x:%d"
,
clkctrl_name
,
offset
,
index
);
/* l4per_cm:1234:0 old style naming based on parent node name */
if
(
legacy_naming
)
return
kasprintf
(
GFP_KERNEL
,
"%pOFn:clk:%04x:%d"
,
np
->
parent
,
offset
,
index
);
/* l4per-clkctrl:1234:0 style naming based on node name */
return
kasprintf
(
GFP_KERNEL
,
"%pOFn:%04x:%d"
,
np
,
offset
,
index
);
}
static
void
__init
_ti_omap4_clkctrl_setup
(
struct
device_node
*
node
)
static
void
__init
_ti_omap4_clkctrl_setup
(
struct
device_node
*
node
)
{
{
struct
omap_clkctrl_provider
*
provider
;
struct
omap_clkctrl_provider
*
provider
;
...
@@ -448,8 +505,10 @@ static void __init _ti_omap4_clkctrl_setup(struct device_node *node)
...
@@ -448,8 +505,10 @@ static void __init _ti_omap4_clkctrl_setup(struct device_node *node)
struct
clk_init_data
init
=
{
NULL
};
struct
clk_init_data
init
=
{
NULL
};
struct
clk_hw_omap
*
hw
;
struct
clk_hw_omap
*
hw
;
struct
clk
*
clk
;
struct
clk
*
clk
;
struct
omap_clkctrl_clk
*
clkctrl_clk
;
struct
omap_clkctrl_clk
*
clkctrl_clk
=
NULL
;
const
__be32
*
addrp
;
const
__be32
*
addrp
;
bool
legacy_naming
;
char
*
clkctrl_name
;
u32
addr
;
u32
addr
;
int
ret
;
int
ret
;
char
*
c
;
char
*
c
;
...
@@ -537,7 +596,19 @@ static void __init _ti_omap4_clkctrl_setup(struct device_node *node)
...
@@ -537,7 +596,19 @@ static void __init _ti_omap4_clkctrl_setup(struct device_node *node)
provider
->
base
=
of_iomap
(
node
,
0
);
provider
->
base
=
of_iomap
(
node
,
0
);
if
(
ti_clk_get_features
()
->
flags
&
TI_CLK_CLKCTRL_COMPAT
)
{
legacy_naming
=
ti_clk_get_features
()
->
flags
&
TI_CLK_CLKCTRL_COMPAT
;
clkctrl_name
=
clkctrl_get_name
(
node
);
if
(
clkctrl_name
)
{
provider
->
clkdm_name
=
kasprintf
(
GFP_KERNEL
,
"%s_clkdm"
,
clkctrl_name
);
goto
clkdm_found
;
}
/*
* The code below can be removed when all clkctrl nodes use domain
* specific compatible proprerty and standard clock node naming
*/
if
(
legacy_naming
)
{
provider
->
clkdm_name
=
kasprintf
(
GFP_KERNEL
,
"%pOFnxxx"
,
node
->
parent
);
provider
->
clkdm_name
=
kasprintf
(
GFP_KERNEL
,
"%pOFnxxx"
,
node
->
parent
);
if
(
!
provider
->
clkdm_name
)
{
if
(
!
provider
->
clkdm_name
)
{
kfree
(
provider
);
kfree
(
provider
);
...
@@ -573,7 +644,7 @@ static void __init _ti_omap4_clkctrl_setup(struct device_node *node)
...
@@ -573,7 +644,7 @@ static void __init _ti_omap4_clkctrl_setup(struct device_node *node)
*
c
=
'_'
;
*
c
=
'_'
;
c
++
;
c
++
;
}
}
clkdm_found:
INIT_LIST_HEAD
(
&
provider
->
clocks
);
INIT_LIST_HEAD
(
&
provider
->
clocks
);
/* Generate clocks */
/* Generate clocks */
...
@@ -612,15 +683,15 @@ static void __init _ti_omap4_clkctrl_setup(struct device_node *node)
...
@@ -612,15 +683,15 @@ static void __init _ti_omap4_clkctrl_setup(struct device_node *node)
init
.
flags
=
0
;
init
.
flags
=
0
;
if
(
reg_data
->
flags
&
CLKF_SET_RATE_PARENT
)
if
(
reg_data
->
flags
&
CLKF_SET_RATE_PARENT
)
init
.
flags
|=
CLK_SET_RATE_PARENT
;
init
.
flags
|=
CLK_SET_RATE_PARENT
;
if
(
ti_clk_get_features
()
->
flags
&
TI_CLK_CLKCTRL_COMPAT
)
init
.
name
=
kasprintf
(
GFP_KERNEL
,
"%pOFn:%pOFn:%04x:%d"
,
init
.
name
=
clkctrl_get_clock_name
(
node
,
clkctrl_name
,
node
->
parent
,
node
,
reg_data
->
offset
,
0
,
reg_data
->
offset
,
0
);
legacy_naming
);
else
if
(
!
init
.
name
)
init
.
name
=
kasprintf
(
GFP_KERNEL
,
"%pOFn:%04x:%d"
,
goto
cleanup
;
node
,
reg_data
->
offset
,
0
);
clkctrl_clk
=
kzalloc
(
sizeof
(
*
clkctrl_clk
),
GFP_KERNEL
);
clkctrl_clk
=
kzalloc
(
sizeof
(
*
clkctrl_clk
),
GFP_KERNEL
);
if
(
!
init
.
name
||
!
clkctrl_clk
)
if
(
!
clkctrl_clk
)
goto
cleanup
;
goto
cleanup
;
init
.
ops
=
&
omap4_clkctrl_clk_ops
;
init
.
ops
=
&
omap4_clkctrl_clk_ops
;
...
@@ -642,11 +713,14 @@ static void __init _ti_omap4_clkctrl_setup(struct device_node *node)
...
@@ -642,11 +713,14 @@ static void __init _ti_omap4_clkctrl_setup(struct device_node *node)
if
(
ret
==
-
EPROBE_DEFER
)
if
(
ret
==
-
EPROBE_DEFER
)
ti_clk_retry_init
(
node
,
provider
,
_clkctrl_add_provider
);
ti_clk_retry_init
(
node
,
provider
,
_clkctrl_add_provider
);
kfree
(
clkctrl_name
);
return
;
return
;
cleanup:
cleanup:
kfree
(
hw
);
kfree
(
hw
);
kfree
(
init
.
name
);
kfree
(
init
.
name
);
kfree
(
clkctrl_name
);
kfree
(
clkctrl_clk
);
kfree
(
clkctrl_clk
);
}
}
CLK_OF_DECLARE
(
ti_omap4_clkctrl_clock
,
"ti,clkctrl"
,
CLK_OF_DECLARE
(
ti_omap4_clkctrl_clock
,
"ti,clkctrl"
,
...
...
include/dt-bindings/clock/dra7.h
View file @
885d21e4
...
@@ -29,6 +29,16 @@
...
@@ -29,6 +29,16 @@
#define DRA7_RTC_CLKCTRL_INDEX(offset) ((offset) - DRA7_RTC_CLKCTRL_OFFSET)
#define DRA7_RTC_CLKCTRL_INDEX(offset) ((offset) - DRA7_RTC_CLKCTRL_OFFSET)
#define DRA7_RTCSS_CLKCTRL DRA7_RTC_CLKCTRL_INDEX(0x44)
#define DRA7_RTCSS_CLKCTRL DRA7_RTC_CLKCTRL_INDEX(0x44)
/* vip clocks */
#define DRA7_VIP1_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
#define DRA7_VIP2_CLKCTRL DRA7_CLKCTRL_INDEX(0x28)
#define DRA7_VIP3_CLKCTRL DRA7_CLKCTRL_INDEX(0x30)
/* vpe clocks */
#define DRA7_VPE_CLKCTRL_OFFSET 0x60
#define DRA7_VPE_CLKCTRL_INDEX(offset) ((offset) - DRA7_VPE_CLKCTRL_OFFSET)
#define DRA7_VPE_CLKCTRL DRA7_VPE_CLKCTRL_INDEX(0x64)
/* coreaon clocks */
/* coreaon clocks */
#define DRA7_SMARTREFLEX_MPU_CLKCTRL DRA7_CLKCTRL_INDEX(0x28)
#define DRA7_SMARTREFLEX_MPU_CLKCTRL DRA7_CLKCTRL_INDEX(0x28)
#define DRA7_SMARTREFLEX_CORE_CLKCTRL DRA7_CLKCTRL_INDEX(0x38)
#define DRA7_SMARTREFLEX_CORE_CLKCTRL DRA7_CLKCTRL_INDEX(0x38)
...
@@ -78,6 +88,9 @@
...
@@ -78,6 +88,9 @@
#define DRA7_DSS_CORE_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
#define DRA7_DSS_CORE_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
#define DRA7_BB2D_CLKCTRL DRA7_CLKCTRL_INDEX(0x30)
#define DRA7_BB2D_CLKCTRL DRA7_CLKCTRL_INDEX(0x30)
/* gpu clocks */
#define DRA7_GPU_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
/* l3init clocks */
/* l3init clocks */
#define DRA7_MMC1_CLKCTRL DRA7_CLKCTRL_INDEX(0x28)
#define DRA7_MMC1_CLKCTRL DRA7_CLKCTRL_INDEX(0x28)
#define DRA7_MMC2_CLKCTRL DRA7_CLKCTRL_INDEX(0x30)
#define DRA7_MMC2_CLKCTRL DRA7_CLKCTRL_INDEX(0x30)
...
@@ -192,6 +205,16 @@
...
@@ -192,6 +205,16 @@
/* rtc clocks */
/* rtc clocks */
#define DRA7_RTC_RTCSS_CLKCTRL DRA7_CLKCTRL_INDEX(0x44)
#define DRA7_RTC_RTCSS_CLKCTRL DRA7_CLKCTRL_INDEX(0x44)
/* vip clocks */
#define DRA7_CAM_VIP1_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
#define DRA7_CAM_VIP2_CLKCTRL DRA7_CLKCTRL_INDEX(0x28)
#define DRA7_CAM_VIP3_CLKCTRL DRA7_CLKCTRL_INDEX(0x30)
/* vpe clocks */
#define DRA7_VPE_CLKCTRL_OFFSET 0x60
#define DRA7_VPE_CLKCTRL_INDEX(offset) ((offset) - DRA7_VPE_CLKCTRL_OFFSET)
#define DRA7_VPE_VPE_CLKCTRL DRA7_VPE_CLKCTRL_INDEX(0x64)
/* coreaon clocks */
/* coreaon clocks */
#define DRA7_COREAON_SMARTREFLEX_MPU_CLKCTRL DRA7_CLKCTRL_INDEX(0x28)
#define DRA7_COREAON_SMARTREFLEX_MPU_CLKCTRL DRA7_CLKCTRL_INDEX(0x28)
#define DRA7_COREAON_SMARTREFLEX_CORE_CLKCTRL DRA7_CLKCTRL_INDEX(0x38)
#define DRA7_COREAON_SMARTREFLEX_CORE_CLKCTRL DRA7_CLKCTRL_INDEX(0x38)
...
...
include/dt-bindings/clock/omap4.h
View file @
885d21e4
...
@@ -124,6 +124,17 @@
...
@@ -124,6 +124,17 @@
#define OMAP4_UART4_CLKCTRL OMAP4_CLKCTRL_INDEX(0x158)
#define OMAP4_UART4_CLKCTRL OMAP4_CLKCTRL_INDEX(0x158)
#define OMAP4_MMC5_CLKCTRL OMAP4_CLKCTRL_INDEX(0x160)
#define OMAP4_MMC5_CLKCTRL OMAP4_CLKCTRL_INDEX(0x160)
/* l4_secure clocks */
#define OMAP4_L4_SECURE_CLKCTRL_OFFSET 0x1a0
#define OMAP4_L4_SECURE_CLKCTRL_INDEX(offset) ((offset) - OMAP4_L4_SECURE_CLKCTRL_OFFSET)
#define OMAP4_AES1_CLKCTRL OMAP4_L4_SECURE_CLKCTRL_INDEX(0x1a0)
#define OMAP4_AES2_CLKCTRL OMAP4_L4_SECURE_CLKCTRL_INDEX(0x1a8)
#define OMAP4_DES3DES_CLKCTRL OMAP4_L4_SECURE_CLKCTRL_INDEX(0x1b0)
#define OMAP4_PKA_CLKCTRL OMAP4_L4_SECURE_CLKCTRL_INDEX(0x1b8)
#define OMAP4_RNG_CLKCTRL OMAP4_L4_SECURE_CLKCTRL_INDEX(0x1c0)
#define OMAP4_SHA2MD5_CLKCTRL OMAP4_L4_SECURE_CLKCTRL_INDEX(0x1c8)
#define OMAP4_CRYPTODMA_CLKCTRL OMAP4_L4_SECURE_CLKCTRL_INDEX(0x1d8)
/* l4_wkup clocks */
/* l4_wkup clocks */
#define OMAP4_L4_WKUP_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20)
#define OMAP4_L4_WKUP_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20)
#define OMAP4_WD_TIMER2_CLKCTRL OMAP4_CLKCTRL_INDEX(0x30)
#define OMAP4_WD_TIMER2_CLKCTRL OMAP4_CLKCTRL_INDEX(0x30)
...
...
include/dt-bindings/clock/omap5.h
View file @
885d21e4
...
@@ -16,6 +16,7 @@
...
@@ -16,6 +16,7 @@
/* abe clocks */
/* abe clocks */
#define OMAP5_L4_ABE_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20)
#define OMAP5_L4_ABE_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20)
#define OMAP5_AESS_CLKCTRL OMAP5_CLKCTRL_INDEX(0x28)
#define OMAP5_MCPDM_CLKCTRL OMAP5_CLKCTRL_INDEX(0x30)
#define OMAP5_MCPDM_CLKCTRL OMAP5_CLKCTRL_INDEX(0x30)
#define OMAP5_DMIC_CLKCTRL OMAP5_CLKCTRL_INDEX(0x38)
#define OMAP5_DMIC_CLKCTRL OMAP5_CLKCTRL_INDEX(0x38)
#define OMAP5_MCBSP1_CLKCTRL OMAP5_CLKCTRL_INDEX(0x48)
#define OMAP5_MCBSP1_CLKCTRL OMAP5_CLKCTRL_INDEX(0x48)
...
@@ -86,6 +87,17 @@
...
@@ -86,6 +87,17 @@
#define OMAP5_UART5_CLKCTRL OMAP5_CLKCTRL_INDEX(0x170)
#define OMAP5_UART5_CLKCTRL OMAP5_CLKCTRL_INDEX(0x170)
#define OMAP5_UART6_CLKCTRL OMAP5_CLKCTRL_INDEX(0x178)
#define OMAP5_UART6_CLKCTRL OMAP5_CLKCTRL_INDEX(0x178)
/* l4_secure clocks */
#define OMAP5_L4_SECURE_CLKCTRL_OFFSET 0x1a0
#define OMAP5_L4_SECURE_CLKCTRL_INDEX(offset) ((offset) - OMAP5_L4_SECURE_CLKCTRL_OFFSET)
#define OMAP5_AES1_CLKCTRL OMAP5_L4_SECURE_CLKCTRL_INDEX(0x1a0)
#define OMAP5_AES2_CLKCTRL OMAP5_L4_SECURE_CLKCTRL_INDEX(0x1a8)
#define OMAP5_DES3DES_CLKCTRL OMAP5_L4_SECURE_CLKCTRL_INDEX(0x1b0)
#define OMAP5_FPKA_CLKCTRL OMAP5_L4_SECURE_CLKCTRL_INDEX(0x1b8)
#define OMAP5_RNG_CLKCTRL OMAP5_L4_SECURE_CLKCTRL_INDEX(0x1c0)
#define OMAP5_SHA2MD5_CLKCTRL OMAP5_L4_SECURE_CLKCTRL_INDEX(0x1c8)
#define OMAP5_DMA_CRYPTO_CLKCTRL OMAP5_L4_SECURE_CLKCTRL_INDEX(0x1d8)
/* iva clocks */
/* iva clocks */
#define OMAP5_IVA_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20)
#define OMAP5_IVA_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20)
#define OMAP5_SL2IF_CLKCTRL OMAP5_CLKCTRL_INDEX(0x28)
#define OMAP5_SL2IF_CLKCTRL OMAP5_CLKCTRL_INDEX(0x28)
...
...
include/dt-bindings/clk/ti-dra7-atl.h
→
include/dt-bindings/cl
oc
k/ti-dra7-atl.h
View file @
885d21e4
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