Commit 893cf382 authored by Candice Li's avatar Candice Li Committed by Alex Deucher

drm/amd/amdgpu: remove unnecessary RAS context field

Delete ras_if->name in the RAS ctx structure and remove related lines.
Signed-off-by: default avatarCandice Li <candice.li@amd.com>
Reviewed-by: default avatarJohn Clements <john.clements@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 2bbab7ce
...@@ -615,7 +615,6 @@ int amdgpu_gfx_ras_late_init(struct amdgpu_device *adev) ...@@ -615,7 +615,6 @@ int amdgpu_gfx_ras_late_init(struct amdgpu_device *adev)
adev->gfx.ras_if->block = AMDGPU_RAS_BLOCK__GFX; adev->gfx.ras_if->block = AMDGPU_RAS_BLOCK__GFX;
adev->gfx.ras_if->type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE; adev->gfx.ras_if->type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE;
adev->gfx.ras_if->sub_block_index = 0; adev->gfx.ras_if->sub_block_index = 0;
strcpy(adev->gfx.ras_if->name, "gfx");
} }
fs_info.head = ih_info.head = *adev->gfx.ras_if; fs_info.head = ih_info.head = *adev->gfx.ras_if;
r = amdgpu_ras_late_init(adev, adev->gfx.ras_if, r = amdgpu_ras_late_init(adev, adev->gfx.ras_if,
......
...@@ -41,7 +41,6 @@ int amdgpu_hdp_ras_late_init(struct amdgpu_device *adev) ...@@ -41,7 +41,6 @@ int amdgpu_hdp_ras_late_init(struct amdgpu_device *adev)
adev->hdp.ras_if->block = AMDGPU_RAS_BLOCK__HDP; adev->hdp.ras_if->block = AMDGPU_RAS_BLOCK__HDP;
adev->hdp.ras_if->type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE; adev->hdp.ras_if->type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE;
adev->hdp.ras_if->sub_block_index = 0; adev->hdp.ras_if->sub_block_index = 0;
strcpy(adev->hdp.ras_if->name, "hdp");
} }
ih_info.head = fs_info.head = *adev->hdp.ras_if; ih_info.head = fs_info.head = *adev->hdp.ras_if;
r = amdgpu_ras_late_init(adev, adev->hdp.ras_if, r = amdgpu_ras_late_init(adev, adev->hdp.ras_if,
......
...@@ -41,7 +41,6 @@ int amdgpu_mmhub_ras_late_init(struct amdgpu_device *adev) ...@@ -41,7 +41,6 @@ int amdgpu_mmhub_ras_late_init(struct amdgpu_device *adev)
adev->mmhub.ras_if->block = AMDGPU_RAS_BLOCK__MMHUB; adev->mmhub.ras_if->block = AMDGPU_RAS_BLOCK__MMHUB;
adev->mmhub.ras_if->type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE; adev->mmhub.ras_if->type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE;
adev->mmhub.ras_if->sub_block_index = 0; adev->mmhub.ras_if->sub_block_index = 0;
strcpy(adev->mmhub.ras_if->name, "mmhub");
} }
ih_info.head = fs_info.head = *adev->mmhub.ras_if; ih_info.head = fs_info.head = *adev->mmhub.ras_if;
r = amdgpu_ras_late_init(adev, adev->mmhub.ras_if, r = amdgpu_ras_late_init(adev, adev->mmhub.ras_if,
......
...@@ -39,7 +39,6 @@ int amdgpu_nbio_ras_late_init(struct amdgpu_device *adev) ...@@ -39,7 +39,6 @@ int amdgpu_nbio_ras_late_init(struct amdgpu_device *adev)
adev->nbio.ras_if->block = AMDGPU_RAS_BLOCK__PCIE_BIF; adev->nbio.ras_if->block = AMDGPU_RAS_BLOCK__PCIE_BIF;
adev->nbio.ras_if->type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE; adev->nbio.ras_if->type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE;
adev->nbio.ras_if->sub_block_index = 0; adev->nbio.ras_if->sub_block_index = 0;
strcpy(adev->nbio.ras_if->name, "pcie_bif");
} }
ih_info.head = fs_info.head = *adev->nbio.ras_if; ih_info.head = fs_info.head = *adev->nbio.ras_if;
r = amdgpu_ras_late_init(adev, adev->nbio.ras_if, r = amdgpu_ras_late_init(adev, adev->nbio.ras_if,
......
...@@ -64,7 +64,6 @@ const char *ras_block_string[] = { ...@@ -64,7 +64,6 @@ const char *ras_block_string[] = {
}; };
#define ras_err_str(i) (ras_error_string[ffs(i)]) #define ras_err_str(i) (ras_error_string[ffs(i)])
#define ras_block_str(i) (ras_block_string[i])
#define RAS_DEFAULT_FLAGS (AMDGPU_RAS_FLAG_INIT_BY_VBIOS) #define RAS_DEFAULT_FLAGS (AMDGPU_RAS_FLAG_INIT_BY_VBIOS)
...@@ -530,7 +529,7 @@ static inline void put_obj(struct ras_manager *obj) ...@@ -530,7 +529,7 @@ static inline void put_obj(struct ras_manager *obj)
if (obj && (--obj->use == 0)) if (obj && (--obj->use == 0))
list_del(&obj->node); list_del(&obj->node);
if (obj && (obj->use < 0)) if (obj && (obj->use < 0))
DRM_ERROR("RAS ERROR: Unbalance obj(%s) use\n", obj->head.name); DRM_ERROR("RAS ERROR: Unbalance obj(%s) use\n", ras_block_str(obj->head.block));
} }
/* make one obj and return it. */ /* make one obj and return it. */
...@@ -793,7 +792,6 @@ static int amdgpu_ras_enable_all_features(struct amdgpu_device *adev, ...@@ -793,7 +792,6 @@ static int amdgpu_ras_enable_all_features(struct amdgpu_device *adev,
.type = default_ras_type, .type = default_ras_type,
.sub_block_index = 0, .sub_block_index = 0,
}; };
strcpy(head.name, ras_block_str(i));
if (bypass) { if (bypass) {
/* /*
* bypass psp. vbios enable ras for us. * bypass psp. vbios enable ras for us.
......
...@@ -53,6 +53,9 @@ enum amdgpu_ras_block { ...@@ -53,6 +53,9 @@ enum amdgpu_ras_block {
AMDGPU_RAS_BLOCK__LAST AMDGPU_RAS_BLOCK__LAST
}; };
extern const char *ras_block_string[];
#define ras_block_str(i) (ras_block_string[i])
#define AMDGPU_RAS_BLOCK_COUNT AMDGPU_RAS_BLOCK__LAST #define AMDGPU_RAS_BLOCK_COUNT AMDGPU_RAS_BLOCK__LAST
#define AMDGPU_RAS_BLOCK_MASK ((1ULL << AMDGPU_RAS_BLOCK_COUNT) - 1) #define AMDGPU_RAS_BLOCK_MASK ((1ULL << AMDGPU_RAS_BLOCK_COUNT) - 1)
...@@ -306,8 +309,6 @@ struct ras_common_if { ...@@ -306,8 +309,6 @@ struct ras_common_if {
enum amdgpu_ras_block block; enum amdgpu_ras_block block;
enum amdgpu_ras_error_type type; enum amdgpu_ras_error_type type;
uint32_t sub_block_index; uint32_t sub_block_index;
/* block name */
char name[32];
}; };
struct amdgpu_ras { struct amdgpu_ras {
......
...@@ -105,7 +105,6 @@ int amdgpu_sdma_ras_late_init(struct amdgpu_device *adev, ...@@ -105,7 +105,6 @@ int amdgpu_sdma_ras_late_init(struct amdgpu_device *adev,
adev->sdma.ras_if->block = AMDGPU_RAS_BLOCK__SDMA; adev->sdma.ras_if->block = AMDGPU_RAS_BLOCK__SDMA;
adev->sdma.ras_if->type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE; adev->sdma.ras_if->type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE;
adev->sdma.ras_if->sub_block_index = 0; adev->sdma.ras_if->sub_block_index = 0;
strcpy(adev->sdma.ras_if->name, "sdma");
} }
fs_info.head = ih_info->head = *adev->sdma.ras_if; fs_info.head = ih_info->head = *adev->sdma.ras_if;
......
...@@ -41,7 +41,6 @@ int amdgpu_umc_ras_late_init(struct amdgpu_device *adev) ...@@ -41,7 +41,6 @@ int amdgpu_umc_ras_late_init(struct amdgpu_device *adev)
adev->umc.ras_if->block = AMDGPU_RAS_BLOCK__UMC; adev->umc.ras_if->block = AMDGPU_RAS_BLOCK__UMC;
adev->umc.ras_if->type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE; adev->umc.ras_if->type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE;
adev->umc.ras_if->sub_block_index = 0; adev->umc.ras_if->sub_block_index = 0;
strcpy(adev->umc.ras_if->name, "umc");
} }
ih_info.head = fs_info.head = *adev->umc.ras_if; ih_info.head = fs_info.head = *adev->umc.ras_if;
......
...@@ -663,7 +663,6 @@ static int amdgpu_xgmi_ras_late_init(struct amdgpu_device *adev) ...@@ -663,7 +663,6 @@ static int amdgpu_xgmi_ras_late_init(struct amdgpu_device *adev)
adev->gmc.xgmi.ras_if->block = AMDGPU_RAS_BLOCK__XGMI_WAFL; adev->gmc.xgmi.ras_if->block = AMDGPU_RAS_BLOCK__XGMI_WAFL;
adev->gmc.xgmi.ras_if->type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE; adev->gmc.xgmi.ras_if->type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE;
adev->gmc.xgmi.ras_if->sub_block_index = 0; adev->gmc.xgmi.ras_if->sub_block_index = 0;
strcpy(adev->gmc.xgmi.ras_if->name, "xgmi_wafl");
} }
ih_info.head = fs_info.head = *adev->gmc.xgmi.ras_if; ih_info.head = fs_info.head = *adev->gmc.xgmi.ras_if;
r = amdgpu_ras_late_init(adev, adev->gmc.xgmi.ras_if, r = amdgpu_ras_late_init(adev, adev->gmc.xgmi.ras_if,
......
...@@ -372,13 +372,13 @@ static void nbio_v7_4_handle_ras_controller_intr_no_bifring(struct amdgpu_device ...@@ -372,13 +372,13 @@ static void nbio_v7_4_handle_ras_controller_intr_no_bifring(struct amdgpu_device
"errors detected in %s block, " "errors detected in %s block, "
"no user action is needed.\n", "no user action is needed.\n",
obj->err_data.ce_count, obj->err_data.ce_count,
adev->nbio.ras_if->name); ras_block_str(adev->nbio.ras_if->block));
if (err_data.ue_count) if (err_data.ue_count)
dev_info(adev->dev, "%ld uncorrectable hardware " dev_info(adev->dev, "%ld uncorrectable hardware "
"errors detected in %s block\n", "errors detected in %s block\n",
obj->err_data.ue_count, obj->err_data.ue_count,
adev->nbio.ras_if->name); ras_block_str(adev->nbio.ras_if->block));
} }
dev_info(adev->dev, "RAS controller interrupt triggered " dev_info(adev->dev, "RAS controller interrupt triggered "
......
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