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Commit 89d2bce7 authored by Mark Brown's avatar Mark Brown
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ASoC: fsl_micfil: Driver updates 

Merge series from Sascha Hauer <s.hauer@pengutronix.de>:

Cleanups for the fsl_micfil driver.
parents e18610ea a69d7f1b
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Showing with 297 additions and 465 deletions
drivers/dma/imx-dma.c
View file @ 89d2bce7
...@@ -25,7 +25,7 @@ ...@@ -25,7 +25,7 @@
#include <linux/of_dma.h> #include <linux/of_dma.h>
#include <asm/irq.h> #include <asm/irq.h>
#include <linux/platform_data/dma-imx.h> #include <linux/dma/imx-dma.h>
#include "dmaengine.h" #include "dmaengine.h"
#define IMXDMA_MAX_CHAN_DESCRIPTORS 16 #define IMXDMA_MAX_CHAN_DESCRIPTORS 16
......
drivers/dma/imx-sdma.c
View file @ 89d2bce7
...@@ -14,6 +14,7 @@ ...@@ -14,6 +14,7 @@
#include <linux/iopoll.h> #include <linux/iopoll.h>
#include <linux/module.h> #include <linux/module.h>
#include <linux/types.h> #include <linux/types.h>
#include <linux/bitfield.h>
#include <linux/bitops.h> #include <linux/bitops.h>
#include <linux/mm.h> #include <linux/mm.h>
#include <linux/interrupt.h> #include <linux/interrupt.h>
...@@ -35,7 +36,7 @@ ...@@ -35,7 +36,7 @@
#include <linux/workqueue.h> #include <linux/workqueue.h>
#include <asm/irq.h> #include <asm/irq.h>
#include <linux/platform_data/dma-imx.h> #include <linux/dma/imx-dma.h>
#include <linux/regmap.h> #include <linux/regmap.h>
#include <linux/mfd/syscon.h> #include <linux/mfd/syscon.h>
#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h> #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
...@@ -73,6 +74,7 @@ ...@@ -73,6 +74,7 @@
#define SDMA_CHNENBL0_IMX35 0x200 #define SDMA_CHNENBL0_IMX35 0x200
#define SDMA_CHNENBL0_IMX31 0x080 #define SDMA_CHNENBL0_IMX31 0x080
#define SDMA_CHNPRI_0 0x100 #define SDMA_CHNPRI_0 0x100
#define SDMA_DONE0_CONFIG 0x1000
/* /*
* Buffer descriptor status values. * Buffer descriptor status values.
...@@ -180,6 +182,12 @@ ...@@ -180,6 +182,12 @@
BIT(DMA_MEM_TO_DEV) | \ BIT(DMA_MEM_TO_DEV) | \
BIT(DMA_DEV_TO_DEV)) BIT(DMA_DEV_TO_DEV))
#define SDMA_WATERMARK_LEVEL_N_FIFOS GENMASK(15, 12)
#define SDMA_WATERMARK_LEVEL_SW_DONE BIT(23)
#define SDMA_DONE0_CONFIG_DONE_SEL BIT(7)
#define SDMA_DONE0_CONFIG_DONE_DIS BIT(6)
/** /**
* struct sdma_script_start_addrs - SDMA script start pointers * struct sdma_script_start_addrs - SDMA script start pointers
* *
...@@ -441,6 +449,9 @@ struct sdma_channel { ...@@ -441,6 +449,9 @@ struct sdma_channel {
struct work_struct terminate_worker; struct work_struct terminate_worker;
struct list_head terminated; struct list_head terminated;
bool is_ram_script; bool is_ram_script;
unsigned int n_fifos_src;
unsigned int n_fifos_dst;
bool sw_done;
}; };
#define IMX_DMA_SG_LOOP BIT(0) #define IMX_DMA_SG_LOOP BIT(0)
...@@ -778,6 +789,14 @@ static void sdma_event_enable(struct sdma_channel *sdmac, unsigned int event) ...@@ -778,6 +789,14 @@ static void sdma_event_enable(struct sdma_channel *sdmac, unsigned int event)
val = readl_relaxed(sdma->regs + chnenbl); val = readl_relaxed(sdma->regs + chnenbl);
__set_bit(channel, &val); __set_bit(channel, &val);
writel_relaxed(val, sdma->regs + chnenbl); writel_relaxed(val, sdma->regs + chnenbl);
/* Set SDMA_DONEx_CONFIG is sw_done enabled */
if (sdmac->sw_done) {
val = readl_relaxed(sdma->regs + SDMA_DONE0_CONFIG);
val |= SDMA_DONE0_CONFIG_DONE_SEL;
val &= ~SDMA_DONE0_CONFIG_DONE_DIS;
writel_relaxed(val, sdma->regs + SDMA_DONE0_CONFIG);
}
} }
static void sdma_event_disable(struct sdma_channel *sdmac, unsigned int event) static void sdma_event_disable(struct sdma_channel *sdmac, unsigned int event)
...@@ -940,7 +959,7 @@ static irqreturn_t sdma_int_handler(int irq, void *dev_id) ...@@ -940,7 +959,7 @@ static irqreturn_t sdma_int_handler(int irq, void *dev_id)
/* /*
* sets the pc of SDMA script according to the peripheral type * sets the pc of SDMA script according to the peripheral type
*/ */
static void sdma_get_pc(struct sdma_channel *sdmac, static int sdma_get_pc(struct sdma_channel *sdmac,
enum sdma_peripheral_type peripheral_type) enum sdma_peripheral_type peripheral_type)
{ {
struct sdma_engine *sdma = sdmac->sdma; struct sdma_engine *sdma = sdmac->sdma;
...@@ -1038,14 +1057,22 @@ static void sdma_get_pc(struct sdma_channel *sdmac, ...@@ -1038,14 +1057,22 @@ static void sdma_get_pc(struct sdma_channel *sdmac,
case IMX_DMATYPE_IPU_MEMORY: case IMX_DMATYPE_IPU_MEMORY:
emi_2_per = sdma->script_addrs->ext_mem_2_ipu_addr; emi_2_per = sdma->script_addrs->ext_mem_2_ipu_addr;
break; break;
default: case IMX_DMATYPE_MULTI_SAI:
per_2_emi = sdma->script_addrs->sai_2_mcu_addr;
emi_2_per = sdma->script_addrs->mcu_2_sai_addr;
break; break;
default:
dev_err(sdma->dev, "Unsupported transfer type %d\n",
peripheral_type);
return -EINVAL;
} }
sdmac->pc_from_device = per_2_emi; sdmac->pc_from_device = per_2_emi;
sdmac->pc_to_device = emi_2_per; sdmac->pc_to_device = emi_2_per;
sdmac->device_to_device = per_2_per; sdmac->device_to_device = per_2_per;
sdmac->pc_to_pc = emi_2_emi; sdmac->pc_to_pc = emi_2_emi;
return 0;
} }
static int sdma_load_context(struct sdma_channel *sdmac) static int sdma_load_context(struct sdma_channel *sdmac)
...@@ -1210,9 +1237,26 @@ static void sdma_set_watermarklevel_for_p2p(struct sdma_channel *sdmac) ...@@ -1210,9 +1237,26 @@ static void sdma_set_watermarklevel_for_p2p(struct sdma_channel *sdmac)
sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_CONT; sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_CONT;
} }
static void sdma_set_watermarklevel_for_sais(struct sdma_channel *sdmac)
{
unsigned int n_fifos;
if (sdmac->sw_done)
sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_SW_DONE;
if (sdmac->direction == DMA_DEV_TO_MEM)
n_fifos = sdmac->n_fifos_src;
else
n_fifos = sdmac->n_fifos_dst;
sdmac->watermark_level |=
FIELD_PREP(SDMA_WATERMARK_LEVEL_N_FIFOS, n_fifos);
}
static int sdma_config_channel(struct dma_chan *chan) static int sdma_config_channel(struct dma_chan *chan)
{ {
struct sdma_channel *sdmac = to_sdma_chan(chan); struct sdma_channel *sdmac = to_sdma_chan(chan);
int ret;
sdma_disable_channel(chan); sdma_disable_channel(chan);
...@@ -1233,7 +1277,9 @@ static int sdma_config_channel(struct dma_chan *chan) ...@@ -1233,7 +1277,9 @@ static int sdma_config_channel(struct dma_chan *chan)
break; break;
} }
sdma_get_pc(sdmac, sdmac->peripheral_type); ret = sdma_get_pc(sdmac, sdmac->peripheral_type);
if (ret)
return ret;
if ((sdmac->peripheral_type != IMX_DMATYPE_MEMORY) && if ((sdmac->peripheral_type != IMX_DMATYPE_MEMORY) &&
(sdmac->peripheral_type != IMX_DMATYPE_DSP)) { (sdmac->peripheral_type != IMX_DMATYPE_DSP)) {
...@@ -1243,6 +1289,10 @@ static int sdma_config_channel(struct dma_chan *chan) ...@@ -1243,6 +1289,10 @@ static int sdma_config_channel(struct dma_chan *chan)
sdmac->peripheral_type == IMX_DMATYPE_ASRC) sdmac->peripheral_type == IMX_DMATYPE_ASRC)
sdma_set_watermarklevel_for_p2p(sdmac); sdma_set_watermarklevel_for_p2p(sdmac);
} else { } else {
if (sdmac->peripheral_type ==
IMX_DMATYPE_MULTI_SAI)
sdma_set_watermarklevel_for_sais(sdmac);
__set_bit(sdmac->event_id0, sdmac->event_mask); __set_bit(sdmac->event_id0, sdmac->event_mask);
} }
...@@ -1349,7 +1399,9 @@ static int sdma_alloc_chan_resources(struct dma_chan *chan) ...@@ -1349,7 +1399,9 @@ static int sdma_alloc_chan_resources(struct dma_chan *chan)
mem_data.dma_request2 = 0; mem_data.dma_request2 = 0;
data = &mem_data; data = &mem_data;
sdma_get_pc(sdmac, IMX_DMATYPE_MEMORY); ret = sdma_get_pc(sdmac, IMX_DMATYPE_MEMORY);
if (ret)
return ret;
} }
switch (data->priority) { switch (data->priority) {
...@@ -1698,9 +1750,23 @@ static int sdma_config(struct dma_chan *chan, ...@@ -1698,9 +1750,23 @@ static int sdma_config(struct dma_chan *chan,
struct dma_slave_config *dmaengine_cfg) struct dma_slave_config *dmaengine_cfg)
{ {
struct sdma_channel *sdmac = to_sdma_chan(chan); struct sdma_channel *sdmac = to_sdma_chan(chan);
struct sdma_engine *sdma = sdmac->sdma;
memcpy(&sdmac->slave_config, dmaengine_cfg, sizeof(*dmaengine_cfg)); memcpy(&sdmac->slave_config, dmaengine_cfg, sizeof(*dmaengine_cfg));
if (dmaengine_cfg->peripheral_config) {
struct sdma_peripheral_config *sdmacfg = dmaengine_cfg->peripheral_config;
if (dmaengine_cfg->peripheral_size != sizeof(struct sdma_peripheral_config)) {
dev_err(sdma->dev, "Invalid peripheral size %zu, expected %zu\n",
dmaengine_cfg->peripheral_size,
sizeof(struct sdma_peripheral_config));
return -EINVAL;
}
sdmac->n_fifos_src = sdmacfg->n_fifos_src;
sdmac->n_fifos_dst = sdmacfg->n_fifos_dst;
sdmac->sw_done = sdmacfg->sw_done;
}
/* Set ENBLn earlier to make sure dma request triggered after that */ /* Set ENBLn earlier to make sure dma request triggered after that */
if (sdmac->event_id0 >= sdmac->sdma->drvdata->num_events) if (sdmac->event_id0 >= sdmac->sdma->drvdata->num_events)
return -EINVAL; return -EINVAL;
......
drivers/mmc/host/mxcmmc.c
View file @ 89d2bce7
...@@ -39,7 +39,7 @@ ...@@ -39,7 +39,7 @@
#include <asm/irq.h> #include <asm/irq.h>
#include <linux/platform_data/mmc-mxcmmc.h> #include <linux/platform_data/mmc-mxcmmc.h>
#include <linux/platform_data/dma-imx.h> #include <linux/dma/imx-dma.h>
#define DRIVER_NAME "mxc-mmc" #define DRIVER_NAME "mxc-mmc"
#define MXCMCI_TIMEOUT_MS 10000 #define MXCMCI_TIMEOUT_MS 10000
......
drivers/spi/spi-fsl-lpspi.c
View file @ 89d2bce7
...@@ -20,7 +20,7 @@ ...@@ -20,7 +20,7 @@
#include <linux/of_device.h> #include <linux/of_device.h>
#include <linux/pinctrl/consumer.h> #include <linux/pinctrl/consumer.h>
#include <linux/platform_device.h> #include <linux/platform_device.h>
#include <linux/platform_data/dma-imx.h> #include <linux/dma/imx-dma.h>
#include <linux/pm_runtime.h> #include <linux/pm_runtime.h>
#include <linux/slab.h> #include <linux/slab.h>
#include <linux/spi/spi.h> #include <linux/spi/spi.h>
......
drivers/spi/spi-imx.c
View file @ 89d2bce7
...@@ -24,7 +24,7 @@ ...@@ -24,7 +24,7 @@
#include <linux/of_device.h> #include <linux/of_device.h>
#include <linux/property.h> #include <linux/property.h>
#include <linux/platform_data/dma-imx.h> #include <linux/dma/imx-dma.h>
#define DRIVER_NAME "spi_imx" #define DRIVER_NAME "spi_imx"
......
drivers/tty/serial/imx.c
View file @ 89d2bce7
...@@ -30,7 +30,7 @@ ...@@ -30,7 +30,7 @@
#include <linux/dma-mapping.h> #include <linux/dma-mapping.h>
#include <asm/irq.h> #include <asm/irq.h>
#include <linux/platform_data/dma-imx.h> #include <linux/dma/imx-dma.h>
#include "serial_mctrl_gpio.h" #include "serial_mctrl_gpio.h"
......
drivers/video/fbdev/mx3fb.c
View file @ 89d2bce7
...@@ -26,7 +26,7 @@ ...@@ -26,7 +26,7 @@
#include <linux/dma/ipu-dma.h> #include <linux/dma/ipu-dma.h>
#include <linux/backlight.h> #include <linux/backlight.h>
#include <linux/platform_data/dma-imx.h> #include <linux/dma/imx-dma.h>
#include <linux/platform_data/video-mx3fb.h> #include <linux/platform_data/video-mx3fb.h>
#include <asm/io.h> #include <asm/io.h>
......
include/linux/platform_data/dma-imx.h → include/linux/dma/imx-dma.h
View file @ 89d2bce7
...@@ -3,8 +3,8 @@ ...@@ -3,8 +3,8 @@
* Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved. * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved.
*/ */
#ifndef __ASM_ARCH_MXC_DMA_H__ #ifndef __LINUX_DMA_IMX_H
#define __ASM_ARCH_MXC_DMA_H__ #define __LINUX_DMA_IMX_H
#include <linux/scatterlist.h> #include <linux/scatterlist.h>
#include <linux/device.h> #include <linux/device.h>
...@@ -39,6 +39,7 @@ enum sdma_peripheral_type { ...@@ -39,6 +39,7 @@ enum sdma_peripheral_type {
IMX_DMATYPE_SSI_DUAL, /* SSI Dual FIFO */ IMX_DMATYPE_SSI_DUAL, /* SSI Dual FIFO */
IMX_DMATYPE_ASRC_SP, /* Shared ASRC */ IMX_DMATYPE_ASRC_SP, /* Shared ASRC */
IMX_DMATYPE_SAI, /* SAI */ IMX_DMATYPE_SAI, /* SAI */
IMX_DMATYPE_MULTI_SAI, /* MULTI FIFOs For Audio */
}; };
enum imx_dma_prio { enum imx_dma_prio {
...@@ -65,4 +66,23 @@ static inline int imx_dma_is_general_purpose(struct dma_chan *chan) ...@@ -65,4 +66,23 @@ static inline int imx_dma_is_general_purpose(struct dma_chan *chan)
!strcmp(chan->device->dev->driver->name, "imx-dma"); !strcmp(chan->device->dev->driver->name, "imx-dma");
} }
#endif /**
* struct sdma_peripheral_config - SDMA config for audio
* @n_fifos_src: Number of FIFOs for recording
* @n_fifos_dst: Number of FIFOs for playback
* @sw_done: Use software done. Needed for PDM (micfil)
*
* Some i.MX Audio devices (SAI, micfil) have multiple successive FIFO
* registers. For multichannel recording/playback the SAI/micfil have
* one FIFO register per channel and the SDMA engine has to read/write
* the next channel from/to the next register and wrap around to the
* first register when all channels are handled. The number of active
* channels must be communicated to the SDMA engine using this struct.
*/
struct sdma_peripheral_config {
int n_fifos_src;
int n_fifos_dst;
bool sw_done;
};
#endif /* __LINUX_DMA_IMX_H */
sound/soc/fsl/fsl_asrc.c
View file @ 89d2bce7
...@@ -11,7 +11,7 @@ ...@@ -11,7 +11,7 @@
#include <linux/dma-mapping.h> #include <linux/dma-mapping.h>
#include <linux/module.h> #include <linux/module.h>
#include <linux/of_platform.h> #include <linux/of_platform.h>
#include <linux/platform_data/dma-imx.h> #include <linux/dma/imx-dma.h>
#include <linux/pm_runtime.h> #include <linux/pm_runtime.h>
#include <sound/dmaengine_pcm.h> #include <sound/dmaengine_pcm.h>
#include <sound/pcm_params.h> #include <sound/pcm_params.h>
......
sound/soc/fsl/fsl_asrc_dma.c
View file @ 89d2bce7
...@@ -8,7 +8,7 @@ ...@@ -8,7 +8,7 @@
#include <linux/dma-mapping.h> #include <linux/dma-mapping.h>
#include <linux/module.h> #include <linux/module.h>
#include <linux/platform_data/dma-imx.h> #include <linux/dma/imx-dma.h>
#include <sound/dmaengine_pcm.h> #include <sound/dmaengine_pcm.h>
#include <sound/pcm_params.h> #include <sound/pcm_params.h>
......
sound/soc/fsl/fsl_easrc.h
View file @ 89d2bce7
...@@ -7,7 +7,7 @@ ...@@ -7,7 +7,7 @@
#define _FSL_EASRC_H #define _FSL_EASRC_H
#include <sound/asound.h> #include <sound/asound.h>
#include <linux/platform_data/dma-imx.h> #include <linux/dma/imx-dma.h>
#include "fsl_asrc_common.h" #include "fsl_asrc_common.h"
......
sound/soc/fsl/fsl_micfil.c
View file @ 89d2bce7
// SPDX-License-Identifier: GPL-2.0 // SPDX-License-Identifier: GPL-2.0
// Copyright 2018 NXP // Copyright 2018 NXP
#include <linux/bitfield.h>
#include <linux/clk.h> #include <linux/clk.h>
#include <linux/device.h> #include <linux/device.h>
#include <linux/interrupt.h> #include <linux/interrupt.h>
...@@ -15,6 +16,7 @@ ...@@ -15,6 +16,7 @@
#include <linux/regmap.h> #include <linux/regmap.h>
#include <linux/sysfs.h> #include <linux/sysfs.h>
#include <linux/types.h> #include <linux/types.h>
#include <linux/dma/imx-dma.h>
#include <sound/dmaengine_pcm.h> #include <sound/dmaengine_pcm.h>
#include <sound/pcm.h> #include <sound/pcm.h>
#include <sound/soc.h> #include <sound/soc.h>
...@@ -22,10 +24,17 @@ ...@@ -22,10 +24,17 @@
#include <sound/core.h> #include <sound/core.h>
#include "fsl_micfil.h" #include "fsl_micfil.h"
#include "imx-pcm.h"
#define FSL_MICFIL_RATES SNDRV_PCM_RATE_8000_48000 #define MICFIL_OSR_DEFAULT 16
#define FSL_MICFIL_FORMATS (SNDRV_PCM_FMTBIT_S16_LE)
enum quality {
QUALITY_HIGH,
QUALITY_MEDIUM,
QUALITY_LOW,
QUALITY_VLOW0,
QUALITY_VLOW1,
QUALITY_VLOW2,
};
struct fsl_micfil { struct fsl_micfil {
struct platform_device *pdev; struct platform_device *pdev;
...@@ -34,13 +43,11 @@ struct fsl_micfil { ...@@ -34,13 +43,11 @@ struct fsl_micfil {
struct clk *busclk; struct clk *busclk;
struct clk *mclk; struct clk *mclk;
struct snd_dmaengine_dai_dma_data dma_params_rx; struct snd_dmaengine_dai_dma_data dma_params_rx;
struct sdma_peripheral_config sdmacfg;
unsigned int dataline; unsigned int dataline;
char name[32]; char name[32];
int irq[MICFIL_IRQ_LINES]; int irq[MICFIL_IRQ_LINES];
unsigned int mclk_streams; enum quality quality;
int quality; /*QUALITY 2-0 bits */
bool slave_mode;
int channel_gain[8];
}; };
struct fsl_micfil_soc_data { struct fsl_micfil_soc_data {
...@@ -63,29 +70,73 @@ static const struct of_device_id fsl_micfil_dt_ids[] = { ...@@ -63,29 +70,73 @@ static const struct of_device_id fsl_micfil_dt_ids[] = {
}; };
MODULE_DEVICE_TABLE(of, fsl_micfil_dt_ids); MODULE_DEVICE_TABLE(of, fsl_micfil_dt_ids);
/* Table 5. Quality Modes
* Medium 0 0 0
* High 0 0 1
* Very Low 2 1 0 0
* Very Low 1 1 0 1
* Very Low 0 1 1 0
* Low 1 1 1
*/
static const char * const micfil_quality_select_texts[] = { static const char * const micfil_quality_select_texts[] = {
"Medium", "High", [QUALITY_HIGH] = "High",
"N/A", "N/A", [QUALITY_MEDIUM] = "Medium",
"VLow2", "VLow1", [QUALITY_LOW] = "Low",
"VLow0", "Low", [QUALITY_VLOW0] = "VLow0",
[QUALITY_VLOW1] = "Vlow1",
[QUALITY_VLOW2] = "Vlow2",
}; };
static const struct soc_enum fsl_micfil_quality_enum = static const struct soc_enum fsl_micfil_quality_enum =
SOC_ENUM_SINGLE(REG_MICFIL_CTRL2, SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(micfil_quality_select_texts),
MICFIL_CTRL2_QSEL_SHIFT,
ARRAY_SIZE(micfil_quality_select_texts),
micfil_quality_select_texts); micfil_quality_select_texts);
static DECLARE_TLV_DB_SCALE(gain_tlv, 0, 100, 0); static DECLARE_TLV_DB_SCALE(gain_tlv, 0, 100, 0);
static int micfil_set_quality(struct fsl_micfil *micfil)
{
u32 qsel;
switch (micfil->quality) {
case QUALITY_HIGH:
qsel = MICFIL_QSEL_HIGH_QUALITY;
break;
case QUALITY_MEDIUM:
qsel = MICFIL_QSEL_MEDIUM_QUALITY;
break;
case QUALITY_LOW:
qsel = MICFIL_QSEL_LOW_QUALITY;
break;
case QUALITY_VLOW0:
qsel = MICFIL_QSEL_VLOW0_QUALITY;
break;
case QUALITY_VLOW1:
qsel = MICFIL_QSEL_VLOW1_QUALITY;
break;
case QUALITY_VLOW2:
qsel = MICFIL_QSEL_VLOW2_QUALITY;
break;
}
return regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL2,
MICFIL_CTRL2_QSEL,
FIELD_PREP(MICFIL_CTRL2_QSEL, qsel));
}
static int micfil_quality_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
struct fsl_micfil *micfil = snd_soc_component_get_drvdata(cmpnt);
ucontrol->value.integer.value[0] = micfil->quality;
return 0;
}
static int micfil_quality_set(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
struct fsl_micfil *micfil = snd_soc_component_get_drvdata(cmpnt);
micfil->quality = ucontrol->value.integer.value[0];
return micfil_set_quality(micfil);
}
static const struct snd_kcontrol_new fsl_micfil_snd_controls[] = { static const struct snd_kcontrol_new fsl_micfil_snd_controls[] = {
SOC_SINGLE_SX_TLV("CH0 Volume", REG_MICFIL_OUT_CTRL, SOC_SINGLE_SX_TLV("CH0 Volume", REG_MICFIL_OUT_CTRL,
MICFIL_OUTGAIN_CHX_SHIFT(0), 0xF, 0x7, gain_tlv), MICFIL_OUTGAIN_CHX_SHIFT(0), 0xF, 0x7, gain_tlv),
...@@ -105,64 +156,9 @@ static const struct snd_kcontrol_new fsl_micfil_snd_controls[] = { ...@@ -105,64 +156,9 @@ static const struct snd_kcontrol_new fsl_micfil_snd_controls[] = {
MICFIL_OUTGAIN_CHX_SHIFT(7), 0xF, 0x7, gain_tlv), MICFIL_OUTGAIN_CHX_SHIFT(7), 0xF, 0x7, gain_tlv),
SOC_ENUM_EXT("MICFIL Quality Select", SOC_ENUM_EXT("MICFIL Quality Select",
fsl_micfil_quality_enum, fsl_micfil_quality_enum,
snd_soc_get_enum_double, snd_soc_put_enum_double), micfil_quality_get, micfil_quality_set),
}; };
static inline int get_pdm_clk(struct fsl_micfil *micfil,
unsigned int rate)
{
u32 ctrl2_reg;
int qsel, osr;
int bclk;
regmap_read(micfil->regmap, REG_MICFIL_CTRL2, &ctrl2_reg);
osr = 16 - ((ctrl2_reg & MICFIL_CTRL2_CICOSR_MASK)
>> MICFIL_CTRL2_CICOSR_SHIFT);
regmap_read(micfil->regmap, REG_MICFIL_CTRL2, &ctrl2_reg);
qsel = ctrl2_reg & MICFIL_CTRL2_QSEL_MASK;
switch (qsel) {
case MICFIL_HIGH_QUALITY:
bclk = rate * 8 * osr / 2; /* kfactor = 0.5 */
break;
case MICFIL_MEDIUM_QUALITY:
case MICFIL_VLOW0_QUALITY:
bclk = rate * 4 * osr * 1; /* kfactor = 1 */
break;
case MICFIL_LOW_QUALITY:
case MICFIL_VLOW1_QUALITY:
bclk = rate * 2 * osr * 2; /* kfactor = 2 */
break;
case MICFIL_VLOW2_QUALITY:
bclk = rate * osr * 4; /* kfactor = 4 */
break;
default:
dev_err(&micfil->pdev->dev,
"Please make sure you select a valid quality.\n");
bclk = -1;
break;
}
return bclk;
}
static inline int get_clk_div(struct fsl_micfil *micfil,
unsigned int rate)
{
u32 ctrl2_reg;
long mclk_rate;
int clk_div;
regmap_read(micfil->regmap, REG_MICFIL_CTRL2, &ctrl2_reg);
mclk_rate = clk_get_rate(micfil->mclk);
clk_div = mclk_rate / (get_pdm_clk(micfil, rate) * 2);
return clk_div;
}
/* The SRES is a self-negated bit which provides the CPU with the /* The SRES is a self-negated bit which provides the CPU with the
* capability to initialize the PDM Interface module through the * capability to initialize the PDM Interface module through the
* slave-bus interface. This bit always reads as zero, and this * slave-bus interface. This bit always reads as zero, and this
...@@ -173,45 +169,19 @@ static int fsl_micfil_reset(struct device *dev) ...@@ -173,45 +169,19 @@ static int fsl_micfil_reset(struct device *dev)
struct fsl_micfil *micfil = dev_get_drvdata(dev); struct fsl_micfil *micfil = dev_get_drvdata(dev);
int ret; int ret;
ret = regmap_update_bits(micfil->regmap, ret = regmap_clear_bits(micfil->regmap, REG_MICFIL_CTRL1,
REG_MICFIL_CTRL1, MICFIL_CTRL1_MDIS);
MICFIL_CTRL1_MDIS_MASK, if (ret)
0);
if (ret) {
dev_err(dev, "failed to clear MDIS bit %d\n", ret);
return ret; return ret;
}
ret = regmap_update_bits(micfil->regmap, ret = regmap_set_bits(micfil->regmap, REG_MICFIL_CTRL1,
REG_MICFIL_CTRL1,
MICFIL_CTRL1_SRES_MASK,
MICFIL_CTRL1_SRES); MICFIL_CTRL1_SRES);
if (ret) { if (ret)
dev_err(dev, "failed to reset MICFIL: %d\n", ret);
return ret; return ret;
}
return 0; return 0;
} }
static int fsl_micfil_set_mclk_rate(struct fsl_micfil *micfil,
unsigned int freq)
{
struct device *dev = &micfil->pdev->dev;
int ret;
clk_disable_unprepare(micfil->mclk);
ret = clk_set_rate(micfil->mclk, freq * 1024);
if (ret)
dev_warn(dev, "failed to set rate (%u): %d\n",
freq * 1024, ret);
clk_prepare_enable(micfil->mclk);
return ret;
}
static int fsl_micfil_startup(struct snd_pcm_substream *substream, static int fsl_micfil_startup(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai) struct snd_soc_dai *dai)
{ {
...@@ -249,42 +219,32 @@ static int fsl_micfil_trigger(struct snd_pcm_substream *substream, int cmd, ...@@ -249,42 +219,32 @@ static int fsl_micfil_trigger(struct snd_pcm_substream *substream, int cmd,
* 11 - reserved * 11 - reserved
*/ */
ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL1, ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL1,
MICFIL_CTRL1_DISEL_MASK, MICFIL_CTRL1_DISEL,
(1 << MICFIL_CTRL1_DISEL_SHIFT)); FIELD_PREP(MICFIL_CTRL1_DISEL, MICFIL_CTRL1_DISEL_DMA));
if (ret) { if (ret)
dev_err(dev, "failed to update DISEL bits\n");
return ret; return ret;
}
/* Enable the module */ /* Enable the module */
ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL1, ret = regmap_set_bits(micfil->regmap, REG_MICFIL_CTRL1,
MICFIL_CTRL1_PDMIEN_MASK,
MICFIL_CTRL1_PDMIEN); MICFIL_CTRL1_PDMIEN);
if (ret) { if (ret)
dev_err(dev, "failed to enable the module\n");
return ret; return ret;
}
break; break;
case SNDRV_PCM_TRIGGER_STOP: case SNDRV_PCM_TRIGGER_STOP:
case SNDRV_PCM_TRIGGER_SUSPEND: case SNDRV_PCM_TRIGGER_SUSPEND:
case SNDRV_PCM_TRIGGER_PAUSE_PUSH: case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
/* Disable the module */ /* Disable the module */
ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL1, ret = regmap_clear_bits(micfil->regmap, REG_MICFIL_CTRL1,
MICFIL_CTRL1_PDMIEN_MASK, MICFIL_CTRL1_PDMIEN);
0); if (ret)
if (ret) {
dev_err(dev, "failed to enable the module\n");
return ret; return ret;
}
ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL1, ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL1,
MICFIL_CTRL1_DISEL_MASK, MICFIL_CTRL1_DISEL,
(0 << MICFIL_CTRL1_DISEL_SHIFT)); FIELD_PREP(MICFIL_CTRL1_DISEL, MICFIL_CTRL1_DISEL_DISABLE));
if (ret) { if (ret)
dev_err(dev, "failed to update DISEL bits\n");
return ret; return ret;
}
break; break;
default: default:
return -EINVAL; return -EINVAL;
...@@ -292,39 +252,6 @@ static int fsl_micfil_trigger(struct snd_pcm_substream *substream, int cmd, ...@@ -292,39 +252,6 @@ static int fsl_micfil_trigger(struct snd_pcm_substream *substream, int cmd,
return 0; return 0;
} }
static int fsl_set_clock_params(struct device *dev, unsigned int rate)
{
struct fsl_micfil *micfil = dev_get_drvdata(dev);
int clk_div;
int ret;
ret = fsl_micfil_set_mclk_rate(micfil, rate);
if (ret < 0)
dev_err(dev, "failed to set mclk[%lu] to rate %u\n",
clk_get_rate(micfil->mclk), rate);
/* set CICOSR */
ret |= regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL2,
MICFIL_CTRL2_CICOSR_MASK,
MICFIL_CTRL2_OSR_DEFAULT);
if (ret)
dev_err(dev, "failed to set CICOSR in reg 0x%X\n",
REG_MICFIL_CTRL2);
/* set CLK_DIV */
clk_div = get_clk_div(micfil, rate);
if (clk_div < 0)
ret = -EINVAL;
ret |= regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL2,
MICFIL_CTRL2_CLKDIV_MASK, clk_div);
if (ret)
dev_err(dev, "failed to set CLKDIV in reg 0x%X\n",
REG_MICFIL_CTRL2);
return ret;
}
static int fsl_micfil_hw_params(struct snd_pcm_substream *substream, static int fsl_micfil_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params, struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai) struct snd_soc_dai *dai)
...@@ -332,97 +259,69 @@ static int fsl_micfil_hw_params(struct snd_pcm_substream *substream, ...@@ -332,97 +259,69 @@ static int fsl_micfil_hw_params(struct snd_pcm_substream *substream,
struct fsl_micfil *micfil = snd_soc_dai_get_drvdata(dai); struct fsl_micfil *micfil = snd_soc_dai_get_drvdata(dai);
unsigned int channels = params_channels(params); unsigned int channels = params_channels(params);
unsigned int rate = params_rate(params); unsigned int rate = params_rate(params);
struct device *dev = &micfil->pdev->dev; int clk_div = 8;
int osr = MICFIL_OSR_DEFAULT;
int ret; int ret;
/* 1. Disable the module */ /* 1. Disable the module */
ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL1, ret = regmap_clear_bits(micfil->regmap, REG_MICFIL_CTRL1,
MICFIL_CTRL1_PDMIEN_MASK, 0); MICFIL_CTRL1_PDMIEN);
if (ret) { if (ret)
dev_err(dev, "failed to disable the module\n");
return ret; return ret;
}
/* enable channels */ /* enable channels */
ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL1, ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL1,
0xFF, ((1 << channels) - 1)); 0xFF, ((1 << channels) - 1));
if (ret) { if (ret)
dev_err(dev, "failed to enable channels %d, reg 0x%X\n", ret,
REG_MICFIL_CTRL1);
return ret; return ret;
}
ret = fsl_set_clock_params(dev, rate); ret = clk_set_rate(micfil->mclk, rate * clk_div * osr * 8);
if (ret < 0) { if (ret)
dev_err(dev, "Failed to set clock parameters [%d]\n", ret);
return ret; return ret;
}
micfil->dma_params_rx.maxburst = channels * MICFIL_DMA_MAXBURST_RX;
return 0; ret = micfil_set_quality(micfil);
} if (ret)
return ret;
static int fsl_micfil_set_dai_sysclk(struct snd_soc_dai *dai, int clk_id,
unsigned int freq, int dir)
{
struct fsl_micfil *micfil = snd_soc_dai_get_drvdata(dai);
struct device *dev = &micfil->pdev->dev;
int ret; ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL2,
MICFIL_CTRL2_CLKDIV | MICFIL_CTRL2_CICOSR,
FIELD_PREP(MICFIL_CTRL2_CLKDIV, clk_div) |
FIELD_PREP(MICFIL_CTRL2_CICOSR, 16 - osr));
micfil->dma_params_rx.peripheral_config = &micfil->sdmacfg;
micfil->dma_params_rx.peripheral_size = sizeof(micfil->sdmacfg);
micfil->sdmacfg.n_fifos_src = channels;
micfil->sdmacfg.sw_done = true;
micfil->dma_params_rx.maxburst = channels * MICFIL_DMA_MAXBURST_RX;
if (!freq)
return 0; return 0;
ret = fsl_micfil_set_mclk_rate(micfil, freq);
if (ret < 0)
dev_err(dev, "failed to set mclk[%lu] to rate %u\n",
clk_get_rate(micfil->mclk), freq);
return ret;
} }
static const struct snd_soc_dai_ops fsl_micfil_dai_ops = { static const struct snd_soc_dai_ops fsl_micfil_dai_ops = {
.startup = fsl_micfil_startup, .startup = fsl_micfil_startup,
.trigger = fsl_micfil_trigger, .trigger = fsl_micfil_trigger,
.hw_params = fsl_micfil_hw_params, .hw_params = fsl_micfil_hw_params,
.set_sysclk = fsl_micfil_set_dai_sysclk,
}; };
static int fsl_micfil_dai_probe(struct snd_soc_dai *cpu_dai) static int fsl_micfil_dai_probe(struct snd_soc_dai *cpu_dai)
{ {
struct fsl_micfil *micfil = dev_get_drvdata(cpu_dai->dev); struct fsl_micfil *micfil = dev_get_drvdata(cpu_dai->dev);
struct device *dev = cpu_dai->dev;
unsigned int val;
int ret; int ret;
int i;
/* set qsel to medium */ micfil->quality = QUALITY_MEDIUM;
ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL2,
MICFIL_CTRL2_QSEL_MASK, MICFIL_MEDIUM_QUALITY);
if (ret) {
dev_err(dev, "failed to set quality mode bits, reg 0x%X\n",
REG_MICFIL_CTRL2);
return ret;
}
/* set default gain to max_gain */ /* set default gain to max_gain */
regmap_write(micfil->regmap, REG_MICFIL_OUT_CTRL, 0x77777777); regmap_write(micfil->regmap, REG_MICFIL_OUT_CTRL, 0x77777777);
for (i = 0; i < 8; i++)
micfil->channel_gain[i] = 0xF;
snd_soc_dai_init_dma_data(cpu_dai, NULL, snd_soc_dai_init_dma_data(cpu_dai, NULL,
&micfil->dma_params_rx); &micfil->dma_params_rx);
/* FIFO Watermark Control - FIFOWMK*/ /* FIFO Watermark Control - FIFOWMK*/
val = MICFIL_FIFO_CTRL_FIFOWMK(micfil->soc->fifo_depth) - 1;
ret = regmap_update_bits(micfil->regmap, REG_MICFIL_FIFO_CTRL, ret = regmap_update_bits(micfil->regmap, REG_MICFIL_FIFO_CTRL,
MICFIL_FIFO_CTRL_FIFOWMK_MASK, MICFIL_FIFO_CTRL_FIFOWMK,
val); FIELD_PREP(MICFIL_FIFO_CTRL_FIFOWMK, micfil->soc->fifo_depth - 1));
if (ret) { if (ret)
dev_err(dev, "failed to set FIFOWMK\n");
return ret; return ret;
}
return 0; return 0;
} }
...@@ -433,8 +332,8 @@ static struct snd_soc_dai_driver fsl_micfil_dai = { ...@@ -433,8 +332,8 @@ static struct snd_soc_dai_driver fsl_micfil_dai = {
.stream_name = "CPU-Capture", .stream_name = "CPU-Capture",
.channels_min = 1, .channels_min = 1,
.channels_max = 8, .channels_max = 8,
.rates = FSL_MICFIL_RATES, .rates = SNDRV_PCM_RATE_8000_48000,
.formats = FSL_MICFIL_FORMATS, .formats = SNDRV_PCM_FMTBIT_S16_LE,
}, },
.ops = &fsl_micfil_dai_ops, .ops = &fsl_micfil_dai_ops,
}; };
...@@ -578,11 +477,11 @@ static irqreturn_t micfil_isr(int irq, void *devid) ...@@ -578,11 +477,11 @@ static irqreturn_t micfil_isr(int irq, void *devid)
regmap_read(micfil->regmap, REG_MICFIL_CTRL1, &ctrl1_reg); regmap_read(micfil->regmap, REG_MICFIL_CTRL1, &ctrl1_reg);
regmap_read(micfil->regmap, REG_MICFIL_FIFO_STAT, &fifo_stat_reg); regmap_read(micfil->regmap, REG_MICFIL_FIFO_STAT, &fifo_stat_reg);
dma_enabled = MICFIL_DMA_ENABLED(ctrl1_reg); dma_enabled = FIELD_GET(MICFIL_CTRL1_DISEL, ctrl1_reg) == MICFIL_CTRL1_DISEL_DMA;
/* Channel 0-7 Output Data Flags */ /* Channel 0-7 Output Data Flags */
for (i = 0; i < MICFIL_OUTPUT_CHANNELS; i++) { for (i = 0; i < MICFIL_OUTPUT_CHANNELS; i++) {
if (stat_reg & MICFIL_STAT_CHXF_MASK(i)) if (stat_reg & MICFIL_STAT_CHXF(i))
dev_dbg(&pdev->dev, dev_dbg(&pdev->dev,
"Data available in Data Channel %d\n", i); "Data available in Data Channel %d\n", i);
/* if DMA is not enabled, field must be written with 1 /* if DMA is not enabled, field must be written with 1
...@@ -591,17 +490,17 @@ static irqreturn_t micfil_isr(int irq, void *devid) ...@@ -591,17 +490,17 @@ static irqreturn_t micfil_isr(int irq, void *devid)
if (!dma_enabled) if (!dma_enabled)
regmap_write_bits(micfil->regmap, regmap_write_bits(micfil->regmap,
REG_MICFIL_STAT, REG_MICFIL_STAT,
MICFIL_STAT_CHXF_MASK(i), MICFIL_STAT_CHXF(i),
1); 1);
} }
for (i = 0; i < MICFIL_FIFO_NUM; i++) { for (i = 0; i < MICFIL_FIFO_NUM; i++) {
if (fifo_stat_reg & MICFIL_FIFO_STAT_FIFOX_OVER_MASK(i)) if (fifo_stat_reg & MICFIL_FIFO_STAT_FIFOX_OVER(i))
dev_dbg(&pdev->dev, dev_dbg(&pdev->dev,
"FIFO Overflow Exception flag for channel %d\n", "FIFO Overflow Exception flag for channel %d\n",
i); i);
if (fifo_stat_reg & MICFIL_FIFO_STAT_FIFOX_UNDER_MASK(i)) if (fifo_stat_reg & MICFIL_FIFO_STAT_FIFOX_UNDER(i))
dev_dbg(&pdev->dev, dev_dbg(&pdev->dev,
"FIFO Underflow Exception flag for channel %d\n", "FIFO Underflow Exception flag for channel %d\n",
i); i);
...@@ -618,16 +517,16 @@ static irqreturn_t micfil_err_isr(int irq, void *devid) ...@@ -618,16 +517,16 @@ static irqreturn_t micfil_err_isr(int irq, void *devid)
regmap_read(micfil->regmap, REG_MICFIL_STAT, &stat_reg); regmap_read(micfil->regmap, REG_MICFIL_STAT, &stat_reg);
if (stat_reg & MICFIL_STAT_BSY_FIL_MASK) if (stat_reg & MICFIL_STAT_BSY_FIL)
dev_dbg(&pdev->dev, "isr: Decimation Filter is running\n"); dev_dbg(&pdev->dev, "isr: Decimation Filter is running\n");
if (stat_reg & MICFIL_STAT_FIR_RDY_MASK) if (stat_reg & MICFIL_STAT_FIR_RDY)
dev_dbg(&pdev->dev, "isr: FIR Filter Data ready\n"); dev_dbg(&pdev->dev, "isr: FIR Filter Data ready\n");
if (stat_reg & MICFIL_STAT_LOWFREQF_MASK) { if (stat_reg & MICFIL_STAT_LOWFREQF) {
dev_dbg(&pdev->dev, "isr: ipg_clk_app is too low\n"); dev_dbg(&pdev->dev, "isr: ipg_clk_app is too low\n");
regmap_write_bits(micfil->regmap, REG_MICFIL_STAT, regmap_write_bits(micfil->regmap, REG_MICFIL_STAT,
MICFIL_STAT_LOWFREQF_MASK, 1); MICFIL_STAT_LOWFREQF, 1);
} }
return IRQ_HANDLED; return IRQ_HANDLED;
...@@ -640,7 +539,6 @@ static int fsl_micfil_probe(struct platform_device *pdev) ...@@ -640,7 +539,6 @@ static int fsl_micfil_probe(struct platform_device *pdev)
struct resource *res; struct resource *res;
void __iomem *regs; void __iomem *regs;
int ret, i; int ret, i;
unsigned long irqflag = 0;
micfil = devm_kzalloc(&pdev->dev, sizeof(*micfil), GFP_KERNEL); micfil = devm_kzalloc(&pdev->dev, sizeof(*micfil), GFP_KERNEL);
if (!micfil) if (!micfil)
...@@ -699,17 +597,13 @@ static int fsl_micfil_probe(struct platform_device *pdev) ...@@ -699,17 +597,13 @@ static int fsl_micfil_probe(struct platform_device *pdev)
/* get IRQs */ /* get IRQs */
for (i = 0; i < MICFIL_IRQ_LINES; i++) { for (i = 0; i < MICFIL_IRQ_LINES; i++) {
micfil->irq[i] = platform_get_irq(pdev, i); micfil->irq[i] = platform_get_irq(pdev, i);
dev_err(&pdev->dev, "GET IRQ: %d\n", micfil->irq[i]);
if (micfil->irq[i] < 0) if (micfil->irq[i] < 0)
return micfil->irq[i]; return micfil->irq[i];
} }
if (of_property_read_bool(np, "fsl,shared-interrupt"))
irqflag = IRQF_SHARED;
/* Digital Microphone interface interrupt */ /* Digital Microphone interface interrupt */
ret = devm_request_irq(&pdev->dev, micfil->irq[0], ret = devm_request_irq(&pdev->dev, micfil->irq[0],
micfil_isr, irqflag, micfil_isr, IRQF_SHARED,
micfil->name, micfil); micfil->name, micfil);
if (ret) { if (ret) {
dev_err(&pdev->dev, "failed to claim mic interface irq %u\n", dev_err(&pdev->dev, "failed to claim mic interface irq %u\n",
...@@ -719,7 +613,7 @@ static int fsl_micfil_probe(struct platform_device *pdev) ...@@ -719,7 +613,7 @@ static int fsl_micfil_probe(struct platform_device *pdev)
/* Digital Microphone interface error interrupt */ /* Digital Microphone interface error interrupt */
ret = devm_request_irq(&pdev->dev, micfil->irq[1], ret = devm_request_irq(&pdev->dev, micfil->irq[1],
micfil_err_isr, irqflag, micfil_err_isr, IRQF_SHARED,
micfil->name, micfil); micfil->name, micfil);
if (ret) { if (ret) {
dev_err(&pdev->dev, "failed to claim mic interface error irq %u\n", dev_err(&pdev->dev, "failed to claim mic interface error irq %u\n",
...@@ -731,7 +625,6 @@ static int fsl_micfil_probe(struct platform_device *pdev) ...@@ -731,7 +625,6 @@ static int fsl_micfil_probe(struct platform_device *pdev)
micfil->dma_params_rx.addr = res->start + REG_MICFIL_DATACH0; micfil->dma_params_rx.addr = res->start + REG_MICFIL_DATACH0;
micfil->dma_params_rx.maxburst = MICFIL_DMA_MAXBURST_RX; micfil->dma_params_rx.maxburst = MICFIL_DMA_MAXBURST_RX;
platform_set_drvdata(pdev, micfil); platform_set_drvdata(pdev, micfil);
pm_runtime_enable(&pdev->dev); pm_runtime_enable(&pdev->dev);
......
sound/soc/fsl/fsl_micfil.h
View file @ 89d2bce7
...@@ -33,240 +33,94 @@ ...@@ -33,240 +33,94 @@
#define REG_MICFIL_VAD0_ZCD 0xA8 #define REG_MICFIL_VAD0_ZCD 0xA8
/* MICFIL Control Register 1 -- REG_MICFILL_CTRL1 0x00 */ /* MICFIL Control Register 1 -- REG_MICFILL_CTRL1 0x00 */
#define MICFIL_CTRL1_MDIS_SHIFT 31 #define MICFIL_CTRL1_MDIS BIT(31)
#define MICFIL_CTRL1_MDIS_MASK BIT(MICFIL_CTRL1_MDIS_SHIFT) #define MICFIL_CTRL1_DOZEN BIT(30)
#define MICFIL_CTRL1_MDIS BIT(MICFIL_CTRL1_MDIS_SHIFT) #define MICFIL_CTRL1_PDMIEN BIT(29)
#define MICFIL_CTRL1_DOZEN_SHIFT 30 #define MICFIL_CTRL1_DBG BIT(28)
#define MICFIL_CTRL1_DOZEN_MASK BIT(MICFIL_CTRL1_DOZEN_SHIFT) #define MICFIL_CTRL1_SRES BIT(27)
#define MICFIL_CTRL1_DOZEN BIT(MICFIL_CTRL1_DOZEN_SHIFT) #define MICFIL_CTRL1_DBGE BIT(26)
#define MICFIL_CTRL1_PDMIEN_SHIFT 29
#define MICFIL_CTRL1_PDMIEN_MASK BIT(MICFIL_CTRL1_PDMIEN_SHIFT) #define MICFIL_CTRL1_DISEL_DISABLE 0
#define MICFIL_CTRL1_PDMIEN BIT(MICFIL_CTRL1_PDMIEN_SHIFT) #define MICFIL_CTRL1_DISEL_DMA 1
#define MICFIL_CTRL1_DBG_SHIFT 28 #define MICFIL_CTRL1_DISEL_IRQ 2
#define MICFIL_CTRL1_DBG_MASK BIT(MICFIL_CTRL1_DBG_SHIFT) #define MICFIL_CTRL1_DISEL GENMASK(25, 24)
#define MICFIL_CTRL1_DBG BIT(MICFIL_CTRL1_DBG_SHIFT) #define MICFIL_CTRL1_ERREN BIT(23)
#define MICFIL_CTRL1_SRES_SHIFT 27 #define MICFIL_CTRL1_CHEN(ch) BIT(ch)
#define MICFIL_CTRL1_SRES_MASK BIT(MICFIL_CTRL1_SRES_SHIFT)
#define MICFIL_CTRL1_SRES BIT(MICFIL_CTRL1_SRES_SHIFT)
#define MICFIL_CTRL1_DBGE_SHIFT 26
#define MICFIL_CTRL1_DBGE_MASK BIT(MICFIL_CTRL1_DBGE_SHIFT)
#define MICFIL_CTRL1_DBGE BIT(MICFIL_CTRL1_DBGE_SHIFT)
#define MICFIL_CTRL1_DISEL_SHIFT 24
#define MICFIL_CTRL1_DISEL_WIDTH 2
#define MICFIL_CTRL1_DISEL_MASK ((BIT(MICFIL_CTRL1_DISEL_WIDTH) - 1) \
<< MICFIL_CTRL1_DISEL_SHIFT)
#define MICFIL_CTRL1_DISEL(v) (((v) << MICFIL_CTRL1_DISEL_SHIFT) \
& MICFIL_CTRL1_DISEL_MASK)
#define MICFIL_CTRL1_ERREN_SHIFT 23
#define MICFIL_CTRL1_ERREN_MASK BIT(MICFIL_CTRL1_ERREN_SHIFT)
#define MICFIL_CTRL1_ERREN BIT(MICFIL_CTRL1_ERREN_SHIFT)
#define MICFIL_CTRL1_CHEN_SHIFT 0
#define MICFIL_CTRL1_CHEN_WIDTH 8
#define MICFIL_CTRL1_CHEN_MASK(x) (BIT(x) << MICFIL_CTRL1_CHEN_SHIFT)
#define MICFIL_CTRL1_CHEN(x) (MICFIL_CTRL1_CHEN_MASK(x))
/* MICFIL Control Register 2 -- REG_MICFILL_CTRL2 0x04 */ /* MICFIL Control Register 2 -- REG_MICFILL_CTRL2 0x04 */
#define MICFIL_CTRL2_QSEL_SHIFT 25 #define MICFIL_CTRL2_QSEL_SHIFT 25
#define MICFIL_CTRL2_QSEL_WIDTH 3 #define MICFIL_CTRL2_QSEL GENMASK(27, 25)
#define MICFIL_CTRL2_QSEL_MASK ((BIT(MICFIL_CTRL2_QSEL_WIDTH) - 1) \ #define MICFIL_QSEL_MEDIUM_QUALITY 0
<< MICFIL_CTRL2_QSEL_SHIFT) #define MICFIL_QSEL_HIGH_QUALITY 1
#define MICFIL_HIGH_QUALITY BIT(MICFIL_CTRL2_QSEL_SHIFT) #define MICFIL_QSEL_LOW_QUALITY 7
#define MICFIL_MEDIUM_QUALITY (0 << MICFIL_CTRL2_QSEL_SHIFT) #define MICFIL_QSEL_VLOW0_QUALITY 6
#define MICFIL_LOW_QUALITY (7 << MICFIL_CTRL2_QSEL_SHIFT) #define MICFIL_QSEL_VLOW1_QUALITY 5
#define MICFIL_VLOW0_QUALITY (6 << MICFIL_CTRL2_QSEL_SHIFT) #define MICFIL_QSEL_VLOW2_QUALITY 4
#define MICFIL_VLOW1_QUALITY (5 << MICFIL_CTRL2_QSEL_SHIFT)
#define MICFIL_VLOW2_QUALITY (4 << MICFIL_CTRL2_QSEL_SHIFT)
#define MICFIL_CTRL2_CICOSR_SHIFT 16 #define MICFIL_CTRL2_CICOSR GENMASK(19, 16)
#define MICFIL_CTRL2_CICOSR_WIDTH 4 #define MICFIL_CTRL2_CLKDIV GENMASK(7, 0)
#define MICFIL_CTRL2_CICOSR_MASK ((BIT(MICFIL_CTRL2_CICOSR_WIDTH) - 1) \
<< MICFIL_CTRL2_CICOSR_SHIFT)
#define MICFIL_CTRL2_CICOSR(v) (((v) << MICFIL_CTRL2_CICOSR_SHIFT) \
& MICFIL_CTRL2_CICOSR_MASK)
#define MICFIL_CTRL2_CLKDIV_SHIFT 0
#define MICFIL_CTRL2_CLKDIV_WIDTH 8
#define MICFIL_CTRL2_CLKDIV_MASK ((BIT(MICFIL_CTRL2_CLKDIV_WIDTH) - 1) \
<< MICFIL_CTRL2_CLKDIV_SHIFT)
#define MICFIL_CTRL2_CLKDIV(v) (((v) << MICFIL_CTRL2_CLKDIV_SHIFT) \
& MICFIL_CTRL2_CLKDIV_MASK)
/* MICFIL Status Register -- REG_MICFIL_STAT 0x08 */ /* MICFIL Status Register -- REG_MICFIL_STAT 0x08 */
#define MICFIL_STAT_BSY_FIL_SHIFT 31 #define MICFIL_STAT_BSY_FIL BIT(31)
#define MICFIL_STAT_BSY_FIL_MASK BIT(MICFIL_STAT_BSY_FIL_SHIFT) #define MICFIL_STAT_FIR_RDY BIT(30)
#define MICFIL_STAT_BSY_FIL BIT(MICFIL_STAT_BSY_FIL_SHIFT) #define MICFIL_STAT_LOWFREQF BIT(29)
#define MICFIL_STAT_FIR_RDY_SHIFT 30 #define MICFIL_STAT_CHXF(ch) BIT(ch)
#define MICFIL_STAT_FIR_RDY_MASK BIT(MICFIL_STAT_FIR_RDY_SHIFT)
#define MICFIL_STAT_FIR_RDY BIT(MICFIL_STAT_FIR_RDY_SHIFT)
#define MICFIL_STAT_LOWFREQF_SHIFT 29
#define MICFIL_STAT_LOWFREQF_MASK BIT(MICFIL_STAT_LOWFREQF_SHIFT)
#define MICFIL_STAT_LOWFREQF BIT(MICFIL_STAT_LOWFREQF_SHIFT)
#define MICFIL_STAT_CHXF_SHIFT(v) (v)
#define MICFIL_STAT_CHXF_MASK(v) BIT(MICFIL_STAT_CHXF_SHIFT(v))
#define MICFIL_STAT_CHXF(v) BIT(MICFIL_STAT_CHXF_SHIFT(v))
/* MICFIL FIFO Control Register -- REG_MICFIL_FIFO_CTRL 0x10 */ /* MICFIL FIFO Control Register -- REG_MICFIL_FIFO_CTRL 0x10 */
#define MICFIL_FIFO_CTRL_FIFOWMK_SHIFT 0 #define MICFIL_FIFO_CTRL_FIFOWMK GENMASK(2, 0)
#define MICFIL_FIFO_CTRL_FIFOWMK_WIDTH 3
#define MICFIL_FIFO_CTRL_FIFOWMK_MASK ((BIT(MICFIL_FIFO_CTRL_FIFOWMK_WIDTH) - 1) \
<< MICFIL_FIFO_CTRL_FIFOWMK_SHIFT)
#define MICFIL_FIFO_CTRL_FIFOWMK(v) (((v) << MICFIL_FIFO_CTRL_FIFOWMK_SHIFT) \
& MICFIL_FIFO_CTRL_FIFOWMK_MASK)
/* MICFIL FIFO Status Register -- REG_MICFIL_FIFO_STAT 0x14 */ /* MICFIL FIFO Status Register -- REG_MICFIL_FIFO_STAT 0x14 */
#define MICFIL_FIFO_STAT_FIFOX_OVER_SHIFT(v) (v) #define MICFIL_FIFO_STAT_FIFOX_OVER(ch) BIT(ch)
#define MICFIL_FIFO_STAT_FIFOX_OVER_MASK(v) BIT(MICFIL_FIFO_STAT_FIFOX_OVER_SHIFT(v)) #define MICFIL_FIFO_STAT_FIFOX_UNDER(ch) BIT((ch) + 8)
#define MICFIL_FIFO_STAT_FIFOX_UNDER_SHIFT(v) ((v) + 8)
#define MICFIL_FIFO_STAT_FIFOX_UNDER_MASK(v) BIT(MICFIL_FIFO_STAT_FIFOX_UNDER_SHIFT(v))
/* MICFIL HWVAD0 Control 1 Register -- REG_MICFIL_VAD0_CTRL1*/ /* MICFIL HWVAD0 Control 1 Register -- REG_MICFIL_VAD0_CTRL1*/
#define MICFIL_VAD0_CTRL1_CHSEL_SHIFT 24 #define MICFIL_VAD0_CTRL1_CHSEL_SHIFT GENMASK(26, 24)
#define MICFIL_VAD0_CTRL1_CHSEL_WIDTH 3 #define MICFIL_VAD0_CTRL1_CICOSR_SHIFT GENMASK(19, 16)
#define MICFIL_VAD0_CTRL1_CHSEL_MASK ((BIT(MICFIL_VAD0_CTRL1_CHSEL_WIDTH) - 1) \ #define MICFIL_VAD0_CTRL1_INITT_SHIFT GENMASK(12, 8)
<< MICFIL_VAD0_CTRL1_CHSEL_SHIFT) #define MICFIL_VAD0_CTRL1_ST10 BIT(4)
#define MICFIL_VAD0_CTRL1_CHSEL(v) (((v) << MICFIL_VAD0_CTRL1_CHSEL_SHIFT) \ #define MICFIL_VAD0_CTRL1_ERIE BIT(3)
& MICFIL_VAD0_CTRL1_CHSEL_MASK) #define MICFIL_VAD0_CTRL1_IE BIT(2)
#define MICFIL_VAD0_CTRL1_CICOSR_SHIFT 16 #define MICFIL_VAD0_CTRL1_RST BIT(1)
#define MICFIL_VAD0_CTRL1_CICOSR_WIDTH 4 #define MICFIL_VAD0_CTRL1_EN BIT(0)
#define MICFIL_VAD0_CTRL1_CICOSR_MASK ((BIT(MICFIL_VAD0_CTRL1_CICOSR_WIDTH) - 1) \
<< MICFIL_VAD0_CTRL1_CICOSR_SHIFT)
#define MICFIL_VAD0_CTRL1_CICOSR(v) (((v) << MICFIL_VAD0_CTRL1_CICOSR_SHIFT) \
& MICFIL_VAD0_CTRL1_CICOSR_MASK)
#define MICFIL_VAD0_CTRL1_INITT_SHIFT 8
#define MICFIL_VAD0_CTRL1_INITT_WIDTH 5
#define MICFIL_VAD0_CTRL1_INITT_MASK ((BIT(MICFIL_VAD0_CTRL1_INITT_WIDTH) - 1) \
<< MICFIL_VAD0_CTRL1_INITT_SHIFT)
#define MICFIL_VAD0_CTRL1_INITT(v) (((v) << MICFIL_VAD0_CTRL1_INITT_SHIFT) \
& MICFIL_VAD0_CTRL1_INITT_MASK)
#define MICFIL_VAD0_CTRL1_ST10_SHIFT 4
#define MICFIL_VAD0_CTRL1_ST10_MASK BIT(MICFIL_VAD0_CTRL1_ST10_SHIFT)
#define MICFIL_VAD0_CTRL1_ST10 BIT(MICFIL_VAD0_CTRL1_ST10_SHIFT)
#define MICFIL_VAD0_CTRL1_ERIE_SHIFT 3
#define MICFIL_VAD0_CTRL1_ERIE_MASK BIT(MICFIL_VAD0_CTRL1_ERIE_SHIFT)
#define MICFIL_VAD0_CTRL1_ERIE BIT(MICFIL_VAD0_CTRL1_ERIE_SHIFT)
#define MICFIL_VAD0_CTRL1_IE_SHIFT 2
#define MICFIL_VAD0_CTRL1_IE_MASK BIT(MICFIL_VAD0_CTRL1_IE_SHIFT)
#define MICFIL_VAD0_CTRL1_IE BIT(MICFIL_VAD0_CTRL1_IE_SHIFT)
#define MICFIL_VAD0_CTRL1_RST_SHIFT 1
#define MICFIL_VAD0_CTRL1_RST_MASK BIT(MICFIL_VAD0_CTRL1_RST_SHIFT)
#define MICFIL_VAD0_CTRL1_RST BIT(MICFIL_VAD0_CTRL1_RST_SHIFT)
#define MICFIL_VAD0_CTRL1_EN_SHIFT 0
#define MICFIL_VAD0_CTRL1_EN_MASK BIT(MICFIL_VAD0_CTRL1_EN_SHIFT)
#define MICFIL_VAD0_CTRL1_EN BIT(MICFIL_VAD0_CTRL1_EN_SHIFT)
/* MICFIL HWVAD0 Control 2 Register -- REG_MICFIL_VAD0_CTRL2*/ /* MICFIL HWVAD0 Control 2 Register -- REG_MICFIL_VAD0_CTRL2*/
#define MICFIL_VAD0_CTRL2_FRENDIS_SHIFT 31 #define MICFIL_VAD0_CTRL2_FRENDIS BIT(31)
#define MICFIL_VAD0_CTRL2_FRENDIS_MASK BIT(MICFIL_VAD0_CTRL2_FRENDIS_SHIFT) #define MICFIL_VAD0_CTRL2_PREFEN BIT(30)
#define MICFIL_VAD0_CTRL2_FRENDIS BIT(MICFIL_VAD0_CTRL2_FRENDIS_SHIFT) #define MICFIL_VAD0_CTRL2_FOUTDIS BIT(28)
#define MICFIL_VAD0_CTRL2_PREFEN_SHIFT 30 #define MICFIL_VAD0_CTRL2_FRAMET GENMASK(21, 16)
#define MICFIL_VAD0_CTRL2_PREFEN_MASK BIT(MICFIL_VAD0_CTRL2_PREFEN_SHIFT) #define MICFIL_VAD0_CTRL2_INPGAIN GENMASK(11, 8)
#define MICFIL_VAD0_CTRL2_PREFEN BIT(MICFIL_VAD0_CTRL2_PREFEN_SHIFT) #define MICFIL_VAD0_CTRL2_HPF GENMASK(1, 0)
#define MICFIL_VAD0_CTRL2_FOUTDIS_SHIFT 28
#define MICFIL_VAD0_CTRL2_FOUTDIS_MASK BIT(MICFIL_VAD0_CTRL2_FOUTDIS_SHIFT)
#define MICFIL_VAD0_CTRL2_FOUTDIS BIT(MICFIL_VAD0_CTRL2_FOUTDIS_SHIFT)
#define MICFIL_VAD0_CTRL2_FRAMET_SHIFT 16
#define MICFIL_VAD0_CTRL2_FRAMET_WIDTH 6
#define MICFIL_VAD0_CTRL2_FRAMET_MASK ((BIT(MICFIL_VAD0_CTRL2_FRAMET_WIDTH) - 1) \
<< MICFIL_VAD0_CTRL2_FRAMET_SHIFT)
#define MICFIL_VAD0_CTRL2_FRAMET(v) (((v) << MICFIL_VAD0_CTRL2_FRAMET_SHIFT) \
& MICFIL_VAD0_CTRL2_FRAMET_MASK)
#define MICFIL_VAD0_CTRL2_INPGAIN_SHIFT 8
#define MICFIL_VAD0_CTRL2_INPGAIN_WIDTH 4
#define MICFIL_VAD0_CTRL2_INPGAIN_MASK ((BIT(MICFIL_VAD0_CTRL2_INPGAIN_WIDTH) - 1) \
<< MICFIL_VAD0_CTRL2_INPGAIN_SHIFT)
#define MICFIL_VAD0_CTRL2_INPGAIN(v) (((v) << MICFIL_VAD0_CTRL2_INPGAIN_SHIFT) \
& MICFIL_VAD0_CTRL2_INPGAIN_MASK)
#define MICFIL_VAD0_CTRL2_HPF_SHIFT 0
#define MICFIL_VAD0_CTRL2_HPF_WIDTH 2
#define MICFIL_VAD0_CTRL2_HPF_MASK ((BIT(MICFIL_VAD0_CTRL2_HPF_WIDTH) - 1) \
<< MICFIL_VAD0_CTRL2_HPF_SHIFT)
#define MICFIL_VAD0_CTRL2_HPF(v) (((v) << MICFIL_VAD0_CTRL2_HPF_SHIFT) \
& MICFIL_VAD0_CTRL2_HPF_MASK)
/* MICFIL HWVAD0 Signal CONFIG Register -- REG_MICFIL_VAD0_SCONFIG */ /* MICFIL HWVAD0 Signal CONFIG Register -- REG_MICFIL_VAD0_SCONFIG */
#define MICFIL_VAD0_SCONFIG_SFILEN_SHIFT 31 #define MICFIL_VAD0_SCONFIG_SFILEN BIT(31)
#define MICFIL_VAD0_SCONFIG_SFILEN_MASK BIT(MICFIL_VAD0_SCONFIG_SFILEN_SHIFT) #define MICFIL_VAD0_SCONFIG_SMAXEN BIT(30)
#define MICFIL_VAD0_SCONFIG_SFILEN BIT(MICFIL_VAD0_SCONFIG_SFILEN_SHIFT) #define MICFIL_VAD0_SCONFIG_SGAIN GENMASK(3, 0)
#define MICFIL_VAD0_SCONFIG_SMAXEN_SHIFT 30
#define MICFIL_VAD0_SCONFIG_SMAXEN_MASK BIT(MICFIL_VAD0_SCONFIG_SMAXEN_SHIFT)
#define MICFIL_VAD0_SCONFIG_SMAXEN BIT(MICFIL_VAD0_SCONFIG_SMAXEN_SHIFT)
#define MICFIL_VAD0_SCONFIG_SGAIN_SHIFT 0
#define MICFIL_VAD0_SCONFIG_SGAIN_WIDTH 4
#define MICFIL_VAD0_SCONFIG_SGAIN_MASK ((BIT(MICFIL_VAD0_SCONFIG_SGAIN_WIDTH) - 1) \
<< MICFIL_VAD0_SCONFIG_SGAIN_SHIFT)
#define MICFIL_VAD0_SCONFIG_SGAIN(v) (((v) << MICFIL_VAD0_SCONFIG_SGAIN_SHIFT) \
& MICFIL_VAD0_SCONFIG_SGAIN_MASK)
/* MICFIL HWVAD0 Noise CONFIG Register -- REG_MICFIL_VAD0_NCONFIG */ /* MICFIL HWVAD0 Noise CONFIG Register -- REG_MICFIL_VAD0_NCONFIG */
#define MICFIL_VAD0_NCONFIG_NFILAUT_SHIFT 31 #define MICFIL_VAD0_NCONFIG_NFILAUT BIT(31)
#define MICFIL_VAD0_NCONFIG_NFILAUT_MASK BIT(MICFIL_VAD0_NCONFIG_NFILAUT_SHIFT) #define MICFIL_VAD0_NCONFIG_NMINEN BIT(30)
#define MICFIL_VAD0_NCONFIG_NFILAUT BIT(MICFIL_VAD0_NCONFIG_NFILAUT_SHIFT) #define MICFIL_VAD0_NCONFIG_NDECEN BIT(29)
#define MICFIL_VAD0_NCONFIG_NMINEN_SHIFT 30 #define MICFIL_VAD0_NCONFIG_NOREN BIT(28)
#define MICFIL_VAD0_NCONFIG_NMINEN_MASK BIT(MICFIL_VAD0_NCONFIG_NMINEN_SHIFT) #define MICFIL_VAD0_NCONFIG_NFILADJ GENMASK(12, 8)
#define MICFIL_VAD0_NCONFIG_NMINEN BIT(MICFIL_VAD0_NCONFIG_NMINEN_SHIFT) #define MICFIL_VAD0_NCONFIG_NGAIN GENMASK(3, 0)
#define MICFIL_VAD0_NCONFIG_NDECEN_SHIFT 29
#define MICFIL_VAD0_NCONFIG_NDECEN_MASK BIT(MICFIL_VAD0_NCONFIG_NDECEN_SHIFT)
#define MICFIL_VAD0_NCONFIG_NDECEN BIT(MICFIL_VAD0_NCONFIG_NDECEN_SHIFT)
#define MICFIL_VAD0_NCONFIG_NOREN_SHIFT 28
#define MICFIL_VAD0_NCONFIG_NOREN BIT(MICFIL_VAD0_NCONFIG_NOREN_SHIFT)
#define MICFIL_VAD0_NCONFIG_NFILADJ_SHIFT 8
#define MICFIL_VAD0_NCONFIG_NFILADJ_WIDTH 5
#define MICFIL_VAD0_NCONFIG_NFILADJ_MASK ((BIT(MICFIL_VAD0_NCONFIG_NFILADJ_WIDTH) - 1) \
<< MICFIL_VAD0_NCONFIG_NFILADJ_SHIFT)
#define MICFIL_VAD0_NCONFIG_NFILADJ(v) (((v) << MICFIL_VAD0_NCONFIG_NFILADJ_SHIFT) \
& MICFIL_VAD0_NCONFIG_NFILADJ_MASK)
#define MICFIL_VAD0_NCONFIG_NGAIN_SHIFT 0
#define MICFIL_VAD0_NCONFIG_NGAIN_WIDTH 4
#define MICFIL_VAD0_NCONFIG_NGAIN_MASK ((BIT(MICFIL_VAD0_NCONFIG_NGAIN_WIDTH) - 1) \
<< MICFIL_VAD0_NCONFIG_NGAIN_SHIFT)
#define MICFIL_VAD0_NCONFIG_NGAIN(v) (((v) << MICFIL_VAD0_NCONFIG_NGAIN_SHIFT) \
& MICFIL_VAD0_NCONFIG_NGAIN_MASK)
/* MICFIL HWVAD0 Zero-Crossing Detector - REG_MICFIL_VAD0_ZCD */ /* MICFIL HWVAD0 Zero-Crossing Detector - REG_MICFIL_VAD0_ZCD */
#define MICFIL_VAD0_ZCD_ZCDTH_SHIFT 16 #define MICFIL_VAD0_ZCD_ZCDTH GENMASK(25, 16)
#define MICFIL_VAD0_ZCD_ZCDTH_WIDTH 10 #define MICFIL_VAD0_ZCD_ZCDADJ_SHIFT GENMASK(11, 8)
#define MICFIL_VAD0_ZCD_ZCDTH_MASK ((BIT(MICFIL_VAD0_ZCD_ZCDTH_WIDTH) - 1) \ #define MICFIL_VAD0_ZCD_ZCDAND BIT(4)
<< MICFIL_VAD0_ZCD_ZCDTH_SHIFT) #define MICFIL_VAD0_ZCD_ZCDAUT BIT(2)
#define MICFIL_VAD0_ZCD_ZCDTH(v) (((v) << MICFIL_VAD0_ZCD_ZCDTH_SHIFT)\ #define MICFIL_VAD0_ZCD_ZCDEN BIT(0)
& MICFIL_VAD0_ZCD_ZCDTH_MASK)
#define MICFIL_VAD0_ZCD_ZCDADJ_SHIFT 8
#define MICFIL_VAD0_ZCD_ZCDADJ_WIDTH 4
#define MICFIL_VAD0_ZCD_ZCDADJ_MASK ((BIT(MICFIL_VAD0_ZCD_ZCDADJ_WIDTH) - 1)\
<< MICFIL_VAD0_ZCD_ZCDADJ_SHIFT)
#define MICFIL_VAD0_ZCD_ZCDADJ(v) (((v) << MICFIL_VAD0_ZCD_ZCDADJ_SHIFT)\
& MICFIL_VAD0_ZCD_ZCDADJ_MASK)
#define MICFIL_VAD0_ZCD_ZCDAND_SHIFT 4
#define MICFIL_VAD0_ZCD_ZCDAND_MASK BIT(MICFIL_VAD0_ZCD_ZCDAND_SHIFT)
#define MICFIL_VAD0_ZCD_ZCDAND BIT(MICFIL_VAD0_ZCD_ZCDAND_SHIFT)
#define MICFIL_VAD0_ZCD_ZCDAUT_SHIFT 2
#define MICFIL_VAD0_ZCD_ZCDAUT_MASK BIT(MICFIL_VAD0_ZCD_ZCDAUT_SHIFT)
#define MICFIL_VAD0_ZCD_ZCDAUT BIT(MICFIL_VAD0_ZCD_ZCDAUT_SHIFT)
#define MICFIL_VAD0_ZCD_ZCDEN_SHIFT 0
#define MICFIL_VAD0_ZCD_ZCDEN_MASK BIT(MICFIL_VAD0_ZCD_ZCDEN_SHIFT)
#define MICFIL_VAD0_ZCD_ZCDEN BIT(MICFIL_VAD0_ZCD_ZCDEN_SHIFT)
/* MICFIL HWVAD0 Status Register - REG_MICFIL_VAD0_STAT */ /* MICFIL HWVAD0 Status Register - REG_MICFIL_VAD0_STAT */
#define MICFIL_VAD0_STAT_INITF_SHIFT 31 #define MICFIL_VAD0_STAT_INITF BIT(31)
#define MICFIL_VAD0_STAT_INITF_MASK BIT(MICFIL_VAD0_STAT_INITF_SHIFT) #define MICFIL_VAD0_STAT_INSATF BIT(16)
#define MICFIL_VAD0_STAT_INITF BIT(MICFIL_VAD0_STAT_INITF_SHIFT) #define MICFIL_VAD0_STAT_EF BIT(15)
#define MICFIL_VAD0_STAT_INSATF_SHIFT 16 #define MICFIL_VAD0_STAT_IF BIT(0)
#define MICFIL_VAD0_STAT_INSATF_MASK BIT(MICFIL_VAD0_STAT_INSATF_SHIFT)
#define MICFIL_VAD0_STAT_INSATF BIT(MICFIL_VAD0_STAT_INSATF_SHIFT)
#define MICFIL_VAD0_STAT_EF_SHIFT 15
#define MICFIL_VAD0_STAT_EF_MASK BIT(MICFIL_VAD0_STAT_EF_SHIFT)
#define MICFIL_VAD0_STAT_EF BIT(MICFIL_VAD0_STAT_EF_SHIFT)
#define MICFIL_VAD0_STAT_IF_SHIFT 0
#define MICFIL_VAD0_STAT_IF_MASK BIT(MICFIL_VAD0_STAT_IF_SHIFT)
#define MICFIL_VAD0_STAT_IF BIT(MICFIL_VAD0_STAT_IF_SHIFT)
/* MICFIL Output Control Register */ /* MICFIL Output Control Register */
#define MICFIL_OUTGAIN_CHX_SHIFT(v) (4 * (v)) #define MICFIL_OUTGAIN_CHX_SHIFT(v) (4 * (v))
/* Constants */ /* Constants */
#define MICFIL_DMA_IRQ_DISABLED(v) ((v) & MICFIL_CTRL1_DISEL_MASK)
#define MICFIL_DMA_ENABLED(v) ((0x1 << MICFIL_CTRL1_DISEL_SHIFT) \
== ((v) & MICFIL_CTRL1_DISEL_MASK))
#define MICFIL_IRQ_ENABLED(v) ((0x2 << MICFIL_CTRL1_DISEL_SHIFT) \
== ((v) & MICFIL_CTRL1_DISEL_MASK))
#define MICFIL_OUTPUT_CHANNELS 8 #define MICFIL_OUTPUT_CHANNELS 8
#define MICFIL_FIFO_NUM 8 #define MICFIL_FIFO_NUM 8
...@@ -278,6 +132,5 @@ ...@@ -278,6 +132,5 @@
#define MICFIL_SLEEP_MIN 90000 /* in us */ #define MICFIL_SLEEP_MIN 90000 /* in us */
#define MICFIL_SLEEP_MAX 100000 /* in us */ #define MICFIL_SLEEP_MAX 100000 /* in us */
#define MICFIL_DMA_MAXBURST_RX 6 #define MICFIL_DMA_MAXBURST_RX 6
#define MICFIL_CTRL2_OSR_DEFAULT (0 << MICFIL_CTRL2_CICOSR_SHIFT)
#endif /* _FSL_MICFIL_H */ #endif /* _FSL_MICFIL_H */
sound/soc/fsl/imx-pcm.h
View file @ 89d2bce7
...@@ -9,7 +9,7 @@ ...@@ -9,7 +9,7 @@
#ifndef _IMX_PCM_H #ifndef _IMX_PCM_H
#define _IMX_PCM_H #define _IMX_PCM_H
#include <linux/platform_data/dma-imx.h> #include <linux/dma/imx-dma.h>
/* /*
* Do not change this as the FIQ handler depends on this size * Do not change this as the FIQ handler depends on this size
......
sound/soc/fsl/imx-ssi.h
View file @ 89d2bce7
...@@ -182,7 +182,7 @@ ...@@ -182,7 +182,7 @@
#define DRV_NAME "imx-ssi" #define DRV_NAME "imx-ssi"
#include <linux/dmaengine.h> #include <linux/dmaengine.h>
#include <linux/platform_data/dma-imx.h> #include <linux/dma/imx-dma.h>
#include <sound/dmaengine_pcm.h> #include <sound/dmaengine_pcm.h>
#include "imx-pcm.h" #include "imx-pcm.h"
......
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