Commit 89fb2d77 authored by Andrew Lunn's avatar Andrew Lunn

Merge branch 'v3.5-rc7-fixes' into v3.5-rc7-dt-v3

Merge in branch already pulled. Fulfils dependancies needed by
this patchset.
parents 42971035 77843504
NAND support for Marvell Orion SoC platforms
Required properties:
- compatible : "mrvl,orion-nand".
- compatible : "marvell,orion-nand".
- reg : Base physical address of the NAND and length of memory mapped
region
......@@ -24,7 +24,7 @@ nand@f4000000 {
ale = <1>;
bank-width = <1>;
chip-delay = <25>;
compatible = "mrvl,orion-nand";
compatible = "marvell,orion-nand";
reg = <0xf4000000 0x400>;
partition@0 {
......
......@@ -4,7 +4,7 @@
/ {
model = "D-Link DNS-320 NAS (Rev A1)";
compatible = "dlink,dns-320-a1", "dlink,dns-320", "dlink,dns-kirkwood", "mrvl,kirkwood-88f6281", "mrvl,kirkwood";
compatible = "dlink,dns-320-a1", "dlink,dns-320", "dlink,dns-kirkwood", "marvell,kirkwood-88f6281", "marvell,kirkwood";
memory {
device_type = "memory";
......
......@@ -4,7 +4,7 @@
/ {
model = "D-Link DNS-325 NAS (Rev A1)";
compatible = "dlink,dns-325-a1", "dlink,dns-325", "dlink,dns-kirkwood", "mrvl,kirkwood-88f6281", "mrvl,kirkwood";
compatible = "dlink,dns-325-a1", "dlink,dns-325", "dlink,dns-kirkwood", "marvell,kirkwood-88f6281", "marvell,kirkwood";
memory {
device_type = "memory";
......
......@@ -4,7 +4,7 @@
/ {
model = "Globalscale Technologies Dreamplug";
compatible = "globalscale,dreamplug-003-ds2001", "globalscale,dreamplug", "mrvl,kirkwood-88f6281", "mrvl,kirkwood";
compatible = "globalscale,dreamplug-003-ds2001", "globalscale,dreamplug", "marvell,kirkwood-88f6281", "marvell,kirkwood";
memory {
device_type = "memory";
......
......@@ -4,7 +4,7 @@
/ {
model = "RaidSonic ICY BOX IB-NAS62x0 (Rev B)";
compatible = "raidsonic,ib-nas6210-b", "raidsonic,ib-nas6220-b", "raidsonic,ib-nas6210", "raidsonic,ib-nas6220", "raidsonic,ib-nas62x0", "mrvl,kirkwood-88f6281", "mrvl,kirkwood";
compatible = "raidsonic,ib-nas6210-b", "raidsonic,ib-nas6220-b", "raidsonic,ib-nas6210", "raidsonic,ib-nas6220", "raidsonic,ib-nas62x0", "marvell,kirkwood-88f6281", "marvell,kirkwood";
memory {
device_type = "memory";
......
......@@ -4,7 +4,7 @@
/ {
model = "Iomega Iconnect";
compatible = "iom,iconnect-1.1", "iom,iconnect", "mrvl,kirkwood-88f6281", "mrvl,kirkwood";
compatible = "iom,iconnect-1.1", "iom,iconnect", "marvell,kirkwood-88f6281", "marvell,kirkwood";
memory {
device_type = "memory";
......
/include/ "skeleton.dtsi"
/ {
compatible = "mrvl,kirkwood";
compatible = "marvell,kirkwood";
ocp@f1000000 {
compatible = "simple-bus";
......@@ -28,7 +28,7 @@ serial@12100 {
};
rtc@10300 {
compatible = "mrvl,kirkwood-rtc", "mrvl,orion-rtc";
compatible = "marvell,kirkwood-rtc", "marvell,orion-rtc";
reg = <0x10300 0x20>;
interrupts = <53>;
};
......@@ -39,7 +39,7 @@ nand@3000000 {
cle = <0>;
ale = <1>;
bank-width = <1>;
compatible = "mrvl,orion-nand";
compatible = "marvell,orion-nand";
reg = <0x3000000 0x400>;
chip-delay = <25>;
/* set partition map and/or chip-delay in board dts */
......
......@@ -101,8 +101,8 @@ void __init dove_ehci1_init(void)
****************************************************************************/
void __init dove_ge00_init(struct mv643xx_eth_platform_data *eth_data)
{
orion_ge00_init(eth_data,
DOVE_GE00_PHYS_BASE, IRQ_DOVE_GE00_SUM, 0);
orion_ge00_init(eth_data, DOVE_GE00_PHYS_BASE,
IRQ_DOVE_GE00_SUM, IRQ_DOVE_GE00_ERR);
}
/*****************************************************************************
......
......@@ -67,6 +67,14 @@ void __init kirkwood_map_io(void)
* CLK tree
****************************************************************************/
static void enable_sata0(void)
{
/* Enable PLL and IVREF */
writel(readl(SATA0_PHY_MODE_2) | 0xf, SATA0_PHY_MODE_2);
/* Enable PHY */
writel(readl(SATA0_IF_CTRL) & ~0x200, SATA0_IF_CTRL);
}
static void disable_sata0(void)
{
/* Disable PLL and IVREF */
......@@ -75,6 +83,14 @@ static void disable_sata0(void)
writel(readl(SATA0_IF_CTRL) | 0x200, SATA0_IF_CTRL);
}
static void enable_sata1(void)
{
/* Enable PLL and IVREF */
writel(readl(SATA1_PHY_MODE_2) | 0xf, SATA1_PHY_MODE_2);
/* Enable PHY */
writel(readl(SATA1_IF_CTRL) & ~0x200, SATA1_IF_CTRL);
}
static void disable_sata1(void)
{
/* Disable PLL and IVREF */
......@@ -107,23 +123,38 @@ static void disable_pcie1(void)
}
}
/* An extended version of the gated clk. This calls fn() before
* disabling the clock. We use this to turn off PHYs etc. */
/* An extended version of the gated clk. This calls fn_en()/fn_dis
* before enabling/disabling the clock. We use this to turn on/off
* PHYs etc. */
struct clk_gate_fn {
struct clk_gate gate;
void (*fn)(void);
void (*fn_en)(void);
void (*fn_dis)(void);
};
#define to_clk_gate_fn(_gate) container_of(_gate, struct clk_gate_fn, gate)
#define to_clk_gate(_hw) container_of(_hw, struct clk_gate, hw)
static int clk_gate_fn_enable(struct clk_hw *hw)
{
struct clk_gate *gate = to_clk_gate(hw);
struct clk_gate_fn *gate_fn = to_clk_gate_fn(gate);
int ret;
ret = clk_gate_ops.enable(hw);
if (!ret && gate_fn->fn_en)
gate_fn->fn_en();
return ret;
}
static void clk_gate_fn_disable(struct clk_hw *hw)
{
struct clk_gate *gate = to_clk_gate(hw);
struct clk_gate_fn *gate_fn = to_clk_gate_fn(gate);
if (gate_fn->fn)
gate_fn->fn();
if (gate_fn->fn_dis)
gate_fn->fn_dis();
clk_gate_ops.disable(hw);
}
......@@ -135,7 +166,7 @@ static struct clk __init *clk_register_gate_fn(struct device *dev,
const char *parent_name, unsigned long flags,
void __iomem *reg, u8 bit_idx,
u8 clk_gate_flags, spinlock_t *lock,
void (*fn)(void))
void (*fn_en)(void), void (*fn_dis)(void))
{
struct clk_gate_fn *gate_fn;
struct clk *clk;
......@@ -159,11 +190,14 @@ static struct clk __init *clk_register_gate_fn(struct device *dev,
gate_fn->gate.flags = clk_gate_flags;
gate_fn->gate.lock = lock;
gate_fn->gate.hw.init = &init;
gate_fn->fn = fn;
gate_fn->fn_en = fn_en;
gate_fn->fn_dis = fn_dis;
/* ops is the gate ops, but with our disable function */
if (clk_gate_fn_ops.disable != clk_gate_fn_disable) {
/* ops is the gate ops, but with our enable/disable functions */
if (clk_gate_fn_ops.enable != clk_gate_fn_enable ||
clk_gate_fn_ops.disable != clk_gate_fn_disable) {
clk_gate_fn_ops = clk_gate_ops;
clk_gate_fn_ops.enable = clk_gate_fn_enable;
clk_gate_fn_ops.disable = clk_gate_fn_disable;
}
......@@ -187,11 +221,12 @@ static struct clk __init *kirkwood_register_gate(const char *name, u8 bit_idx)
static struct clk __init *kirkwood_register_gate_fn(const char *name,
u8 bit_idx,
void (*fn)(void))
void (*fn_en)(void),
void (*fn_dis)(void))
{
return clk_register_gate_fn(NULL, name, "tclk", 0,
(void __iomem *)CLOCK_GATING_CTRL,
bit_idx, 0, &gating_lock, fn);
bit_idx, 0, &gating_lock, fn_en, fn_dis);
}
static struct clk *ge0, *ge1;
......@@ -208,18 +243,18 @@ void __init kirkwood_clk_init(void)
ge0 = kirkwood_register_gate("ge0", CGC_BIT_GE0);
ge1 = kirkwood_register_gate("ge1", CGC_BIT_GE1);
sata0 = kirkwood_register_gate_fn("sata0", CGC_BIT_SATA0,
disable_sata0);
enable_sata0, disable_sata0);
sata1 = kirkwood_register_gate_fn("sata1", CGC_BIT_SATA1,
disable_sata1);
enable_sata1, disable_sata1);
usb0 = kirkwood_register_gate("usb0", CGC_BIT_USB0);
sdio = kirkwood_register_gate("sdio", CGC_BIT_SDIO);
crypto = kirkwood_register_gate("crypto", CGC_BIT_CRYPTO);
xor0 = kirkwood_register_gate("xor0", CGC_BIT_XOR0);
xor1 = kirkwood_register_gate("xor1", CGC_BIT_XOR1);
pex0 = kirkwood_register_gate_fn("pex0", CGC_BIT_PEX0,
disable_pcie0);
NULL, disable_pcie0);
pex1 = kirkwood_register_gate_fn("pex1", CGC_BIT_PEX1,
disable_pcie1);
NULL, disable_pcie1);
audio = kirkwood_register_gate("audio", CGC_BIT_AUDIO);
kirkwood_register_gate("tdm", CGC_BIT_TDM);
kirkwood_register_gate("tsu", CGC_BIT_TSU);
......@@ -241,6 +276,11 @@ void __init kirkwood_clk_init(void)
orion_clkdev_add("0", "pcie", pex0);
orion_clkdev_add("1", "pcie", pex1);
orion_clkdev_add(NULL, "kirkwood-i2s", audio);
/* Marvell says runit is used by SPI, UART, NAND, TWSI, ...,
* so should never be gated.
*/
clk_prepare_enable(runit);
}
/*****************************************************************************
......
......@@ -1098,6 +1098,10 @@ static int mv_probe(struct platform_device *pdev)
crypto_unregister_alg(&mv_aes_alg_ecb);
err_irq:
free_irq(irq, cp);
if (!IS_ERR(cp->clk)) {
clk_disable_unprepare(cp->clk);
clk_put(cp->clk);
}
err_thread:
kthread_stop(cp->queue_th);
err_unmap_sram:
......
......@@ -839,6 +839,10 @@ static int __init mvsd_probe(struct platform_device *pdev)
if (r)
release_resource(r);
if (mmc)
if (!IS_ERR_OR_NULL(host->clk)) {
clk_disable_unprepare(host->clk);
clk_put(host->clk);
}
mmc_free_host(mmc);
return ret;
......
......@@ -183,6 +183,10 @@ static int __init orion_nand_probe(struct platform_device *pdev)
return 0;
no_dev:
if (!IS_ERR(clk)) {
clk_disable_unprepare(clk);
clk_put(clk);
}
platform_set_drvdata(pdev, NULL);
iounmap(io_base);
no_res:
......@@ -214,7 +218,7 @@ static int __devexit orion_nand_remove(struct platform_device *pdev)
#ifdef CONFIG_OF
static struct of_device_id orion_nand_of_match_table[] = {
{ .compatible = "mrvl,orion-nand", },
{ .compatible = "marvell,orion-nand", },
{},
};
#endif
......
......@@ -2983,6 +2983,12 @@ static int mv643xx_eth_probe(struct platform_device *pdev)
return 0;
out:
#if defined(CONFIG_HAVE_CLK)
if (!IS_ERR(mp->clk)) {
clk_disable_unprepare(mp->clk);
clk_put(mp->clk);
}
#endif
free_netdev(dev);
return err;
......
......@@ -297,7 +297,7 @@ static int __exit mv_rtc_remove(struct platform_device *pdev)
#ifdef CONFIG_OF
static struct of_device_id rtc_mv_of_match_table[] = {
{ .compatible = "mrvl,orion-rtc", },
{ .compatible = "marvell,orion-rtc", },
{}
};
#endif
......
......@@ -298,6 +298,10 @@ static int __devinit ehci_orion_drv_probe(struct platform_device *pdev)
err4:
usb_put_hcd(hcd);
err3:
if (!IS_ERR(clk)) {
clk_disable_unprepare(clk);
clk_put(clk);
}
iounmap(regs);
err2:
release_mem_region(res->start, resource_size(res));
......
......@@ -458,7 +458,13 @@ static __devinit int kirkwood_i2s_dev_probe(struct platform_device *pdev)
}
clk_prepare_enable(priv->clk);
return snd_soc_register_dai(&pdev->dev, &kirkwood_i2s_dai);
err = snd_soc_register_dai(&pdev->dev, &kirkwood_i2s_dai);
if (!err)
return 0;
dev_err(&pdev->dev, "snd_soc_register_dai failed\n");
clk_disable_unprepare(priv->clk);
clk_put(priv->clk);
err_ioremap:
iounmap(priv->io);
......
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