Commit 8a1e75c5 authored by Arnd Bergmann's avatar Arnd Bergmann

Merge tag 'v5.19-rockchip-dts64-2' of...

Merge tag 'v5.19-rockchip-dts64-2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into arm/late

Clock properties for cru nodes to match the yaml-converted bindings
and renaming of Quartz-A bluetooth pin nodename to not conflict with
Yaml constraints.

* tag 'v5.19-rockchip-dts64-2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
  arm64: dts: rockchip: rename Quartz64-A bluetooth gpios
  arm64: dts: rockchip: add clocks property to cru node rk3368
  arm64: dts: rockchip: add clocks property to cru node rk3308
  arm64: dts: rockchip: add clocks to rk356x cru

Link: https://lore.kernel.org/r/7695907.Sb9uPGUboI@philSigned-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents 44051777 cd414d5a
......@@ -745,10 +745,11 @@ sfc: spi@ff4c0000 {
cru: clock-controller@ff500000 {
compatible = "rockchip,rk3308-cru";
reg = <0x0 0xff500000 0x0 0x1000>;
clocks = <&xin24m>;
clock-names = "xin24m";
rockchip,grf = <&grf>;
#clock-cells = <1>;
#reset-cells = <1>;
rockchip,grf = <&grf>;
assigned-clocks = <&cru SCLK_RTC32K>;
assigned-clock-rates = <32768>;
};
......
......@@ -747,6 +747,8 @@ reboot-mode {
cru: clock-controller@ff760000 {
compatible = "rockchip,rk3368-cru";
reg = <0x0 0xff760000 0x0 0x1000>;
clocks = <&xin24m>;
clock-names = "xin24m";
rockchip,grf = <&grf>;
#clock-cells = <1>;
#reset-cells = <1>;
......
......@@ -652,8 +652,8 @@ bluetooth {
compatible = "brcm,bcm43438-bt";
clocks = <&rk817 1>;
clock-names = "lpo";
device-wake-gpios = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>;
host-wake-gpios = <&gpio2 RK_PC0 GPIO_ACTIVE_HIGH>;
device-wakeup-gpios = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>;
host-wakeup-gpios = <&gpio2 RK_PC0 GPIO_ACTIVE_HIGH>;
shutdown-gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_enable_h>;
......
......@@ -397,6 +397,8 @@ pmucru: clock-controller@fdd00000 {
cru: clock-controller@fdd20000 {
compatible = "rockchip,rk3568-cru";
reg = <0x0 0xfdd20000 0x0 0x1000>;
clocks = <&xin24m>;
clock-names = "xin24m";
#clock-cells = <1>;
#reset-cells = <1>;
assigned-clocks = <&cru PLL_GPLL>, <&pmucru PLL_PPLL>;
......
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