Commit 8b01302f authored by Sylwester Nawrocki's avatar Sylwester Nawrocki Committed by Khalid Elmously

ASoC: samsung: i2s: Ensure the RCLK rate is properly determined

BugLink: https://bugs.launchpad.net/bugs/1775771

[ Upstream commit 647d04f8 ]

If the RCLK mux clock configuration is specified in DT and no set_sysclk()
callback is used in the sound card driver the sclk_srcrate field will remain
set to 0, leading to an incorrect PSR divider setting.
To fix this the frequency value is retrieved from the CLK_I2S_RCLK_SRC clock,
so the actual RCLK mux selection is taken into account.
Signed-off-by: default avatarSylwester Nawrocki <s.nawrocki@samsung.com>
Acked-by: default avatarKrzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: default avatarMark Brown <broonie@kernel.org>
Signed-off-by: default avatarSasha Levin <alexander.levin@microsoft.com>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Signed-off-by: default avatarJuerg Haefliger <juergh@canonical.com>
Signed-off-by: default avatarKhalid Elmously <khalid.elmously@canonical.com>
parent dd69f5c4
...@@ -640,8 +640,12 @@ static int i2s_set_fmt(struct snd_soc_dai *dai, ...@@ -640,8 +640,12 @@ static int i2s_set_fmt(struct snd_soc_dai *dai,
tmp |= mod_slave; tmp |= mod_slave;
break; break;
case SND_SOC_DAIFMT_CBS_CFS: case SND_SOC_DAIFMT_CBS_CFS:
/* Set default source clock in Master mode */ /*
if (i2s->rclk_srcrate == 0) * Set default source clock in Master mode, only when the
* CLK_I2S_RCLK_SRC clock is not exposed so we ensure any
* clock configuration assigned in DT is not overwritten.
*/
if (i2s->rclk_srcrate == 0 && i2s->clk_data.clks == NULL)
i2s_set_sysclk(dai, SAMSUNG_I2S_RCLKSRC_0, i2s_set_sysclk(dai, SAMSUNG_I2S_RCLKSRC_0,
0, SND_SOC_CLOCK_IN); 0, SND_SOC_CLOCK_IN);
break; break;
...@@ -856,6 +860,11 @@ static int config_setup(struct i2s_dai *i2s) ...@@ -856,6 +860,11 @@ static int config_setup(struct i2s_dai *i2s)
return 0; return 0;
if (!(i2s->quirks & QUIRK_NO_MUXPSR)) { if (!(i2s->quirks & QUIRK_NO_MUXPSR)) {
struct clk *rclksrc = i2s->clk_table[CLK_I2S_RCLK_SRC];
if (i2s->rclk_srcrate == 0 && rclksrc && !IS_ERR(rclksrc))
i2s->rclk_srcrate = clk_get_rate(rclksrc);
psr = i2s->rclk_srcrate / i2s->frmclk / rfs; psr = i2s->rclk_srcrate / i2s->frmclk / rfs;
writel(((psr - 1) << 8) | PSR_PSREN, i2s->addr + I2SPSR); writel(((psr - 1) << 8) | PSR_PSREN, i2s->addr + I2SPSR);
dev_dbg(&i2s->pdev->dev, dev_dbg(&i2s->pdev->dev,
......
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