Commit 8d7f1fbf authored by Peter Senna Tschudin's avatar Peter Senna Tschudin Committed by David S. Miller

ATHEROS-ALX: Use dma_set_mask_and_coherent and fix a bug

1. For the 64 bits dma mask use dma_set_mask_and_coherent instead of
   dma_set_mask and dma_set_coherent_mask.

2. For the 32 bits dma mask dma_set_coherent_mask is only called if
   dma_set_mask fails, which is unusual. Assuming this as a bug, fixes
   it by replacing calls to dma_set_mask and dma_set_coherent_mask by a
   call to dma_set_mask_and_coherent.
Signed-off-by: default avatarPeter Senna Tschudin <peter.senna@gmail.com>
Tested-by: default avatarJonas Hahnfeld <hahnjo@hahnjo.de>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent ee7d07e7
...@@ -1248,19 +1248,13 @@ static int alx_probe(struct pci_dev *pdev, const struct pci_device_id *ent) ...@@ -1248,19 +1248,13 @@ static int alx_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
* shared register for the high 32 bits, so only a single, aligned, * shared register for the high 32 bits, so only a single, aligned,
* 4 GB physical address range can be used for descriptors. * 4 GB physical address range can be used for descriptors.
*/ */
if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) && if (!dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64))) {
!dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {
dev_dbg(&pdev->dev, "DMA to 64-BIT addresses\n"); dev_dbg(&pdev->dev, "DMA to 64-BIT addresses\n");
} else { } else {
err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32)); err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
if (err) { if (err) {
err = dma_set_coherent_mask(&pdev->dev, dev_err(&pdev->dev, "No usable DMA config, aborting\n");
DMA_BIT_MASK(32)); goto out_pci_disable;
if (err) {
dev_err(&pdev->dev,
"No usable DMA config, aborting\n");
goto out_pci_disable;
}
} }
} }
......
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