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Commit 8ed9de79 authored by Rohit Agarwal's avatar Rohit Agarwal Committed by Bjorn Andersson
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arm64: dts: qcom: sm8450: Update the RPMHPD bindings entry 

Update the RPMHPD bindings entry as per the new generic bindings defined
in rpmhpd.h for SM8450 SoC.
Signed-off-by: default avatarRohit Agarwal <quic_rohiagar@quicinc.com>
Link: https://lore.kernel.org/r/1689840545-5094-4-git-send-email-quic_rohiagar@quicinc.comSigned-off-by: default avatarBjorn Andersson <andersson@kernel.org>
parent fc4cbfbb
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Showing with 19 additions and 18 deletions
arch/arm64/boot/dts/qcom/sm8450.dtsi
View file @ 8ed9de79
......@@ -13,6 +13,7 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/mailbox/qcom-ipcc.h>
#include <dt-bindings/phy/phy-qcom-qmp.h>
#include <dt-bindings/power/qcom,rpmhpd.h>
#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/interconnect/qcom,icc.h>
#include <dt-bindings/interconnect/qcom,sm8450.h>
......@@ -1150,7 +1151,7 @@ spi0: spi@980000 {
interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>;
power-domains = <&rpmhpd SM8450_CX>;
power-domains = <&rpmhpd RPMHPD_CX>;
operating-points-v2 = <&qup_opp_table_100mhz>;
interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
<&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
......@@ -1313,7 +1314,7 @@ spi4: spi@990000 {
interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>;
power-domains = <&rpmhpd SM8450_CX>;
power-domains = <&rpmhpd RPMHPD_CX>;
operating-points-v2 = <&qup_opp_table_100mhz>;
interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
<&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
......@@ -2098,8 +2099,8 @@ remoteproc_slpi: remoteproc@2400000 {
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "xo";
power-domains = <&rpmhpd SM8450_LCX>,
<&rpmhpd SM8450_LMX>;
power-domains = <&rpmhpd RPMHPD_LCX>,
<&rpmhpd RPMHPD_LMX>;
power-domain-names = "lcx", "lmx";
memory-region = <&slpi_mem>;
......@@ -2373,8 +2374,8 @@ remoteproc_adsp: remoteproc@30000000 {
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "xo";
power-domains = <&rpmhpd SM8450_LCX>,
<&rpmhpd SM8450_LMX>;
power-domains = <&rpmhpd RPMHPD_LCX>,
<&rpmhpd RPMHPD_LMX>;
power-domain-names = "lcx", "lmx";
memory-region = <&adsp_mem>;
......@@ -2478,8 +2479,8 @@ remoteproc_cdsp: remoteproc@32300000 {
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "xo";
power-domains = <&rpmhpd SM8450_CX>,
<&rpmhpd SM8450_MXC>;
power-domains = <&rpmhpd RPMHPD_CX>,
<&rpmhpd RPMHPD_MXC>;
power-domain-names = "cx", "mxc";
memory-region = <&cdsp_mem>;
......@@ -2585,8 +2586,8 @@ remoteproc_mpss: remoteproc@4080000 {
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "xo";
power-domains = <&rpmhpd SM8450_CX>,
<&rpmhpd SM8450_MSS>;
power-domains = <&rpmhpd RPMHPD_CX>,
<&rpmhpd RPMHPD_MSS>;
power-domain-names = "cx", "mss";
memory-region = <&mpss_mem>;
......@@ -2614,7 +2615,7 @@ videocc: clock-controller@aaf0000 {
reg = <0 0x0aaf0000 0 0x10000>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&gcc GCC_VIDEO_AHB_CLK>;
power-domains = <&rpmhpd SM8450_MMCX>;
power-domains = <&rpmhpd RPMHPD_MMCX>;
required-opps = <&rpmhpd_opp_low_svs>;
#clock-cells = <1>;
#reset-cells = <1>;
......@@ -2706,7 +2707,7 @@ camcc: clock-controller@ade0000 {
<&rpmhcc RPMH_CXO_CLK>,
<&rpmhcc RPMH_CXO_CLK_A>,
<&sleep_clk>;
power-domains = <&rpmhpd SM8450_MMCX>;
power-domains = <&rpmhpd RPMHPD_MMCX>;
required-opps = <&rpmhpd_opp_low_svs>;
#clock-cells = <1>;
#reset-cells = <1>;
......@@ -2772,7 +2773,7 @@ mdss_mdp: display-controller@ae01000 {
assigned-clock-rates = <19200000>;
operating-points-v2 = <&mdp_opp_table>;
power-domains = <&rpmhpd SM8450_MMCX>;
power-domains = <&rpmhpd RPMHPD_MMCX>;
interrupt-parent = <&mdss>;
interrupts = <0>;
......@@ -2864,7 +2865,7 @@ mdss_dp0: displayport-controller@ae90000 {
#sound-dai-cells = <0>;
operating-points-v2 = <&dp_opp_table>;
power-domains = <&rpmhpd SM8450_MMCX>;
power-domains = <&rpmhpd RPMHPD_MMCX>;
status = "disabled";
......@@ -2930,7 +2931,7 @@ mdss_dsi0: dsi@ae94000 {
assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
operating-points-v2 = <&mdss_dsi_opp_table>;
power-domains = <&rpmhpd SM8450_MMCX>;
power-domains = <&rpmhpd RPMHPD_MMCX>;
phys = <&mdss_dsi0_phy>;
phy-names = "dsi";
......@@ -3022,7 +3023,7 @@ mdss_dsi1: dsi@ae96000 {
assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>;
operating-points-v2 = <&mdss_dsi_opp_table>;
power-domains = <&rpmhpd SM8450_MMCX>;
power-domains = <&rpmhpd RPMHPD_MMCX>;
phys = <&mdss_dsi1_phy>;
phy-names = "dsi";
......@@ -3090,7 +3091,7 @@ dispcc: clock-controller@af00000 {
<0>,
<0>, /* dp3 */
<0>;
power-domains = <&rpmhpd SM8450_MMCX>;
power-domains = <&rpmhpd RPMHPD_MMCX>;
required-opps = <&rpmhpd_opp_low_svs>;
#clock-cells = <1>;
#reset-cells = <1>;
......@@ -4252,7 +4253,7 @@ sdhc_2: mmc@8804000 {
<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>;
interconnect-names = "sdhc-ddr","cpu-sdhc";
iommus = <&apps_smmu 0x4a0 0x0>;
power-domains = <&rpmhpd SM8450_CX>;
power-domains = <&rpmhpd RPMHPD_CX>;
operating-points-v2 = <&sdhc2_opp_table>;
bus-width = <4>;
dma-coherent;
......
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