Commit 8eee6b9d authored by Thor Thayer's avatar Thor Thayer Committed by Mark Brown

spi: Add Flag to Enable Slave Select with GPIO Chip Select.

Some SPI masters require slave selection before the transfer
can begin [1]. The SPI framework currently selects the chip using
either 1) the internal CS mechanism or 2) the GPIO CS, but not both.

This patch adds a new master->flags define to indicate both the GPIO
CS and the internal chip select mechanism should be used.

Tested On:
    Altera CycloneV development kit
    Compile tested for build errors on x86_64 (allyesconfigs)

[1] DesignWare dw_apb_ssi Databook, Version 3.20a (page 39)
Signed-off-by: default avatarThor Thayer <tthayer@opensource.altera.com>
Signed-off-by: default avatarMark Brown <broonie@kernel.org>
parent 1001354c
...@@ -697,10 +697,15 @@ static void spi_set_cs(struct spi_device *spi, bool enable) ...@@ -697,10 +697,15 @@ static void spi_set_cs(struct spi_device *spi, bool enable)
if (spi->mode & SPI_CS_HIGH) if (spi->mode & SPI_CS_HIGH)
enable = !enable; enable = !enable;
if (gpio_is_valid(spi->cs_gpio)) if (gpio_is_valid(spi->cs_gpio)) {
gpio_set_value(spi->cs_gpio, !enable); gpio_set_value(spi->cs_gpio, !enable);
else if (spi->master->set_cs) /* Some SPI masters need both GPIO CS & slave_select */
if ((spi->master->flags & SPI_MASTER_GPIO_SS) &&
spi->master->set_cs)
spi->master->set_cs(spi, !enable);
} else if (spi->master->set_cs) {
spi->master->set_cs(spi, !enable); spi->master->set_cs(spi, !enable);
}
} }
#ifdef CONFIG_HAS_DMA #ifdef CONFIG_HAS_DMA
......
...@@ -442,6 +442,7 @@ struct spi_master { ...@@ -442,6 +442,7 @@ struct spi_master {
#define SPI_MASTER_NO_TX BIT(2) /* can't do buffer write */ #define SPI_MASTER_NO_TX BIT(2) /* can't do buffer write */
#define SPI_MASTER_MUST_RX BIT(3) /* requires rx */ #define SPI_MASTER_MUST_RX BIT(3) /* requires rx */
#define SPI_MASTER_MUST_TX BIT(4) /* requires tx */ #define SPI_MASTER_MUST_TX BIT(4) /* requires tx */
#define SPI_MASTER_GPIO_SS BIT(5) /* GPIO CS must select slave */
/* /*
* on some hardware transfer / message size may be constrained * on some hardware transfer / message size may be constrained
......
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