Commit 8f214347 authored by Philipp Hortmann's avatar Philipp Hortmann Committed by Greg Kroah-Hartman

staging: rtl8192e: Join constants RadioA_ArrayLength with ..LengthPciE

Join constants RadioA_ArrayLength with RadioA_ArrayLengthPciE to
RTL8192E_RADIO_A_ARR_LEN to improve readability.
Signed-off-by: default avatarPhilipp Hortmann <philipp.g.hortmann@gmail.com>
Link: https://lore.kernel.org/r/a03372c15cf1489b964d48d667f39c6e231fa190.1678814935.git.philipp.g.hortmann@gmail.comSigned-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent 27d218e3
...@@ -542,7 +542,7 @@ u8 rtl92e_config_rf_path(struct net_device *dev, enum rf90_radio_path eRFPath) ...@@ -542,7 +542,7 @@ u8 rtl92e_config_rf_path(struct net_device *dev, enum rf90_radio_path eRFPath)
switch (eRFPath) { switch (eRFPath) {
case RF90_PATH_A: case RF90_PATH_A:
for (i = 0; i < RadioA_ArrayLength; i += 2) { for (i = 0; i < RTL8192E_RADIO_A_ARR_LEN; i += 2) {
if (Rtl819XRadioA_Array[i] == 0xfe) { if (Rtl819XRadioA_Array[i] == 0xfe) {
msleep(100); msleep(100);
continue; continue;
......
...@@ -9,7 +9,6 @@ ...@@ -9,7 +9,6 @@
#define MAX_DOZE_WAITING_TIMES_9x 64 #define MAX_DOZE_WAITING_TIMES_9x 64
#define RadioA_ArrayLength RadioA_ArrayLengthPciE
#define RadioB_ArrayLength RadioB_ArrayLengthPciE #define RadioB_ArrayLength RadioB_ArrayLengthPciE
#define MACPHY_Array_PGLength MACPHY_Array_PGLengthPciE #define MACPHY_Array_PGLength MACPHY_Array_PGLengthPciE
#define PHY_REG_1T2RArrayLength PHY_REG_1T2RArrayLengthPciE #define PHY_REG_1T2RArrayLength PHY_REG_1T2RArrayLengthPciE
......
...@@ -157,7 +157,7 @@ u32 Rtl8192PciEPHY_REG_1T2RArray[PHY_REG_1T2RArrayLengthPciE] = { ...@@ -157,7 +157,7 @@ u32 Rtl8192PciEPHY_REG_1T2RArray[PHY_REG_1T2RArrayLengthPciE] = {
0xe1c, 0x12121416, 0xe1c, 0x12121416,
}; };
u32 Rtl8192PciERadioA_Array[RadioA_ArrayLengthPciE] = { u32 Rtl8192PciERadioA_Array[RTL8192E_RADIO_A_ARR_LEN] = {
0x019, 0x00000003, 0x019, 0x00000003,
0x000, 0x000000bf, 0x000, 0x000000bf,
0x001, 0x00000ee0, 0x001, 0x00000ee0,
......
...@@ -13,8 +13,8 @@ ...@@ -13,8 +13,8 @@
#define PHY_REG_1T2RArrayLengthPciE 296 #define PHY_REG_1T2RArrayLengthPciE 296
extern u32 Rtl8192PciEPHY_REG_1T2RArray[PHY_REG_1T2RArrayLengthPciE]; extern u32 Rtl8192PciEPHY_REG_1T2RArray[PHY_REG_1T2RArrayLengthPciE];
#define RadioA_ArrayLengthPciE 246 #define RTL8192E_RADIO_A_ARR_LEN 246
extern u32 Rtl8192PciERadioA_Array[RadioA_ArrayLengthPciE]; extern u32 Rtl8192PciERadioA_Array[RTL8192E_RADIO_A_ARR_LEN];
#define RadioB_ArrayLengthPciE 78 #define RadioB_ArrayLengthPciE 78
extern u32 Rtl8192PciERadioB_Array[RadioB_ArrayLengthPciE]; extern u32 Rtl8192PciERadioB_Array[RadioB_ArrayLengthPciE];
#define RTL8192E_MACPHY_ARR_LEN 18 #define RTL8192E_MACPHY_ARR_LEN 18
......
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