Commit 8f4bb1e7 authored by Alex Deucher's avatar Alex Deucher

drm/amdgpu/sdma5.2: convert to IP version checking

Use IP versions rather than asic_type to differentiate
IP version specific features.
Acked-by: default avatarChristian König <christian.koenig@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 02200e91
...@@ -136,23 +136,23 @@ static int sdma_v5_2_init_microcode(struct amdgpu_device *adev) ...@@ -136,23 +136,23 @@ static int sdma_v5_2_init_microcode(struct amdgpu_device *adev)
DRM_DEBUG("\n"); DRM_DEBUG("\n");
switch (adev->asic_type) { switch (adev->ip_versions[SDMA0_HWIP]) {
case CHIP_SIENNA_CICHLID: case IP_VERSION(5, 2, 0):
chip_name = "sienna_cichlid"; chip_name = "sienna_cichlid";
break; break;
case CHIP_NAVY_FLOUNDER: case IP_VERSION(5, 2, 2):
chip_name = "navy_flounder"; chip_name = "navy_flounder";
break; break;
case CHIP_VANGOGH: case IP_VERSION(5, 2, 1):
chip_name = "vangogh"; chip_name = "vangogh";
break; break;
case CHIP_DIMGREY_CAVEFISH: case IP_VERSION(5, 2, 4):
chip_name = "dimgrey_cavefish"; chip_name = "dimgrey_cavefish";
break; break;
case CHIP_BEIGE_GOBY: case IP_VERSION(5, 2, 5):
chip_name = "beige_goby"; chip_name = "beige_goby";
break; break;
case CHIP_YELLOW_CARP: case IP_VERSION(5, 2, 3):
chip_name = "yellow_carp"; chip_name = "yellow_carp";
break; break;
default: default:
...@@ -174,7 +174,7 @@ static int sdma_v5_2_init_microcode(struct amdgpu_device *adev) ...@@ -174,7 +174,7 @@ static int sdma_v5_2_init_microcode(struct amdgpu_device *adev)
(void *)&adev->sdma.instance[0], (void *)&adev->sdma.instance[0],
sizeof(struct amdgpu_sdma_instance)); sizeof(struct amdgpu_sdma_instance));
if (amdgpu_sriov_vf(adev) && (adev->asic_type == CHIP_SIENNA_CICHLID)) if (amdgpu_sriov_vf(adev) && (adev->ip_versions[SDMA0_HWIP] == IP_VERSION(5, 2, 0)))
return 0; return 0;
DRM_DEBUG("psp_load == '%s'\n", DRM_DEBUG("psp_load == '%s'\n",
...@@ -1217,17 +1217,17 @@ static int sdma_v5_2_early_init(void *handle) ...@@ -1217,17 +1217,17 @@ static int sdma_v5_2_early_init(void *handle)
{ {
struct amdgpu_device *adev = (struct amdgpu_device *)handle; struct amdgpu_device *adev = (struct amdgpu_device *)handle;
switch (adev->asic_type) { switch (adev->ip_versions[SDMA0_HWIP]) {
case CHIP_SIENNA_CICHLID: case IP_VERSION(5, 2, 0):
adev->sdma.num_instances = 4; adev->sdma.num_instances = 4;
break; break;
case CHIP_NAVY_FLOUNDER: case IP_VERSION(5, 2, 2):
case CHIP_DIMGREY_CAVEFISH: case IP_VERSION(5, 2, 4):
adev->sdma.num_instances = 2; adev->sdma.num_instances = 2;
break; break;
case CHIP_VANGOGH: case IP_VERSION(5, 2, 1):
case CHIP_BEIGE_GOBY: case IP_VERSION(5, 2, 5):
case CHIP_YELLOW_CARP: case IP_VERSION(5, 2, 3):
adev->sdma.num_instances = 1; adev->sdma.num_instances = 1;
break; break;
default: default:
...@@ -1555,7 +1555,7 @@ static void sdma_v5_2_update_medium_grain_clock_gating(struct amdgpu_device *ade ...@@ -1555,7 +1555,7 @@ static void sdma_v5_2_update_medium_grain_clock_gating(struct amdgpu_device *ade
for (i = 0; i < adev->sdma.num_instances; i++) { for (i = 0; i < adev->sdma.num_instances; i++) {
if (adev->sdma.instance[i].fw_version < 70 && adev->asic_type == CHIP_VANGOGH) if (adev->sdma.instance[i].fw_version < 70 && adev->ip_versions[SDMA0_HWIP] == IP_VERSION(5, 2, 1))
adev->cg_flags &= ~AMD_CG_SUPPORT_SDMA_MGCG; adev->cg_flags &= ~AMD_CG_SUPPORT_SDMA_MGCG;
if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) { if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) {
...@@ -1592,7 +1592,7 @@ static void sdma_v5_2_update_medium_grain_light_sleep(struct amdgpu_device *adev ...@@ -1592,7 +1592,7 @@ static void sdma_v5_2_update_medium_grain_light_sleep(struct amdgpu_device *adev
for (i = 0; i < adev->sdma.num_instances; i++) { for (i = 0; i < adev->sdma.num_instances; i++) {
if (adev->sdma.instance[i].fw_version < 70 && adev->asic_type == CHIP_VANGOGH) if (adev->sdma.instance[i].fw_version < 70 && adev->ip_versions[SDMA0_HWIP] == IP_VERSION(5, 2, 1))
adev->cg_flags &= ~AMD_CG_SUPPORT_SDMA_LS; adev->cg_flags &= ~AMD_CG_SUPPORT_SDMA_LS;
if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) { if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) {
...@@ -1621,13 +1621,13 @@ static int sdma_v5_2_set_clockgating_state(void *handle, ...@@ -1621,13 +1621,13 @@ static int sdma_v5_2_set_clockgating_state(void *handle,
if (amdgpu_sriov_vf(adev)) if (amdgpu_sriov_vf(adev))
return 0; return 0;
switch (adev->asic_type) { switch (adev->ip_versions[SDMA0_HWIP]) {
case CHIP_SIENNA_CICHLID: case IP_VERSION(5, 2, 0):
case CHIP_NAVY_FLOUNDER: case IP_VERSION(5, 2, 2):
case CHIP_VANGOGH: case IP_VERSION(5, 2, 1):
case CHIP_DIMGREY_CAVEFISH: case IP_VERSION(5, 2, 4):
case CHIP_BEIGE_GOBY: case IP_VERSION(5, 2, 5):
case CHIP_YELLOW_CARP: case IP_VERSION(5, 2, 3):
sdma_v5_2_update_medium_grain_clock_gating(adev, sdma_v5_2_update_medium_grain_clock_gating(adev,
state == AMD_CG_STATE_GATE); state == AMD_CG_STATE_GATE);
sdma_v5_2_update_medium_grain_light_sleep(adev, sdma_v5_2_update_medium_grain_light_sleep(adev,
......
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment