Skip to content

L
linux
Commit 8f9596e3 authored by Andrew Morton's avatar Andrew Morton Committed by Linus Torvalds
Browse files
Options

[PATCH] sn: kill big endian stuff 

From: Pat Gefre <pfg@sgi.com>

kill big endian stuff
parent 6378da80
Hide whitespace changes
Inline Side-by-side
Showing with 0 additions and 416 deletions
arch/ia64/sn/Makefile
View file @ 8f9596e3
......@@ -9,6 +9,4 @@
# Makefile for the sn ia64 subplatform
#
EXTRA_CFLAGS := -DLITTLE_ENDIAN
obj-y += kernel/ io/
arch/ia64/sn/io/Makefile
View file @ 8f9596e3
......@@ -9,7 +9,5 @@
# Makefile for the sn io routines.
#
EXTRA_CFLAGS := -DLITTLE_ENDIAN
obj-y += sgi_if.o xswitch.o sgi_io_sim.o cdl.o \
io.o machvec/ drivers/ platform_init/ sn2/ hwgfs/
arch/ia64/sn/io/drivers/Makefile
View file @ 8f9596e3
......@@ -7,6 +7,4 @@
#
# Makefile for the sn2 io routines.
EXTRA_CFLAGS := -DLITTLE_ENDIAN
obj-y += ioconfig_bus.o
arch/ia64/sn/io/hwgfs/Makefile
View file @ 8f9596e3
......@@ -7,6 +7,4 @@
#
# Makefile for the sn2 io routines.
EXTRA_CFLAGS := -DLITTLE_ENDIAN
obj-y += hcl.o labelcl.o hcl_util.o ramfs.o interface.o
arch/ia64/sn/io/machvec/Makefile
View file @ 8f9596e3
......@@ -7,6 +7,4 @@
#
# Makefile for the sn2 io routines.
EXTRA_CFLAGS := -DLITTLE_ENDIAN
obj-y += pci.o pci_dma.o pci_bus_cvlink.o iomv.o
arch/ia64/sn/io/platform_init/Makefile
View file @ 8f9596e3
......@@ -7,6 +7,4 @@
#
# Makefile for the sn2 io routines.
EXTRA_CFLAGS := -DLITTLE_ENDIAN
obj-y += sgi_io_init.o irix_io_init.o
arch/ia64/sn/io/sn2/Makefile
View file @ 8f9596e3
......@@ -9,8 +9,6 @@
# Makefile for the sn2 specific io routines.
#
EXTRA_CFLAGS := -DLITTLE_ENDIAN
obj-y += pcibr/ ml_SN_intr.o shub_intr.o shuberror.o shub.o bte_error.o \
pic.o geo_op.o l1_command.o klconflib.o klgraph.o ml_SN_init.o \
ml_iograph.o module.o pciio.o xbow.o xtalk.o shubio.o
arch/ia64/sn/io/sn2/pcibr/Makefile
View file @ 8f9596e3
......@@ -9,7 +9,5 @@
# Makefile for the sn2 specific pci bridge routines.
#
EXTRA_CFLAGS := -DLITTLE_ENDIAN
obj-y += pcibr_ate.o pcibr_config.o pcibr_dvr.o pcibr_hints.o pcibr_intr.o pcibr_rrb.o \
pcibr_slot.o pcibr_error.o
arch/ia64/sn/kernel/Makefile
View file @ 8f9596e3
......@@ -7,7 +7,5 @@
# Copyright (C) 1999,2001-2003 Silicon Graphics, Inc. All Rights Reserved.
#
EXTRA_CFLAGS := -DLITTLE_ENDIAN
obj-y += probe.o setup.o bte.o irq.o mca.o idle.o sn2/
obj-$(CONFIG_IA64_GENERIC) += machvec.o
arch/ia64/sn/kernel/sn2/Makefile
View file @ 8f9596e3
......@@ -9,7 +9,5 @@
# sn2 specific kernel files
#
EXTRA_CFLAGS := -DLITTLE_ENDIAN
obj-y += cache.o io.o ptc_deadlock.o sn2_smp.o sn_proc_fs.o \
prominfo_proc.o timer.o
include/asm-ia64/sn/pci/pci_defs.h
View file @ 8f9596e3
......@@ -321,8 +321,6 @@ extern void pci_write(void * address, int data, int type);
#ifndef __ASSEMBLY__
#ifdef LITTLE_ENDIAN
/*
* PCI config space definition
*/
......@@ -425,111 +423,5 @@ typedef volatile struct cap_pcix_type0_s {
cap_pcix_stat_reg_t pcix_type0_status;
} cap_pcix_type0_t;
#else
/*
* PCI config space definition
*/
typedef volatile struct pci_cfg_s {
uint16_t dev_id;
uint16_t vendor_id;
uint16_t status;
uint16_t cmd;
uchar_t class;
uchar_t sub_class;
uchar_t prog_if;
uchar_t rev;
uchar_t bist;
uchar_t hdr_type;
uchar_t lt;
uchar_t line_size;
uint32_t bar[6];
uint32_t cardbus;
uint16_t subsys_dev_id;
uint16_t subsys_vendor_id;
uint32_t exp_rom;
uint32_t res[2];
uchar_t max_lat;
uchar_t min_gnt;
uchar_t int_pin;
uchar_t int_line;
} pci_cfg_t;
/*
* PCI Type 1 config space definition for PCI to PCI Bridges (PPBs)
*/
typedef volatile struct pci_cfg1_s {
uint16_t dev_id;
uint16_t vendor_id;
uint16_t status;
uint16_t cmd;
uchar_t class;
uchar_t sub_class;
uchar_t prog_if;
uchar_t rev;
uchar_t bist;
uchar_t hdr_type;
uchar_t lt;
uchar_t line_size;
uint32_t bar[2];
uchar_t slt;
uchar_t sub_bus_num;
uchar_t snd_bus_num;
uchar_t pri_bus_num;
uint16_t snd_status;
uchar_t io_limit;
uchar_t io_base;
uint16_t mem_limit;
uint16_t mem_base;
uint16_t pmem_limit;
uint16_t pmem_base;
uint32_t pmem_limit_upper;
uint32_t pmem_base_upper;
uint16_t io_limit_upper;
uint16_t io_base_upper;
uint32_t res;
uint32_t exp_rom;
uint16_t ppb_control;
uchar_t int_pin;
uchar_t int_line;
} pci_cfg1_t;
/*
* PCI-X Capability
*/
typedef volatile struct cap_pcix_cmd_reg_s {
uint16_t reserved1: 9,
max_split: 3,
max_mem_read_cnt: 2,
enable_relaxed_order: 1,
data_parity_enable: 1;
} cap_pcix_cmd_reg_t;
typedef volatile struct cap_pcix_stat_reg_s {
uint32_t reserved1: 2,
split_complt_err: 1,
max_cum_read: 3,
max_out_split: 3,
max_mem_read_cnt: 2,
device_complex: 1,
unexpect_split_complt: 1,
split_complt_discard: 1,
mhz133_capable: 1,
bit64_device: 1,
bus_num: 8,
dev_num: 5,
func_num: 3;
} cap_pcix_stat_reg_t;
typedef volatile struct cap_pcix_type0_s {
cap_pcix_cmd_reg_t pcix_type0_command;
uchar_t pcix_cap_nxt;
uchar_t pcix_cap_id;
cap_pcix_stat_reg_t pcix_type0_status;
} cap_pcix_type0_t;
#endif
#endif /* __ASSEMBLY__ */
#endif /* _ASM_SN_PCI_PCI_DEFS_H */
include/asm-ia64/sn/xtalk/xbow.h
View file @ 8f9596e3
......@@ -64,7 +64,6 @@ typedef uint32_t xbowreg_t;
/* Register set for each xbow link */
typedef volatile struct xb_linkregs_s {
#ifdef LITTLE_ENDIAN
/*
* we access these through synergy unswizzled space, so the address
* gets twiddled (i.e. references to 0x4 actually go to 0x0 and vv.)
......@@ -86,24 +85,6 @@ typedef volatile struct xb_linkregs_s {
xbowreg_t filler6;
xbowreg_t link_aux_status;
xbowreg_t filler7;
#else
xbowreg_t filler0; /* filler for proper alignment */
xbowreg_t link_ibf;
xbowreg_t filler1;
xbowreg_t link_control;
xbowreg_t filler2;
xbowreg_t link_status;
xbowreg_t filler3;
xbowreg_t link_arb_upper;
xbowreg_t filler4;
xbowreg_t link_arb_lower;
xbowreg_t filler5;
xbowreg_t link_status_clr;
xbowreg_t filler6;
xbowreg_t link_reset;
xbowreg_t filler7;
xbowreg_t link_aux_status;
#endif /* LITTLE_ENDIAN */
} xb_linkregs_t;
typedef volatile struct xbow_s {
......@@ -124,7 +105,6 @@ typedef volatile struct xbow_s {
#define xb_wid_llp xb_widget.w_llp_cfg
#define xb_wid_stat_clr xb_widget.w_tflush
#ifdef LITTLE_ENDIAN
/*
* we access these through synergy unswizzled space, so the address
* gets twiddled (i.e. references to 0x4 actually go to 0x0 and vv.)
......@@ -165,43 +145,6 @@ typedef volatile struct xbow_s {
xbowreg_t _pad_0000c8;
/* end of Xbridge only */
xbowreg_t _pad_0000d0[12];
#else
/* xbow-specific widget configuration 0x000058-0x0000FF */
xbowreg_t _pad_000058;
xbowreg_t xb_wid_arb_reload; /* 0x00005C */
xbowreg_t _pad_000060;
xbowreg_t xb_perf_ctr_a; /* 0x000064 */
xbowreg_t _pad_000068;
xbowreg_t xb_perf_ctr_b; /* 0x00006c */
xbowreg_t _pad_000070;
xbowreg_t xb_nic; /* 0x000074 */
/* Xbridge only */
xbowreg_t _pad_000078;
xbowreg_t xb_w0_rst_fnc; /* 0x00007C */
xbowreg_t _pad_000080;
xbowreg_t xb_l8_rst_fnc; /* 0x000084 */
xbowreg_t _pad_000088;
xbowreg_t xb_l9_rst_fnc; /* 0x00008c */
xbowreg_t _pad_000090;
xbowreg_t xb_la_rst_fnc; /* 0x000094 */
xbowreg_t _pad_000098;
xbowreg_t xb_lb_rst_fnc; /* 0x00009c */
xbowreg_t _pad_0000a0;
xbowreg_t xb_lc_rst_fnc; /* 0x0000a4 */
xbowreg_t _pad_0000a8;
xbowreg_t xb_ld_rst_fnc; /* 0x0000ac */
xbowreg_t _pad_0000b0;
xbowreg_t xb_le_rst_fnc; /* 0x0000b4 */
xbowreg_t _pad_0000b8;
xbowreg_t xb_lf_rst_fnc; /* 0x0000bc */
xbowreg_t _pad_0000c0;
xbowreg_t xb_lock; /* 0x0000c4 */
xbowreg_t _pad_0000c8;
xbowreg_t xb_lock_clr; /* 0x0000cc */
/* end of Xbridge only */
xbowreg_t _pad_0000d0[12];
#endif /* LITTLE_ENDIAN */
/* Link Specific Registers, port 8..15 0x000100-0x000300 */
xb_linkregs_t xb_link_raw[MAX_XBOW_PORTS];
......@@ -430,8 +373,6 @@ typedef struct xbow_cfg_s {
/*
* Xbow Widget 0 Command error word
*/
#ifdef LITTLE_ENDIAN
typedef union xbw0_cmdword_u {
xbowreg_t cmdword;
struct {
......@@ -450,27 +391,6 @@ typedef union xbw0_cmdword_u {
} xbw0_cmdfield;
} xbw0_cmdword_t;
#else
typedef union xbw0_cmdword_u {
xbowreg_t cmdword;
struct {
uint32_t destid:4, /* Desination ID number */
srcid:4, /* Source ID number */
pactyp:4, /* Packet type: */
tnum:5, /* Transaction Number */
ct:1, /* Is it a coherent transaction */
ds:2, /* Data size */
gbr:1, /* GBR enable ? */
vbpm:1, /* Virtual Backplane message */
error:1, /* Error Occured */
barr:1, /* Barrier operation */
rsvd:8; /* Reserved */
} xbw0_cmdfield;
} xbw0_cmdword_t;
#endif
#define xbcmd_destid xbw0_cmdfield.destid
#define xbcmd_srcid xbw0_cmdfield.srcid
#define xbcmd_pactyp xbw0_cmdfield.pactyp
......@@ -505,7 +425,6 @@ typedef union xbw0_cmdword_u {
/*
* Xbow widget 0 Status register format.
*/
#ifdef LITTLE_ENDIAN
typedef union xbw0_status_u {
xbowreg_t statusword;
......@@ -524,28 +443,6 @@ typedef union xbw0_status_u {
} xbw0_stfield;
} xbw0_status_t;
#else
typedef union xbw0_status_u {
xbowreg_t statusword;
struct {
uint32_t linkXintr:8, /* link(x) error intr */
wid0intr:1, /* Widget 0 err intr */
resvd1:13,
src_id:4, /* source id. Xbridge only */
regacc_err:1, /* Reg Access error */
/* Xbridge only */
w0_recv_tout, /* receive timeout err */
w0_arb_tout, /* arbiter timeout err */
/* End of Xbridge only */
xtalk_err:1, /* Xtalk pkt with error bit */
connect_tout:1, /* Connection timeout */
mult_err:1; /* Multiple error occurred */
} xbw0_stfield;
} xbw0_status_t;
#endif
#define xbst_linkXintr xbw0_stfield.linkXintr
#define xbst_w0intr xbw0_stfield.wid0intr
#define xbst_regacc_err xbw0_stfield.regacc_err
......@@ -559,7 +456,6 @@ typedef union xbw0_status_u {
/*
* Xbow widget 0 Control register format
*/
#ifdef LITTLE_ENDIAN
typedef union xbw0_ctrl_u {
xbowreg_t ctrlword;
......@@ -577,28 +473,6 @@ typedef union xbw0_ctrl_u {
} xbw0_ctrlfield;
} xbw0_ctrl_t;
#else
typedef union xbw0_ctrl_u {
xbowreg_t ctrlword;
struct {
uint32_t
resvd1:24,
enable_watchdog:1, /* Xbridge only */
enable_w0_tout_cntr:1, /* Xbridge only */
accerr_intr:1,
w0_recv_tout_intr:1, /* Xbridge only */
w0_arg_tout_intr:1, /* Xbridge only */
xtalkerr_intr:1,
conntout_intr:1,
resvd3:1;
} xbw0_ctrlfield;
} xbw0_ctrl_t;
#endif
#ifdef LITTLE_ENDIAN
typedef union xbow_linkctrl_u {
xbowreg_t xbl_ctrlword;
struct {
......@@ -625,36 +499,6 @@ typedef union xbow_linkctrl_u {
} xb_linkcontrol;
} xbow_linkctrl_t;
#else
typedef union xbow_linkctrl_u {
xbowreg_t xbl_ctrlword;
struct {
uint32_t alive_intr:1,
rsvd1:1,
perf_mode:2,
inbuf_level:3,
send_bm8:1,
force_badllp:1,
llp_credit:5,
idest_intr:1,
obuf_intr:1,
rsvd2:7,
bwalloc_intr:1,
rcvov_intr:1,
trxov_intr:1,
trx_max_retry_intr:1,
rcv_err_intr:1,
trx_retry_intr:1,
rsvd3:1,
maxto_intr:1,
srcto_intr:1;
} xb_linkcontrol;
} xbow_linkctrl_t;
#endif
#define xbctl_accerr_intr (xbw0_ctrlfield.accerr_intr)
#define xbctl_xtalkerr_intr (xbw0_ctrlfield.xtalkerr_intr)
#define xbctl_cnntout_intr (xbw0_ctrlfield.conntout_intr)
......@@ -667,8 +511,6 @@ typedef union xbow_linkctrl_u {
* Xbow Link specific Registers structure definitions.
*/
#ifdef LITTLE_ENDIAN
typedef union xbow_linkX_status_u {
xbowreg_t linkstatus;
struct {
......@@ -689,30 +531,6 @@ typedef union xbow_linkX_status_u {
} xb_linkstatus;
} xbwX_stat_t;
#else
typedef union xbow_linkX_status_u {
xbowreg_t linkstatus;
struct {
uint32_t alive:1,
resvd1:12,
merror:1,
illdest:1,
ioe:1, /* Input overallocation error */
bw_errport:8, /* BW allocation error port */
llp_rxovflow:1,
llp_txovflow:1,
llp_maxtxretry:1,
llp_rcverror:1,
llp_xmitretry:1,
pkt_toutdest:1, /* reserved in Xbridge */
pkt_toutconn:1, /* max_req_tout in Xbridge */
pkt_toutsrc:1;
} xb_linkstatus;
} xbwX_stat_t;
#endif
#define link_alive xb_linkstatus.alive
#define link_multierror xb_linkstatus.merror
#define link_illegal_dest xb_linkstatus.illdest
......@@ -722,8 +540,6 @@ typedef union xbow_linkX_status_u {
#define link_pkt_toutdest xb_linkstatus.pkt_toutdest
#define link_pkt_toutsrc xb_linkstatus.pkt_toutsrc
#ifdef LITTLE_ENDIAN
typedef union xbow_aux_linkX_status_u {
xbowreg_t aux_linkstatus;
struct {
......@@ -738,27 +554,6 @@ typedef union xbow_aux_linkX_status_u {
} xb_aux_linkstatus;
} xbow_aux_link_status_t;
#else
typedef union xbow_aux_linkX_status_u {
xbowreg_t aux_linkstatus;
struct {
uint32_t rx_err_cnt:8,
tx_retry_cnt:8,
to_src_loc:8,
rsvd1:1,
fail_mode:1,
wid_present:1,
bit_mode_8:1,
rsvd2:4;
} xb_aux_linkstatus;
} xbow_aux_link_status_t;
#endif
#ifdef LITTLE_ENDIAN
typedef union xbow_perf_count_u {
xbowreg_t xb_counter_val;
struct {
......@@ -768,19 +563,6 @@ typedef union xbow_perf_count_u {
} xb_perf;
} xbow_perfcount_t;
#else
typedef union xbow_perf_count_u {
xbowreg_t xb_counter_val;
struct {
uint32_t rsvd:9,
link_select:3,
count:20;
} xb_perf;
} xbow_perfcount_t;
#endif
#define XBOW_COUNTER_MASK 0xFFFFF
extern int xbow_widget_present(xbow_t * xbow, int port);
......
include/asm-ia64/sn/xtalk/xwidget.h
View file @ 8f9596e3
......@@ -18,7 +18,6 @@
#include <asm/sn/cdl.h>
#endif /* __ASSEMBLY__ */
#ifdef LITTLE_ENDIAN
#define WIDGET_ID 0x00
#define WIDGET_STATUS 0x08
#define WIDGET_ERR_UPPER_ADDR 0x10
......@@ -30,19 +29,6 @@
#define WIDGET_ERR_CMD_WORD 0x40
#define WIDGET_LLP_CFG 0x48
#define WIDGET_TFLUSH 0x50
#else /* !LITTLE_ENDIAN */
#define WIDGET_ID 0x04
#define WIDGET_STATUS 0x0c
#define WIDGET_ERR_UPPER_ADDR 0x14
#define WIDGET_ERR_LOWER_ADDR 0x1c
#define WIDGET_CONTROL 0x24
#define WIDGET_REQ_TIMEOUT 0x2c
#define WIDGET_INTDEST_UPPER_ADDR 0x34
#define WIDGET_INTDEST_LOWER_ADDR 0x3c
#define WIDGET_ERR_CMD_WORD 0x44
#define WIDGET_LLP_CFG 0x4c
#define WIDGET_TFLUSH 0x54
#endif
/* WIDGET_ID */
#define WIDGET_REV_NUM 0xf0000000
......@@ -120,7 +106,6 @@ typedef uint32_t widgetreg_t;
/* widget configuration registers */
typedef volatile struct widget_cfg {
#ifdef LITTLE_ENDIAN
/*
* we access these through synergy unswizzled space, so the address
* gets twiddled (i.e. references to 0x4 actually go to 0x0 and vv.)
......@@ -148,33 +133,8 @@ typedef volatile struct widget_cfg {
widgetreg_t w_pad_9; /* 0x48 */
widgetreg_t w_tflush; /* 0x54 */
widgetreg_t w_pad_10; /* 0x50 */
#else
widgetreg_t w_pad_0; /* 0x00 */
widgetreg_t w_id; /* 0x04 */
widgetreg_t w_pad_1; /* 0x08 */
widgetreg_t w_status; /* 0x0c */
widgetreg_t w_pad_2; /* 0x10 */
widgetreg_t w_err_upper_addr; /* 0x14 */
widgetreg_t w_pad_3; /* 0x18 */
widgetreg_t w_err_lower_addr; /* 0x1c */
widgetreg_t w_pad_4; /* 0x20 */
widgetreg_t w_control; /* 0x24 */
widgetreg_t w_pad_5; /* 0x28 */
widgetreg_t w_req_timeout; /* 0x2c */
widgetreg_t w_pad_6; /* 0x30 */
widgetreg_t w_intdest_upper_addr; /* 0x34 */
widgetreg_t w_pad_7; /* 0x38 */
widgetreg_t w_intdest_lower_addr; /* 0x3c */
widgetreg_t w_pad_8; /* 0x40 */
widgetreg_t w_err_cmd_word; /* 0x44 */
widgetreg_t w_pad_9; /* 0x48 */
widgetreg_t w_llp_cfg; /* 0x4c */
widgetreg_t w_pad_10; /* 0x50 */
widgetreg_t w_tflush; /* 0x54 */
#endif /* LITTLE_ENDIAN */
} widget_cfg_t;
#ifdef LITTLE_ENDIAN
typedef struct {
unsigned other:8;
unsigned bo:1;
......@@ -188,33 +148,11 @@ typedef struct {
unsigned sidn:4;
unsigned didn:4;
} w_err_cmd_word_f;
#else
typedef struct {
unsigned didn:4;
unsigned sidn:4;
unsigned pactyp:4;
unsigned tnum:5;
unsigned ct:1;
unsigned ds:2;
unsigned gbr:1;
unsigned vbpm:1;
unsigned error:1;
unsigned bo:1;
unsigned other:8;
} w_err_cmd_word_f;
#endif
#ifdef LITTLE_ENDIAN
typedef union {
w_err_cmd_word_f f;
widgetreg_t r;
} w_err_cmd_word_u;
#else
typedef union {
widgetreg_t r;
w_err_cmd_word_f f;
} w_err_cmd_word_u;
#endif
/* IO widget initialization function */
typedef struct xwidget_info_s *xwidget_info_t;
......@@ -222,19 +160,11 @@ typedef struct xwidget_info_s *xwidget_info_t;
/*
* Crosstalk Widget Hardware Identification, as defined in the Crosstalk spec.
*/
#ifdef LITTLE_ENDIAN
typedef struct xwidget_hwid_s {
xwidget_mfg_num_t mfg_num;
xwidget_rev_num_t rev_num;
xwidget_part_num_t part_num;
} *xwidget_hwid_t;
#else
typedef struct xwidget_hwid_s {
xwidget_part_num_t part_num;
xwidget_rev_num_t rev_num;
xwidget_mfg_num_t mfg_num;
} *xwidget_hwid_t;
#endif
/*
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment
GitLab Nexedi Edition | About GitLab | About Nexedi | 沪ICP备2021021310号-2 | 沪ICP备2021021310号-7