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Commit 8fe25ba3 authored by Dmitry Baryshkov's avatar Dmitry Baryshkov Committed by Bjorn Andersson
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arm64: dts: qcom: sdm845: rename labels for DSI nodes 

Currently in board files MDSS and DSI nodes stay apart, because labels
for DSI nodes do not have the mdss_ prefix. It was found that grouping
all display-related notes is more useful.

To keep all display-related nodes close in the board files, change DSI
node labels from dsi_* to mdss_dsi_*.
Signed-off-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: default avatarKonrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: default avatarBjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230531011623.3808538-12-dmitry.baryshkov@linaro.org
parent 8e61d532
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Showing with 314 additions and 314 deletions
arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi
View file @ 8fe25ba3
......@@ -636,25 +636,6 @@ src_pp600_s3c: smps3 {
};
};
&dsi0 {
status = "okay";
vdda-supply = <&vdda_mipi_dsi0_1p2>;
ports {
port@1 {
endpoint {
remote-endpoint = <&sn65dsi86_in>;
data-lanes = <0 1 2 3>;
};
};
};
};
&dsi0_phy {
status = "okay";
vdds-supply = <&vdda_mipi_dsi0_pll>;
};
edp_brij_i2c: &i2c3 {
status = "okay";
clock-frequency = <400000>;
......@@ -687,7 +668,7 @@ ports {
port@0 {
reg = <0>;
sn65dsi86_in: endpoint {
remote-endpoint = <&dsi0_out>;
remote-endpoint = <&mdss_dsi0_out>;
};
};
......@@ -767,6 +748,25 @@ &mdss {
status = "okay";
};
&mdss_dsi0 {
status = "okay";
vdda-supply = <&vdda_mipi_dsi0_1p2>;
ports {
port@1 {
endpoint {
remote-endpoint = <&sn65dsi86_in>;
data-lanes = <0 1 2 3>;
};
};
};
};
&mdss_dsi0_phy {
status = "okay";
vdds-supply = <&vdda_mipi_dsi0_pll>;
};
/*
* Cheza fw does not properly program the GPU aperture to allow the
* GPU to update the SMMU pagetables for context switches. Work
......
arch/arm64/boot/dts/qcom/sdm845-db845c.dts
View file @ 8fe25ba3
......@@ -415,53 +415,6 @@ &cdsp_pas {
firmware-name = "qcom/sdm845/cdsp.mbn";
};
&dsi0 {
status = "okay";
vdda-supply = <&vreg_l26a_1p2>;
qcom,dual-dsi-mode;
qcom,master-dsi;
ports {
port@1 {
endpoint {
remote-endpoint = <&lt9611_a>;
data-lanes = <0 1 2 3>;
};
};
};
};
&dsi0_phy {
status = "okay";
vdds-supply = <&vreg_l1a_0p875>;
};
&dsi1 {
vdda-supply = <&vreg_l26a_1p2>;
qcom,dual-dsi-mode;
/* DSI1 is slave, so use DSI0 clocks */
assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>;
status = "okay";
ports {
port@1 {
endpoint {
remote-endpoint = <&lt9611_b>;
data-lanes = <0 1 2 3>;
};
};
};
};
&dsi1_phy {
vdds-supply = <&vreg_l1a_0p875>;
status = "okay";
};
&gcc {
protected-clocks = <GCC_QSPI_CORE_CLK>,
<GCC_QSPI_CORE_CLK_SRC>,
......@@ -517,7 +470,7 @@ port@0 {
reg = <0>;
lt9611_a: endpoint {
remote-endpoint = <&dsi0_out>;
remote-endpoint = <&mdss_dsi0_out>;
};
};
......@@ -525,7 +478,7 @@ port@1 {
reg = <1>;
lt9611_b: endpoint {
remote-endpoint = <&dsi1_out>;
remote-endpoint = <&mdss_dsi1_out>;
};
};
......@@ -556,6 +509,53 @@ &mdss {
status = "okay";
};
&mdss_dsi0 {
status = "okay";
vdda-supply = <&vreg_l26a_1p2>;
qcom,dual-dsi-mode;
qcom,master-dsi;
ports {
port@1 {
endpoint {
remote-endpoint = <&lt9611_a>;
data-lanes = <0 1 2 3>;
};
};
};
};
&mdss_dsi0_phy {
status = "okay";
vdds-supply = <&vreg_l1a_0p875>;
};
&mdss_dsi1 {
vdda-supply = <&vreg_l26a_1p2>;
qcom,dual-dsi-mode;
/* DSI1 is slave, so use DSI0 clocks */
assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
status = "okay";
ports {
port@1 {
endpoint {
remote-endpoint = <&lt9611_b>;
data-lanes = <0 1 2 3>;
};
};
};
};
&mdss_dsi1_phy {
vdds-supply = <&vreg_l1a_0p875>;
status = "okay";
};
&mss_pil {
status = "okay";
firmware-name = "qcom/sdm845/mba.mbn", "qcom/sdm845/modem.mbn";
......
arch/arm64/boot/dts/qcom/sdm845-mtp.dts
View file @ 8fe25ba3
......@@ -417,7 +417,43 @@ &cdsp_pas {
firmware-name = "qcom/sdm845/cdsp.mdt";
};
&dsi0 {
&gcc {
protected-clocks = <GCC_QSPI_CORE_CLK>,
<GCC_QSPI_CORE_CLK_SRC>,
<GCC_QSPI_CNOC_PERIPH_AHB_CLK>,
<GCC_LPASS_Q6_AXI_CLK>,
<GCC_LPASS_SWAY_CLK>;
};
&gmu {
status = "okay";
};
&gpu {
status = "okay";
zap-shader {
memory-region = <&gpu_mem>;
firmware-name = "qcom/sdm845/a630_zap.mbn";
};
};
&i2c10 {
status = "okay";
clock-frequency = <400000>;
};
&ipa {
qcom,gsi-loader = "self";
memory-region = <&ipa_fw_mem>;
status = "okay";
};
&mdss {
status = "okay";
};
&mdss_dsi0 {
status = "okay";
vdda-supply = <&vdda_mipi_dsi0_1p2>;
......@@ -448,33 +484,33 @@ ports {
port@0 {
reg = <0>;
truly_in_0: endpoint {
remote-endpoint = <&dsi0_out>;
remote-endpoint = <&mdss_dsi0_out>;
};
};
port@1 {
reg = <1>;
truly_in_1: endpoint {
remote-endpoint = <&dsi1_out>;
remote-endpoint = <&mdss_dsi1_out>;
};
};
};
};
};
&dsi0_phy {
&mdss_dsi0_phy {
status = "okay";
vdds-supply = <&vdda_mipi_dsi0_pll>;
};
&dsi1 {
&mdss_dsi1 {
status = "okay";
vdda-supply = <&vdda_mipi_dsi1_1p2>;
qcom,dual-dsi-mode;
/* DSI1 is slave, so use DSI0 clocks */
assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>;
assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
ports {
port@1 {
......@@ -486,47 +522,11 @@ endpoint {
};
};
&dsi1_phy {
&mdss_dsi1_phy {
status = "okay";
vdds-supply = <&vdda_mipi_dsi1_pll>;
};
&gcc {
protected-clocks = <GCC_QSPI_CORE_CLK>,
<GCC_QSPI_CORE_CLK_SRC>,
<GCC_QSPI_CNOC_PERIPH_AHB_CLK>,
<GCC_LPASS_Q6_AXI_CLK>,
<GCC_LPASS_SWAY_CLK>;
};
&gmu {
status = "okay";
};
&gpu {
status = "okay";
zap-shader {
memory-region = <&gpu_mem>;
firmware-name = "qcom/sdm845/a630_zap.mbn";
};
};
&i2c10 {
status = "okay";
clock-frequency = <400000>;
};
&ipa {
qcom,gsi-loader = "self";
memory-region = <&ipa_fw_mem>;
status = "okay";
};
&mdss {
status = "okay";
};
&mss_pil {
status = "okay";
firmware-name = "qcom/sdm845/mba.mbn", "qcom/sdm845/modem.mbn";
......
arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi
View file @ 8fe25ba3
......@@ -336,44 +336,6 @@ &cdsp_pas {
firmware-name = "qcom/sdm845/oneplus6/cdsp.mbn";
};
&dsi0 {
status = "okay";
vdda-supply = <&vdda_mipi_dsi0_1p2>;
/*
* Both devices use different panels but all other properties
* are common. Compatible line is declared in device dts.
*/
display_panel: panel@0 {
status = "disabled";
reg = <0>;
vddio-supply = <&vreg_l14a_1p88>;
reset-gpios = <&tlmm 6 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&panel_reset_pins &panel_te_pin &panel_esd_pin>;
port {
panel_in: endpoint {
remote-endpoint = <&dsi0_out>;
};
};
};
};
&dsi0_out {
remote-endpoint = <&panel_in>;
data-lanes = <0 1 2 3>;
};
&dsi0_phy {
status = "okay";
vdds-supply = <&vdda_mipi_dsi0_pll>;
};
&gcc {
protected-clocks = <GCC_QSPI_CORE_CLK>,
<GCC_QSPI_CORE_CLK_SRC>,
......@@ -452,6 +414,44 @@ &mdss {
status = "okay";
};
&mdss_dsi0 {
status = "okay";
vdda-supply = <&vdda_mipi_dsi0_1p2>;
/*
* Both devices use different panels but all other properties
* are common. Compatible line is declared in device dts.
*/
display_panel: panel@0 {
status = "disabled";
reg = <0>;
vddio-supply = <&vreg_l14a_1p88>;
reset-gpios = <&tlmm 6 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&panel_reset_pins &panel_te_pin &panel_esd_pin>;
port {
panel_in: endpoint {
remote-endpoint = <&mdss_dsi0_out>;
};
};
};
};
&mdss_dsi0_out {
remote-endpoint = <&panel_in>;
data-lanes = <0 1 2 3>;
};
&mdss_dsi0_phy {
status = "okay";
vdds-supply = <&vdda_mipi_dsi0_pll>;
};
/* Modem/wifi */
&mss_pil {
status = "okay";
......
arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts
View file @ 8fe25ba3
......@@ -411,44 +411,6 @@ &cdsp_pas {
firmware-name = "qcom/sdm845/axolotl/cdsp.mbn";
};
&dsi0 {
status = "okay";
vdda-supply = <&vdda_mipi_dsi0_1p2>;
panel@0 {
compatible = "visionox,rm69299-shift";
status = "okay";
reg = <0>;
vdda-supply = <&vreg_l14a_1p88>;
vdd3p3-supply = <&vreg_l28a_3p0>;
#address-cells = <1>;
#size-cells = <0>;
reset-gpios = <&tlmm 6 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&sde_dsi_active &sde_te_active>;
pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>;
port {
panel_in_0: endpoint {
remote-endpoint = <&dsi0_out>;
};
};
};
};
&dsi0_out {
remote-endpoint = <&panel_in_0>;
data-lanes = <0 1 2 3>;
};
&dsi0_phy {
status = "okay";
vdds-supply = <&vdda_mipi_dsi0_pll>;
};
&gcc {
protected-clocks = <GCC_QSPI_CORE_CLK>,
<GCC_QSPI_CORE_CLK_SRC>,
......@@ -509,6 +471,44 @@ &mdss {
status = "okay";
};
&mdss_dsi0 {
status = "okay";
vdda-supply = <&vdda_mipi_dsi0_1p2>;
panel@0 {
compatible = "visionox,rm69299-shift";
status = "okay";
reg = <0>;
vdda-supply = <&vreg_l14a_1p88>;
vdd3p3-supply = <&vreg_l28a_3p0>;
#address-cells = <1>;
#size-cells = <0>;
reset-gpios = <&tlmm 6 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&sde_dsi_active &sde_te_active>;
pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>;
port {
panel_in_0: endpoint {
remote-endpoint = <&mdss_dsi0_out>;
};
};
};
};
&mdss_dsi0_out {
remote-endpoint = <&panel_in_0>;
data-lanes = <0 1 2 3>;
};
&mdss_dsi0_phy {
status = "okay";
vdds-supply = <&vdda_mipi_dsi0_pll>;
};
&mss_pil {
status = "okay";
firmware-name = "qcom/sdm845/axolotl/mba.mbn", "qcom/sdm845/axolotl/modem.mbn";
......
arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama.dtsi
View file @ 8fe25ba3
......@@ -368,43 +368,6 @@ &cdsp_pas {
status = "okay";
};
&dsi0 {
vdda-supply = <&vreg_l26a_1p2>;
status = "okay";
panel: panel@0 {
/* The compatible is assigned in device DTs. */
reg = <0>;
backlight = <&pmi8998_wled>;
vddio-supply = <&vreg_l14a_1p8>;
vsp-supply = <&lab>;
vsn-supply = <&ibb>;
panel-reset-gpios = <&tlmm 6 GPIO_ACTIVE_HIGH>;
touch-reset-gpios = <&tlmm 99 GPIO_ACTIVE_HIGH>;
pinctrl-0 = <&sde_dsi_active &sde_te_active_sleep>;
pinctrl-1 = <&sde_dsi_sleep &sde_te_active_sleep>;
pinctrl-names = "default", "sleep";
port {
panel_in: endpoint {
remote-endpoint = <&dsi0_out>;
};
};
};
};
&dsi0_out {
remote-endpoint = <&panel_in>;
data-lanes = <0 1 2 3>;
};
&dsi0_phy {
vdds-supply = <&vreg_l1a_0p9>;
status = "okay";
};
&gcc {
protected-clocks = <GCC_QSPI_CORE_CLK>,
<GCC_QSPI_CORE_CLK_SRC>,
......@@ -515,6 +478,43 @@ &mdss {
status = "okay";
};
&mdss_dsi0 {
vdda-supply = <&vreg_l26a_1p2>;
status = "okay";
panel: panel@0 {
/* The compatible is assigned in device DTs. */
reg = <0>;
backlight = <&pmi8998_wled>;
vddio-supply = <&vreg_l14a_1p8>;
vsp-supply = <&lab>;
vsn-supply = <&ibb>;
panel-reset-gpios = <&tlmm 6 GPIO_ACTIVE_HIGH>;
touch-reset-gpios = <&tlmm 99 GPIO_ACTIVE_HIGH>;
pinctrl-0 = <&sde_dsi_active &sde_te_active_sleep>;
pinctrl-1 = <&sde_dsi_sleep &sde_te_active_sleep>;
pinctrl-names = "default", "sleep";
port {
panel_in: endpoint {
remote-endpoint = <&mdss_dsi0_out>;
};
};
};
};
&mdss_dsi0_out {
remote-endpoint = <&panel_in>;
data-lanes = <0 1 2 3>;
};
&mdss_dsi0_phy {
vdds-supply = <&vreg_l1a_0p9>;
status = "okay";
};
&pm8998_gpios {
focus_n: focus-n-state {
pins = "gpio2";
......
arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi
View file @ 8fe25ba3
......@@ -231,39 +231,6 @@ &cdsp_pas {
firmware-name = "qcom/sdm845/beryllium/cdsp.mbn";
};
&dsi0 {
status = "okay";
vdda-supply = <&vreg_l26a_1p2>;
display_panel: panel@0 {
reg = <0>;
vddio-supply = <&vreg_l14a_1p8>;
vddpos-supply = <&lab>;
vddneg-supply = <&ibb>;
backlight = <&pmi8998_wled>;
reset-gpios = <&tlmm 6 GPIO_ACTIVE_LOW>;
status = "disabled";
port {
panel_in_0: endpoint {
remote-endpoint = <&dsi0_out>;
};
};
};
};
&dsi0_out {
remote-endpoint = <&panel_in_0>;
data-lanes = <0 1 2 3>;
};
&dsi0_phy {
status = "okay";
vdds-supply = <&vreg_l1a_0p875>;
};
&gcc {
protected-clocks = <GCC_QSPI_CORE_CLK>,
<GCC_QSPI_CORE_CLK_SRC>,
......@@ -306,6 +273,39 @@ &mdss {
status = "okay";
};
&mdss_dsi0 {
status = "okay";
vdda-supply = <&vreg_l26a_1p2>;
display_panel: panel@0 {
reg = <0>;
vddio-supply = <&vreg_l14a_1p8>;
vddpos-supply = <&lab>;
vddneg-supply = <&ibb>;
backlight = <&pmi8998_wled>;
reset-gpios = <&tlmm 6 GPIO_ACTIVE_LOW>;
status = "disabled";
port {
panel_in_0: endpoint {
remote-endpoint = <&mdss_dsi0_out>;
};
};
};
};
&mdss_dsi0_out {
remote-endpoint = <&panel_in_0>;
data-lanes = <0 1 2 3>;
};
&mdss_dsi0_phy {
status = "okay";
vdds-supply = <&vreg_l1a_0p875>;
};
&mss_pil {
status = "okay";
firmware-name = "qcom/sdm845/beryllium/mba.mbn", "qcom/sdm845/beryllium/modem.mbn";
......
arch/arm64/boot/dts/qcom/sdm845-xiaomi-polaris.dts
View file @ 8fe25ba3
......@@ -373,44 +373,6 @@ &cdsp_pas {
status = "okay";
};
&dsi0 {
vdda-supply = <&vdda_mipi_dsi0_1p2>;
status = "okay";
display_panel: panel@0 {
compatible = "jdi,fhd-nt35596s";
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
reset-gpios = <&tlmm 6 GPIO_ACTIVE_LOW>;
vddio-supply = <&vreg_l14a_1p8>;
backlight = <&pmi8998_wled>;
vddpos-supply = <&lab>;
vddneg-supply = <&ibb>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&sde_dsi_active>;
pinctrl-1 = <&sde_dsi_suspend>;
port {
panel_in: endpoint {
remote-endpoint = <&dsi0_out>;
};
};
};
};
&dsi0_out {
remote-endpoint = <&panel_in>;
data-lanes = <0 1 2 3>;
};
&dsi0_phy {
vdds-supply = <&vdda_mipi_dsi0_pll>;
status = "okay";
};
&gcc {
protected-clocks = <GCC_QSPI_CORE_CLK>,
<GCC_QSPI_CORE_CLK_SRC>,
......@@ -505,6 +467,44 @@ &mdss {
status = "okay";
};
&mdss_dsi0 {
vdda-supply = <&vdda_mipi_dsi0_1p2>;
status = "okay";
display_panel: panel@0 {
compatible = "jdi,fhd-nt35596s";
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
reset-gpios = <&tlmm 6 GPIO_ACTIVE_LOW>;
vddio-supply = <&vreg_l14a_1p8>;
backlight = <&pmi8998_wled>;
vddpos-supply = <&lab>;
vddneg-supply = <&ibb>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&sde_dsi_active>;
pinctrl-1 = <&sde_dsi_suspend>;
port {
panel_in: endpoint {
remote-endpoint = <&mdss_dsi0_out>;
};
};
};
};
&mdss_dsi0_out {
remote-endpoint = <&panel_in>;
data-lanes = <0 1 2 3>;
};
&mdss_dsi0_phy {
vdds-supply = <&vdda_mipi_dsi0_pll>;
status = "okay";
};
&mss_pil {
firmware-name = "qcom/sdm845/polaris/mba.mbn", "qcom/sdm845/polaris/modem.mbn";
status = "okay";
......
arch/arm64/boot/dts/qcom/sdm845.dtsi
View file @ 8fe25ba3
......@@ -4501,14 +4501,14 @@ dpu_intf0_out: endpoint {
port@1 {
reg = <1>;
dpu_intf1_out: endpoint {
remote-endpoint = <&dsi0_in>;
remote-endpoint = <&mdss_dsi0_in>;
};
};
port@2 {
reg = <2>;
dpu_intf2_out: endpoint {
remote-endpoint = <&dsi1_in>;
remote-endpoint = <&mdss_dsi1_in>;
};
};
};
......@@ -4608,7 +4608,7 @@ opp-810000000 {
};
};
dsi0: dsi@ae94000 {
mdss_dsi0: dsi@ae94000 {
compatible = "qcom,sdm845-dsi-ctrl",
"qcom,mdss-dsi-ctrl";
reg = <0 0x0ae94000 0 0x400>;
......@@ -4630,12 +4630,12 @@ dsi0: dsi@ae94000 {
"iface",
"bus";
assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>;
assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
operating-points-v2 = <&dsi_opp_table>;
power-domains = <&rpmhpd SDM845_CX>;
phys = <&dsi0_phy>;
phys = <&mdss_dsi0_phy>;
status = "disabled";
......@@ -4648,20 +4648,20 @@ ports {
port@0 {
reg = <0>;
dsi0_in: endpoint {
mdss_dsi0_in: endpoint {
remote-endpoint = <&dpu_intf1_out>;
};
};
port@1 {
reg = <1>;
dsi0_out: endpoint {
mdss_dsi0_out: endpoint {
};
};
};
};
dsi0_phy: phy@ae94400 {
mdss_dsi0_phy: phy@ae94400 {
compatible = "qcom,dsi-phy-10nm";
reg = <0 0x0ae94400 0 0x200>,
<0 0x0ae94600 0 0x280>,
......@@ -4680,7 +4680,7 @@ dsi0_phy: phy@ae94400 {
status = "disabled";
};
dsi1: dsi@ae96000 {
mdss_dsi1: dsi@ae96000 {
compatible = "qcom,sdm845-dsi-ctrl",
"qcom,mdss-dsi-ctrl";
reg = <0 0x0ae96000 0 0x400>;
......@@ -4702,12 +4702,12 @@ dsi1: dsi@ae96000 {
"iface",
"bus";
assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>;
assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>;
assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>;
operating-points-v2 = <&dsi_opp_table>;
power-domains = <&rpmhpd SDM845_CX>;
phys = <&dsi1_phy>;
phys = <&mdss_dsi1_phy>;
status = "disabled";
......@@ -4720,20 +4720,20 @@ ports {
port@0 {
reg = <0>;
dsi1_in: endpoint {
mdss_dsi1_in: endpoint {
remote-endpoint = <&dpu_intf2_out>;
};
};
port@1 {
reg = <1>;
dsi1_out: endpoint {
mdss_dsi1_out: endpoint {
};
};
};
};
dsi1_phy: phy@ae96400 {
mdss_dsi1_phy: phy@ae96400 {
compatible = "qcom,dsi-phy-10nm";
reg = <0 0x0ae96400 0 0x200>,
<0 0x0ae96600 0 0x280>,
......@@ -4895,10 +4895,10 @@ dispcc: clock-controller@af00000 {
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&gcc GCC_DISP_GPLL0_CLK_SRC>,
<&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>,
<&dsi0_phy 0>,
<&dsi0_phy 1>,
<&dsi1_phy 0>,
<&dsi1_phy 1>,
<&mdss_dsi0_phy 0>,
<&mdss_dsi0_phy 1>,
<&mdss_dsi1_phy 0>,
<&mdss_dsi1_phy 1>,
<&dp_phy 0>,
<&dp_phy 1>;
clock-names = "bi_tcxo",
......
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