lab.nexedi.com will be down from Thursday, 20 March 2025, 07:30:00 UTC for a duration of approximately 2 hours

Commit 8fe9346b authored by Soren Brinkmann's avatar Soren Brinkmann Committed by Michal Simek

ARM: zynq: DT: Migrate UART to Cadence binding

The Zynq UART is Cadence IP and the driver has been renamed accordingly.
Migrate the DT to use the new binding for the UART driver.
Signed-off-by: default avatarSoren Brinkmann <soren.brinkmann@xilinx.com>
Acked-by: default avatarPeter Crosthwaite <peter.crosthwaite@xilinx.com>
Acked-by: default avatarRob Herring <robh@kernel.org>
Tested-by: default avatarMichal Simek <michal.simek@xilinx.com>
Signed-off-by: default avatarMichal Simek <michal.simek@xilinx.com>
parent db34d2b3
......@@ -105,19 +105,19 @@ L2: cache-controller {
};
uart0: serial@e0000000 {
compatible = "xlnx,xuartps";
compatible = "xlnx,xuartps", "cdns,uart-r1p8";
status = "disabled";
clocks = <&clkc 23>, <&clkc 40>;
clock-names = "ref_clk", "aper_clk";
clock-names = "uart_clk", "pclk";
reg = <0xE0000000 0x1000>;
interrupts = <0 27 4>;
};
uart1: serial@e0001000 {
compatible = "xlnx,xuartps";
compatible = "xlnx,xuartps", "cdns,uart-r1p8";
status = "disabled";
clocks = <&clkc 24>, <&clkc 41>;
clock-names = "ref_clk", "aper_clk";
clock-names = "uart_clk", "pclk";
reg = <0xE0001000 0x1000>;
interrupts = <0 50 4>;
};
......
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment