Commit 8ff99ad0 authored by Linus Torvalds's avatar Linus Torvalds

Merge tag 'phy-for-6.3' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy

Pull phy updates from Vinod Koul:
 "This features a bunch of new device support, a couple of new drivers,
  yaml conversion and updates of a few drivers.

  Core support:

   - New devm_of_phy_optional_get() API with users and conversion

  New hardware support:

   - Mediatek MT7986 phy support

   - Qualcomm SM8550 UFS, PCIe, combo phy support, SM6115 / SM4250 USB3
     phy support, SM6350 combo phy support, SM6125 UFS PHY support amd
     SM8350 & SM8450 combo phy support

   - Qualcomm SNPS eUSB2 eUSB2 repeater drivers

   - Allwinner F1C100s USB PHY support

   - Tegra xusb support for Tegra234

  Updates:

   - Yaml conversion for Qualcomm pcie2 phy and usb-hsic-phy

   - G4 mode support in Qualcomm UFS phy and support for various SoCs

   - Yaml conversion for Meson usb2 phy

   - TI Type C support for usb phy for j721

   - Yaml conversion for Tegra xusb binding"

* tag 'phy-for-6.3' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy: (106 commits)
  phy: qcom: phy-qcom-snps-eusb2: Add support for eUSB2 repeater
  phy: qcom: Add QCOM SNPS eUSB2 repeater driver
  dt-bindings: phy: qcom,snps-eusb2-phy: Add phys property for the repeater
  dt-bindings: phy: Add qcom,snps-eusb2-repeater schema file
  dt-bindings: phy: amlogic,g12a-usb3-pcie-phy: add missing optional phy-supply property
  phy: rockchip-typec: Fix unsigned comparison with less than zero
  phy: rockchip-typec: fix tcphy_get_mode error case
  phy: qcom: snps-eusb2: Add missing headers
  phy: qcom-qmp-combo: Add support for SM8550
  phy: qcom-qmp: Add v6 DP register offsets
  phy: qcom-qmp: pcs-usb: Add v6 register offsets
  dt-bindings: phy: qcom,sc8280xp-qmp-usb43dp: Document SM8550 compatible
  phy: qcom: Add QCOM SNPS eUSB2 driver
  dt-bindings: phy: Add qcom,snps-eusb2-phy schema file
  phy: qcom-qmp-pcie: Add support for SM8550 g3x2 and g4x2 PCIEs
  phy: qcom-qmp: qserdes-lane-shared: Add v6 register offsets
  phy: qcom-qmp: qserdes-txrx: Add v6.20 register offsets
  phy: qcom-qmp: pcs-pcie: Add v6.20 register offsets
  phy: qcom-qmp: pcs-pcie: Add v6 register offsets
  phy: qcom-qmp: pcs: Add v6.20 register offsets
  ...
parents 9e6bfd42 3584f639
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/allwinner,suniv-f1c100s-usb-phy.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Allwinner F1C100s USB PHY
maintainers:
- Chen-Yu Tsai <wens@csie.org>
- Maxime Ripard <mripard@kernel.org>
properties:
"#phy-cells":
const: 1
compatible:
const: allwinner,suniv-f1c100s-usb-phy
reg:
maxItems: 1
description: PHY Control registers
reg-names:
const: phy_ctrl
clocks:
maxItems: 1
description: USB OTG PHY bus clock
clock-names:
const: usb0_phy
resets:
maxItems: 1
description: USB OTG reset
reset-names:
const: usb0_reset
usb0_id_det-gpios:
maxItems: 1
description: GPIO to the USB OTG ID pin
usb0_vbus_det-gpios:
maxItems: 1
description: GPIO to the USB OTG VBUS detect pin
usb0_vbus_power-supply:
description: Power supply to detect the USB OTG VBUS
usb0_vbus-supply:
description: Regulator controlling USB OTG VBUS
required:
- "#phy-cells"
- compatible
- clocks
- clock-names
- reg
- reg-names
- resets
- reset-names
additionalProperties: false
examples:
- |
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/clock/suniv-ccu-f1c100s.h>
#include <dt-bindings/reset/suniv-ccu-f1c100s.h>
phy@1c13400 {
compatible = "allwinner,suniv-f1c100s-usb-phy";
reg = <0x01c13400 0x10>;
reg-names = "phy_ctrl";
clocks = <&ccu CLK_USB_PHY0>;
clock-names = "usb0_phy";
resets = <&ccu RST_USB_PHY0>;
reset-names = "usb0_reset";
#phy-cells = <1>;
usb0_id_det-gpios = <&pio 4 2 GPIO_ACTIVE_HIGH>;
};
...@@ -35,6 +35,11 @@ properties: ...@@ -35,6 +35,11 @@ properties:
"#phy-cells": "#phy-cells":
const: 1 const: 1
phy-supply:
description:
Phandle to a regulator that provides power to the PHY. This
regulator will be managed during the PHY power on/off sequence.
required: required:
- compatible - compatible
- reg - reg
......
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/amlogic,meson-gxl-usb2-phy.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Amlogic Meson GXL USB2 PHY
maintainers:
- Neil Armstrong <neil.armstrong@linaro.org>
properties:
compatible:
const: amlogic,meson-gxl-usb2-phy
reg:
maxItems: 1
clocks:
maxItems: 1
clock-names:
items:
- const: phy
resets:
maxItems: 1
reset-names:
items:
- const: phy
"#phy-cells":
const: 0
phy-supply: true
required:
- compatible
- reg
- "#phy-cells"
additionalProperties: false
examples:
- |
phy@78000 {
compatible = "amlogic,meson-gxl-usb2-phy";
reg = <0x78000 0x20>;
clocks = <&xtal>;
clock-names = "phy";
resets = <&phy_reset>;
reset-names = "phy";
#phy-cells = <0>;
phy-supply = <&usb2_supply>;
};
...@@ -79,6 +79,7 @@ properties: ...@@ -79,6 +79,7 @@ properties:
- enum: - enum:
- mediatek,mt2712-tphy - mediatek,mt2712-tphy
- mediatek,mt7629-tphy - mediatek,mt7629-tphy
- mediatek,mt7986-tphy
- mediatek,mt8183-tphy - mediatek,mt8183-tphy
- mediatek,mt8186-tphy - mediatek,mt8186-tphy
- mediatek,mt8192-tphy - mediatek,mt8192-tphy
......
* Amlogic Meson GXL and GXM USB2 PHY binding
Required properties:
- compatible: Should be "amlogic,meson-gxl-usb2-phy"
- reg: The base address and length of the registers
- #phys-cells: must be 0 (see phy-bindings.txt in this directory)
Optional properties:
- clocks: a phandle to the clock of this PHY
- clock-names: must be "phy"
- resets: a phandle to the reset line of this PHY
- reset-names: must be "phy"
- phy-supply: see phy-bindings.txt in this directory
Example:
usb2_phy0: phy@78000 {
compatible = "amlogic,meson-gxl-usb2-phy";
#phy-cells = <0>;
reg = <0x0 0x78000 0x0 0x20>;
};
...@@ -75,6 +75,9 @@ patternProperties: ...@@ -75,6 +75,9 @@ patternProperties:
minItems: 3 minItems: 3
maxItems: 6 maxItems: 6
"#clock-cells":
const: 1
"#phy-cells": "#phy-cells":
const: 0 const: 0
......
...@@ -30,6 +30,7 @@ properties: ...@@ -30,6 +30,7 @@ properties:
- qcom,sdm845-qmp-usb3-uni-phy - qcom,sdm845-qmp-usb3-uni-phy
- qcom,sdx55-qmp-usb3-uni-phy - qcom,sdx55-qmp-usb3-uni-phy
- qcom,sdx65-qmp-usb3-uni-phy - qcom,sdx65-qmp-usb3-uni-phy
- qcom,sm6115-qmp-usb3-phy
- qcom,sm8150-qmp-usb3-phy - qcom,sm8150-qmp-usb3-phy
- qcom,sm8150-qmp-usb3-uni-phy - qcom,sm8150-qmp-usb3-uni-phy
- qcom,sm8250-qmp-usb3-phy - qcom,sm8250-qmp-usb3-phy
...@@ -253,6 +254,7 @@ allOf: ...@@ -253,6 +254,7 @@ allOf:
contains: contains:
enum: enum:
- qcom,qcm2290-qmp-usb3-phy - qcom,qcm2290-qmp-usb3-phy
- qcom,sm6115-qmp-usb3-phy
then: then:
properties: properties:
clocks: clocks:
...@@ -321,6 +323,7 @@ allOf: ...@@ -321,6 +323,7 @@ allOf:
- qcom,sc8180x-qmp-usb3-phy - qcom,sc8180x-qmp-usb3-phy
- qcom,sdx55-qmp-usb3-uni-phy - qcom,sdx55-qmp-usb3-uni-phy
- qcom,sdx65-qmp-usb3-uni-phy - qcom,sdx65-qmp-usb3-uni-phy
- qcom,sm6115-qmp-usb3-phy
- qcom,sm8150-qmp-usb3-uni-phy - qcom,sm8150-qmp-usb3-uni-phy
- qcom,sm8250-qmp-usb3-phy - qcom,sm8250-qmp-usb3-phy
then: then:
......
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/qcom,pcie2-phy.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm PCIe2 PHY controller
maintainers:
- Vinod Koul <vkoul@kernel.org>
description:
The Qualcomm PCIe2 PHY is a Synopsys based phy found in a number of Qualcomm
platforms.
properties:
compatible:
items:
- const: qcom,qcs404-pcie2-phy
- const: qcom,pcie2-phy
reg:
items:
- description: PHY register set
clocks:
items:
- description: a clock-specifier pair for the "pipe" clock
clock-output-names:
maxItems: 1
"#clock-cells":
const: 0
"#phy-cells":
const: 0
vdda-vp-supply:
description: low voltage regulator
vdda-vph-supply:
description: high voltage regulator
resets:
maxItems: 2
reset-names:
items:
- const: phy
- const: pipe
required:
- compatible
- reg
- clocks
- clock-output-names
- "#clock-cells"
- "#phy-cells"
- vdda-vp-supply
- vdda-vph-supply
- resets
- reset-names
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,gcc-qcs404.h>
phy@7786000 {
compatible = "qcom,qcs404-pcie2-phy", "qcom,pcie2-phy";
reg = <0x07786000 0xb8>;
clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
resets = <&gcc GCC_PCIEPHY_0_PHY_BCR>,
<&gcc GCC_PCIE_0_PIPE_ARES>;
reset-names = "phy", "pipe";
vdda-vp-supply = <&vreg_l3_1p05>;
vdda-vph-supply = <&vreg_l5_1p8>;
clock-output-names = "pcie_0_pipe_clk";
#clock-cells = <0>;
#phy-cells = <0>;
};
...
...@@ -82,81 +82,74 @@ properties: ...@@ -82,81 +82,74 @@ properties:
Phandle to TCSR syscon register region. Phandle to TCSR syscon register region.
$ref: /schemas/types.yaml#/definitions/phandle $ref: /schemas/types.yaml#/definitions/phandle
if: qcom,imp-res-offset-value:
properties: description:
compatible: It is a 6 bit value that specifies offset to be
contains: added to PHY refgen RESCODE via IMP_CTRL1 register. It is a PHY
const: qcom,qusb2-v2-phy tuning parameter that may vary for different boards of same SOC.
then: $ref: /schemas/types.yaml#/definitions/uint32
properties: minimum: 0
qcom,imp-res-offset-value: maximum: 63
description: default: 0
It is a 6 bit value that specifies offset to be
added to PHY refgen RESCODE via IMP_CTRL1 register. It is a PHY qcom,bias-ctrl-value:
tuning parameter that may vary for different boards of same SOC. description:
$ref: /schemas/types.yaml#/definitions/uint32 It is a 6 bit value that specifies bias-ctrl-value. It is a PHY
minimum: 0 tuning parameter that may vary for different boards of same SOC.
maximum: 63 $ref: /schemas/types.yaml#/definitions/uint32
default: 0 minimum: 0
maximum: 63
qcom,bias-ctrl-value: default: 32
description:
It is a 6 bit value that specifies bias-ctrl-value. It is a PHY qcom,charge-ctrl-value:
tuning parameter that may vary for different boards of same SOC. description:
$ref: /schemas/types.yaml#/definitions/uint32 It is a 2 bit value that specifies charge-ctrl-value. It is a PHY
minimum: 0 tuning parameter that may vary for different boards of same SOC.
maximum: 63 $ref: /schemas/types.yaml#/definitions/uint32
default: 32 minimum: 0
maximum: 3
qcom,charge-ctrl-value: default: 0
description:
It is a 2 bit value that specifies charge-ctrl-value. It is a PHY qcom,hstx-trim-value:
tuning parameter that may vary for different boards of same SOC. description:
$ref: /schemas/types.yaml#/definitions/uint32 It is a 4 bit value that specifies tuning for HSTX
minimum: 0 output current.
maximum: 3 Possible range is - 15mA to 24mA (stepsize of 600 uA).
default: 0 See dt-bindings/phy/phy-qcom-qusb2.h for applicable values.
$ref: /schemas/types.yaml#/definitions/uint32
qcom,hstx-trim-value: minimum: 0
description: maximum: 15
It is a 4 bit value that specifies tuning for HSTX default: 3
output current.
Possible range is - 15mA to 24mA (stepsize of 600 uA). qcom,preemphasis-level:
See dt-bindings/phy/phy-qcom-qusb2.h for applicable values. description:
$ref: /schemas/types.yaml#/definitions/uint32 It is a 2 bit value that specifies pre-emphasis level.
minimum: 0 Possible range is 0 to 15% (stepsize of 5%).
maximum: 15 See dt-bindings/phy/phy-qcom-qusb2.h for applicable values.
default: 3 $ref: /schemas/types.yaml#/definitions/uint32
minimum: 0
qcom,preemphasis-level: maximum: 3
description: default: 2
It is a 2 bit value that specifies pre-emphasis level.
Possible range is 0 to 15% (stepsize of 5%). qcom,preemphasis-width:
See dt-bindings/phy/phy-qcom-qusb2.h for applicable values. description:
$ref: /schemas/types.yaml#/definitions/uint32 It is a 1 bit value that specifies how long the HSTX
minimum: 0 pre-emphasis (specified using qcom,preemphasis-level) must be in
maximum: 3 effect. Duration could be half-bit of full-bit.
default: 2 See dt-bindings/phy/phy-qcom-qusb2.h for applicable values.
$ref: /schemas/types.yaml#/definitions/uint32
qcom,preemphasis-width: minimum: 0
description: maximum: 1
It is a 1 bit value that specifies how long the HSTX default: 0
pre-emphasis (specified using qcom,preemphasis-level) must be in
effect. Duration could be half-bit of full-bit. qcom,hsdisc-trim-value:
See dt-bindings/phy/phy-qcom-qusb2.h for applicable values. description:
$ref: /schemas/types.yaml#/definitions/uint32 It is a 2 bit value tuning parameter that control disconnect
minimum: 0 threshold and may vary for different boards of same SOC.
maximum: 1 $ref: /schemas/types.yaml#/definitions/uint32
default: 0 minimum: 0
maximum: 3
qcom,hsdisc-trim-value: default: 0
description:
It is a 2 bit value tuning parameter that control disconnect
threshold and may vary for different boards of same SOC.
$ref: /schemas/types.yaml#/definitions/uint32
minimum: 0
maximum: 3
default: 0
required: required:
- compatible - compatible
...@@ -169,6 +162,23 @@ required: ...@@ -169,6 +162,23 @@ required:
- vdda-phy-dpdm-supply - vdda-phy-dpdm-supply
- resets - resets
allOf:
- if:
not:
properties:
compatible:
contains:
const: qcom,qusb2-v2-phy
then:
properties:
qcom,imp-res-offset-value: false
qcom,bias-ctrl-value: false
qcom,charge-ctrl-value: false
qcom,hstx-trim-value: false
qcom,preemphasis-level: false
qcom,preemphasis-width: false
qcom,hsdisc-trim-value: false
additionalProperties: false additionalProperties: false
examples: examples:
......
...@@ -19,12 +19,17 @@ maintainers: ...@@ -19,12 +19,17 @@ maintainers:
properties: properties:
compatible: compatible:
enum: oneOf:
- qcom,sc7180-qmp-usb3-dp-phy - enum:
- qcom,sc7280-qmp-usb3-dp-phy - qcom,sc7180-qmp-usb3-dp-phy
- qcom,sc8180x-qmp-usb3-dp-phy - qcom,sc8180x-qmp-usb3-dp-phy
- qcom,sdm845-qmp-usb3-dp-phy - qcom,sdm845-qmp-usb3-dp-phy
- qcom,sm8250-qmp-usb3-dp-phy - qcom,sm8250-qmp-usb3-dp-phy
- items:
- enum:
- qcom,sc7280-qmp-usb3-dp-phy
- const: qcom,sm8250-qmp-usb3-dp-phy
reg: reg:
items: items:
- description: Address and length of PHY's USB serdes block. - description: Address and length of PHY's USB serdes block.
...@@ -46,18 +51,12 @@ properties: ...@@ -46,18 +51,12 @@ properties:
ranges: true ranges: true
clocks: clocks:
items: minItems: 3
- description: Phy aux clock. maxItems: 4
- description: Phy config clock.
- description: 19.2 MHz ref clk.
- description: Phy common block aux clock.
clock-names: clock-names:
items: minItems: 3
- const: aux maxItems: 4
- const: cfg_ahb
- const: ref
- const: com_aux
power-domains: power-domains:
maxItems: 1 maxItems: 1
...@@ -166,6 +165,64 @@ required: ...@@ -166,6 +165,64 @@ required:
- vdda-phy-supply - vdda-phy-supply
- vdda-pll-supply - vdda-pll-supply
allOf:
- if:
properties:
compatible:
enum:
- qcom,sc7180-qmp-usb3-dp-phy
- qcom,sdm845-qmp-usb3-dp-phy
then:
properties:
clocks:
items:
- description: Phy aux clock
- description: Phy config clock
- description: 19.2 MHz ref clk
- description: Phy common block aux clock
clock-names:
items:
- const: aux
- const: cfg_ahb
- const: ref
- const: com_aux
- if:
properties:
compatible:
enum:
- qcom,sc8180x-qmp-usb3-dp-phy
then:
properties:
clocks:
items:
- description: Phy aux clock
- description: 19.2 MHz ref clk
- description: Phy common block aux clock
clock-names:
items:
- const: aux
- const: ref
- const: com_aux
- if:
properties:
compatible:
enum:
- qcom,sm8250-qmp-usb3-dp-phy
then:
properties:
clocks:
items:
- description: Phy aux clock
- description: Board XO source
- description: Phy common block aux clock
clock-names:
items:
- const: aux
- const: ref_clk_src
- const: com_aux
additionalProperties: false additionalProperties: false
examples: examples:
......
...@@ -19,15 +19,20 @@ properties: ...@@ -19,15 +19,20 @@ properties:
- qcom,sc8280xp-qmp-gen3x1-pcie-phy - qcom,sc8280xp-qmp-gen3x1-pcie-phy
- qcom,sc8280xp-qmp-gen3x2-pcie-phy - qcom,sc8280xp-qmp-gen3x2-pcie-phy
- qcom,sc8280xp-qmp-gen3x4-pcie-phy - qcom,sc8280xp-qmp-gen3x4-pcie-phy
- qcom,sm8350-qmp-gen3x1-pcie-phy
- qcom,sm8550-qmp-gen3x2-pcie-phy
- qcom,sm8550-qmp-gen4x2-pcie-phy
reg: reg:
minItems: 1 minItems: 1
maxItems: 2 maxItems: 2
clocks: clocks:
minItems: 5
maxItems: 6 maxItems: 6
clock-names: clock-names:
minItems: 5
items: items:
- const: aux - const: aux
- const: cfg_ahb - const: cfg_ahb
...@@ -40,16 +45,21 @@ properties: ...@@ -40,16 +45,21 @@ properties:
maxItems: 1 maxItems: 1
resets: resets:
maxItems: 1 minItems: 1
maxItems: 2
reset-names: reset-names:
minItems: 1
items: items:
- const: phy - const: phy
- const: phy_nocsr
vdda-phy-supply: true vdda-phy-supply: true
vdda-pll-supply: true vdda-pll-supply: true
vdda-qref-supply: true
qcom,4ln-config-sel: qcom,4ln-config-sel:
description: PCIe 4-lane configuration description: PCIe 4-lane configuration
$ref: /schemas/types.yaml#/definitions/phandle-array $ref: /schemas/types.yaml#/definitions/phandle-array
...@@ -104,6 +114,46 @@ allOf: ...@@ -104,6 +114,46 @@ allOf:
reg: reg:
maxItems: 1 maxItems: 1
- if:
properties:
compatible:
contains:
enum:
- qcom,sm8350-qmp-gen3x1-pcie-phy
- qcom,sm8550-qmp-gen3x2-pcie-phy
- qcom,sm8550-qmp-gen4x2-pcie-phy
then:
properties:
clocks:
maxItems: 5
clock-names:
maxItems: 5
else:
properties:
clocks:
minItems: 6
clock-names:
minItems: 6
- if:
properties:
compatible:
contains:
enum:
- qcom,sm8550-qmp-gen4x2-pcie-phy
then:
properties:
resets:
minItems: 2
reset-names:
minItems: 2
else:
properties:
resets:
maxItems: 1
reset-names:
maxItems: 1
examples: examples:
- | - |
#include <dt-bindings/clock/qcom,gcc-sc8280xp.h> #include <dt-bindings/clock/qcom,gcc-sc8280xp.h>
......
...@@ -17,6 +17,8 @@ properties: ...@@ -17,6 +17,8 @@ properties:
compatible: compatible:
enum: enum:
- qcom,sc8280xp-qmp-ufs-phy - qcom,sc8280xp-qmp-ufs-phy
- qcom,sm6125-qmp-ufs-phy
- qcom,sm8550-qmp-ufs-phy
reg: reg:
maxItems: 1 maxItems: 1
...@@ -43,6 +45,9 @@ properties: ...@@ -43,6 +45,9 @@ properties:
vdda-pll-supply: true vdda-pll-supply: true
"#clock-cells":
const: 1
"#phy-cells": "#phy-cells":
const: 0 const: 0
......
...@@ -17,6 +17,10 @@ properties: ...@@ -17,6 +17,10 @@ properties:
compatible: compatible:
enum: enum:
- qcom,sc8280xp-qmp-usb43dp-phy - qcom,sc8280xp-qmp-usb43dp-phy
- qcom,sm6350-qmp-usb3-dp-phy
- qcom,sm8350-qmp-usb3-dp-phy
- qcom,sm8450-qmp-usb3-dp-phy
- qcom,sm8550-qmp-usb3-dp-phy
reg: reg:
maxItems: 1 maxItems: 1
......
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/qcom,snps-eusb2-phy.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm SNPS eUSB2 phy controller
maintainers:
- Abel Vesa <abel.vesa@linaro.org>
description:
eUSB2 controller supports LS/FS/HS usb connectivity on Qualcomm chipsets.
properties:
compatible:
const: qcom,sm8550-snps-eusb2-phy
reg:
maxItems: 1
"#phy-cells":
const: 0
clocks:
items:
- description: ref
clock-names:
items:
- const: ref
resets:
maxItems: 1
phys:
maxItems: 1
description:
Phandle to eUSB2 to USB 2.0 repeater
vdd-supply:
description:
Phandle to 0.88V regulator supply to PHY digital circuit.
vdda12-supply:
description:
Phandle to 1.2V regulator supply to PHY refclk pll block.
required:
- compatible
- reg
- "#phy-cells"
- clocks
- clock-names
- vdd-supply
- vdda12-supply
- resets
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,sm8550-gcc.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/clock/qcom,sm8550-tcsr.h>
usb_1_hsphy: phy@88e3000 {
compatible = "qcom,sm8550-snps-eusb2-phy";
reg = <0x88e3000 0x154>;
#phy-cells = <0>;
clocks = <&tcsrcc TCSR_USB2_CLKREF_EN>;
clock-names = "ref";
vdd-supply = <&vreg_l1e_0p88>;
vdda12-supply = <&vreg_l3e_1p2>;
resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
};
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/qcom,snps-eusb2-repeater.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Synopsis eUSB2 to USB 2.0 repeater
maintainers:
- Abel Vesa <abel.vesa@linaro.org>
description:
eUSB2 repeater converts between eUSB2 and USB 2.0 signaling levels and
allows a eUSB2 PHY to connect to legacy USB 2.0 products
properties:
compatible:
const: qcom,pm8550b-eusb2-repeater
reg:
maxItems: 1
"#phy-cells":
const: 0
vdd18-supply: true
vdd3-supply: true
required:
- compatible
- reg
- "#phy-cells"
additionalProperties: false
examples:
- |
#include <dt-bindings/spmi/spmi.h>
pmic@7 {
reg = <0x7 SPMI_USID>;
#address-cells = <1>;
#size-cells = <0>;
pm8550b_eusb2_repeater: phy@fd00 {
compatible = "qcom,pm8550b-eusb2-repeater";
reg = <0xfd00>;
#phy-cells = <0>;
};
};
...
Qualcomm's USB HSIC PHY
PROPERTIES
- compatible:
Usage: required
Value type: <string>
Definition: Should contain "qcom,usb-hsic-phy" and more specifically one of the
following:
"qcom,usb-hsic-phy-mdm9615"
"qcom,usb-hsic-phy-msm8974"
- #phy-cells:
Usage: required
Value type: <u32>
Definition: Should contain 0
- clocks:
Usage: required
Value type: <prop-encoded-array>
Definition: Should contain clock specifier for phy, calibration and
a calibration sleep clock
- clock-names:
Usage: required
Value type: <stringlist>
Definition: Should contain "phy, "cal" and "cal_sleep"
- pinctrl-names:
Usage: required
Value type: <stringlist>
Definition: Should contain "init" and "default" in that order
- pinctrl-0:
Usage: required
Value type: <prop-encoded-array>
Definition: List of pinctrl settings to apply to keep HSIC pins in a glitch
free state
- pinctrl-1:
Usage: required
Value type: <prop-encoded-array>
Definition: List of pinctrl settings to apply to mux out the HSIC pins
EXAMPLE
usb-controller {
ulpi {
phy {
compatible = "qcom,usb-hsic-phy-msm8974",
"qcom,usb-hsic-phy";
#phy-cells = <0>;
pinctrl-names = "init", "default";
pinctrl-0 = <&hsic_sleep>;
pinctrl-1 = <&hsic_default>;
clocks = <&gcc GCC_USB_HSIC_CLK>,
<&gcc GCC_USB_HSIC_IO_CAL_CLK>,
<&gcc GCC_USB_HSIC_IO_CAL_SLEEP_CLK>;
clock-names = "phy", "cal", "cal_sleep";
assigned-clocks = <&gcc GCC_USB_HSIC_IO_CAL_CLK>;
assigned-clock-rates = <960000>;
};
};
};
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/qcom,usb-hsic-phy.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm USB HSIC PHY Controller
maintainers:
- Bjorn Andersson <andersson@kernel.org>
- Vinod Koul <vkoul@kernel.org>
properties:
compatible:
items:
- enum:
- qcom,usb-hsic-phy-mdm9615
- qcom,usb-hsic-phy-msm8974
- const: qcom,usb-hsic-phy
clocks:
maxItems: 3
clock-names:
items:
- const: phy
- const: cal
- const: cal_sleep
"#phy-cells":
const: 0
pinctrl-0: true
pinctrl-1: true
pinctrl-names:
items:
- const: init
- const: default
required:
- compatible
- clocks
- clock-names
- "#phy-cells"
- pinctrl-0
- pinctrl-1
- pinctrl-names
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,gcc-msm8974.h>
phy {
compatible = "qcom,usb-hsic-phy-msm8974",
"qcom,usb-hsic-phy";
clocks = <&gcc GCC_USB_HSIC_CLK>,
<&gcc GCC_USB_HSIC_IO_CAL_CLK>,
<&gcc GCC_USB_HSIC_IO_CAL_SLEEP_CLK>;
clock-names = "phy", "cal", "cal_sleep";
#phy-cells = <0>;
pinctrl-names = "init", "default";
pinctrl-0 = <&hsic_sleep>;
pinctrl-1 = <&hsic_default>;
};
...@@ -14,18 +14,25 @@ description: | ...@@ -14,18 +14,25 @@ description: |
properties: properties:
compatible: compatible:
enum: oneOf:
- qcom,usb-snps-hs-5nm-phy - enum:
- qcom,usb-snps-hs-7nm-phy - qcom,sc8180x-usb-hs-phy
- qcom,sc7280-usb-hs-phy - qcom,usb-snps-femto-v2-phy
- qcom,sc8180x-usb-hs-phy - items:
- qcom,sc8280xp-usb-hs-phy - enum:
- qcom,sm6375-usb-hs-phy - qcom,sc8280xp-usb-hs-phy
- qcom,sm8150-usb-hs-phy - const: qcom,usb-snps-hs-5nm-phy
- qcom,sm8250-usb-hs-phy - items:
- qcom,sm8350-usb-hs-phy - enum:
- qcom,sm8450-usb-hs-phy - qcom,sc7280-usb-hs-phy
- qcom,usb-snps-femto-v2-phy - qcom,sdx55-usb-hs-phy
- qcom,sdx65-usb-hs-phy
- qcom,sm6375-usb-hs-phy
- qcom,sm8150-usb-hs-phy
- qcom,sm8250-usb-hs-phy
- qcom,sm8350-usb-hs-phy
- qcom,sm8450-usb-hs-phy
- const: qcom,usb-snps-hs-7nm-phy
reg: reg:
maxItems: 1 maxItems: 1
...@@ -160,7 +167,7 @@ examples: ...@@ -160,7 +167,7 @@ examples:
#include <dt-bindings/clock/qcom,rpmh.h> #include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/clock/qcom,gcc-sm8150.h> #include <dt-bindings/clock/qcom,gcc-sm8150.h>
phy@88e2000 { phy@88e2000 {
compatible = "qcom,sm8150-usb-hs-phy"; compatible = "qcom,sm8150-usb-hs-phy", "qcom,usb-snps-hs-7nm-phy";
reg = <0x088e2000 0x400>; reg = <0x088e2000 0x400>;
#phy-cells = <0>; #phy-cells = <0>;
......
Qualcomm PCIe2 PHY controller
=============================
The Qualcomm PCIe2 PHY is a Synopsys based phy found in a number of Qualcomm
platforms.
Required properties:
- compatible: compatible list, should be:
"qcom,qcs404-pcie2-phy", "qcom,pcie2-phy"
- reg: offset and length of the PHY register set.
- #phy-cells: must be 0.
- clocks: a clock-specifier pair for the "pipe" clock
- vdda-vp-supply: phandle to low voltage regulator
- vdda-vph-supply: phandle to high voltage regulator
- resets: reset-specifier pairs for the "phy" and "pipe" resets
- reset-names: list of resets, should contain:
"phy" and "pipe"
- clock-output-names: name of the outgoing clock signal from the PHY PLL
- #clock-cells: must be 0
Example:
phy@7786000 {
compatible = "qcom,qcs404-pcie2-phy", "qcom,pcie2-phy";
reg = <0x07786000 0xb8>;
clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
resets = <&gcc GCC_PCIEPHY_0_PHY_BCR>,
<&gcc GCC_PCIE_0_PIPE_ARES>;
reset-names = "phy", "pipe";
vdda-vp-supply = <&vreg_l3_1p05>;
vdda-vph-supply = <&vreg_l5_1p8>;
clock-output-names = "pcie_0_pipe_clk";
#clock-cells = <0>;
#phy-cells = <0>;
};
...@@ -15,6 +15,7 @@ properties: ...@@ -15,6 +15,7 @@ properties:
compatible: compatible:
enum: enum:
- nxp,tjr1443
- ti,tcan1042 - ti,tcan1042
- ti,tcan1043 - ti,tcan1043
......
...@@ -103,27 +103,31 @@ it. This framework provides the following APIs to get a reference to the PHY. ...@@ -103,27 +103,31 @@ it. This framework provides the following APIs to get a reference to the PHY.
:: ::
struct phy *phy_get(struct device *dev, const char *string); struct phy *phy_get(struct device *dev, const char *string);
struct phy *phy_optional_get(struct device *dev, const char *string);
struct phy *devm_phy_get(struct device *dev, const char *string); struct phy *devm_phy_get(struct device *dev, const char *string);
struct phy *devm_phy_optional_get(struct device *dev, struct phy *devm_phy_optional_get(struct device *dev,
const char *string); const char *string);
struct phy *devm_of_phy_get(struct device *dev, struct device_node *np,
const char *con_id);
struct phy *devm_of_phy_optional_get(struct device *dev,
struct device_node *np,
const char *con_id);
struct phy *devm_of_phy_get_by_index(struct device *dev, struct phy *devm_of_phy_get_by_index(struct device *dev,
struct device_node *np, struct device_node *np,
int index); int index);
phy_get, phy_optional_get, devm_phy_get and devm_phy_optional_get can phy_get, devm_phy_get and devm_phy_optional_get can be used to get the PHY.
be used to get the PHY. In the case of dt boot, the string arguments In the case of dt boot, the string arguments
should contain the phy name as given in the dt data and in the case of should contain the phy name as given in the dt data and in the case of
non-dt boot, it should contain the label of the PHY. The two non-dt boot, it should contain the label of the PHY. The two
devm_phy_get associates the device with the PHY using devres on devm_phy_get associates the device with the PHY using devres on
successful PHY get. On driver detach, release function is invoked on successful PHY get. On driver detach, release function is invoked on
the devres data and devres data is freed. phy_optional_get and the devres data and devres data is freed.
devm_phy_optional_get should be used when the phy is optional. These The _optional_get variants should be used when the phy is optional. These
two functions will never return -ENODEV, but instead returns NULL when functions will never return -ENODEV, but instead return NULL when
the phy cannot be found.Some generic drivers, such as ehci, may use multiple the phy cannot be found.
phys and for such drivers referencing phy(s) by name(s) does not make sense. In Some generic drivers, such as ehci, may use multiple phys. In this case,
this case, devm_of_phy_get_by_index can be used to get a phy reference based on devm_of_phy_get or devm_of_phy_get_by_index can be used to get a phy
the index. reference based on name or index.
It should be noted that NULL is a valid phy reference. All phy It should be noted that NULL is a valid phy reference. All phy
consumer calls on the NULL phy become NOPs. That is the release calls, consumer calls on the NULL phy become NOPs. That is the release calls,
......
...@@ -1155,13 +1155,12 @@ int memac_initialization(struct mac_device *mac_dev, ...@@ -1155,13 +1155,12 @@ int memac_initialization(struct mac_device *mac_dev,
else else
memac->sgmii_pcs = pcs; memac->sgmii_pcs = pcs;
memac->serdes = devm_of_phy_get(mac_dev->dev, mac_node, "serdes"); memac->serdes = devm_of_phy_optional_get(mac_dev->dev, mac_node,
err = PTR_ERR(memac->serdes); "serdes");
if (err == -ENODEV || err == -ENOSYS) { if (!memac->serdes) {
dev_dbg(mac_dev->dev, "could not get (optional) serdes\n"); dev_dbg(mac_dev->dev, "could not get (optional) serdes\n");
memac->serdes = NULL;
} else if (IS_ERR(memac->serdes)) { } else if (IS_ERR(memac->serdes)) {
dev_err_probe(mac_dev->dev, err, "could not get serdes\n"); err = PTR_ERR(memac->serdes);
goto _return_fm_mac_free; goto _return_fm_mac_free;
} }
......
...@@ -1154,9 +1154,8 @@ static int lan966x_probe(struct platform_device *pdev) ...@@ -1154,9 +1154,8 @@ static int lan966x_probe(struct platform_device *pdev)
lan966x->ports[p]->config.portmode = phy_mode; lan966x->ports[p]->config.portmode = phy_mode;
lan966x->ports[p]->fwnode = fwnode_handle_get(portnp); lan966x->ports[p]->fwnode = fwnode_handle_get(portnp);
serdes = devm_of_phy_get(lan966x->dev, to_of_node(portnp), NULL); serdes = devm_of_phy_optional_get(lan966x->dev,
if (PTR_ERR(serdes) == -ENODEV) to_of_node(portnp), NULL);
serdes = NULL;
if (IS_ERR(serdes)) { if (IS_ERR(serdes)) {
err = PTR_ERR(serdes); err = PTR_ERR(serdes);
goto cleanup_ports; goto cleanup_ports;
......
...@@ -1330,12 +1330,9 @@ static struct phy *devm_of_phy_optional_get_index(struct device *dev, ...@@ -1330,12 +1330,9 @@ static struct phy *devm_of_phy_optional_get_index(struct device *dev,
if (!name) if (!name)
return ERR_PTR(-ENOMEM); return ERR_PTR(-ENOMEM);
phy = devm_of_phy_get(dev, np, name); phy = devm_of_phy_optional_get(dev, np, name);
kfree(name); kfree(name);
if (PTR_ERR(phy) == -ENODEV)
phy = NULL;
return phy; return phy;
} }
......
...@@ -99,28 +99,17 @@ ...@@ -99,28 +99,17 @@
#define DEBOUNCE_TIME msecs_to_jiffies(50) #define DEBOUNCE_TIME msecs_to_jiffies(50)
#define POLL_TIME msecs_to_jiffies(250) #define POLL_TIME msecs_to_jiffies(250)
enum sun4i_usb_phy_type {
sun4i_a10_phy,
sun6i_a31_phy,
sun8i_a33_phy,
sun8i_a83t_phy,
sun8i_h3_phy,
sun8i_r40_phy,
sun8i_v3s_phy,
sun50i_a64_phy,
sun50i_h6_phy,
};
struct sun4i_usb_phy_cfg { struct sun4i_usb_phy_cfg {
int num_phys; int num_phys;
int hsic_index; int hsic_index;
enum sun4i_usb_phy_type type;
u32 disc_thresh; u32 disc_thresh;
u32 hci_phy_ctl_clear; u32 hci_phy_ctl_clear;
u8 phyctl_offset; u8 phyctl_offset;
bool dedicated_clocks; bool dedicated_clocks;
bool phy0_dual_route; bool phy0_dual_route;
bool needs_phy2_siddq; bool needs_phy2_siddq;
bool siddq_in_base;
bool poll_vbusen;
int missing_phys; int missing_phys;
}; };
...@@ -252,7 +241,8 @@ static void sun4i_usb_phy_passby(struct sun4i_usb_phy *phy, int enable) ...@@ -252,7 +241,8 @@ static void sun4i_usb_phy_passby(struct sun4i_usb_phy *phy, int enable)
SUNXI_AHB_INCRX_ALIGN_EN | SUNXI_ULPI_BYPASS_EN; SUNXI_AHB_INCRX_ALIGN_EN | SUNXI_ULPI_BYPASS_EN;
/* A83T USB2 is HSIC */ /* A83T USB2 is HSIC */
if (phy_data->cfg->type == sun8i_a83t_phy && phy->index == 2) if (phy_data->cfg->hsic_index &&
phy->index == phy_data->cfg->hsic_index)
bits |= SUNXI_EHCI_HS_FORCE | SUNXI_HSIC_CONNECT_INT | bits |= SUNXI_EHCI_HS_FORCE | SUNXI_HSIC_CONNECT_INT |
SUNXI_HSIC; SUNXI_HSIC;
...@@ -340,8 +330,7 @@ static int sun4i_usb_phy_init(struct phy *_phy) ...@@ -340,8 +330,7 @@ static int sun4i_usb_phy_init(struct phy *_phy)
writel(val, phy->pmu + REG_HCI_PHY_CTL); writel(val, phy->pmu + REG_HCI_PHY_CTL);
} }
if (data->cfg->type == sun8i_a83t_phy || if (data->cfg->siddq_in_base) {
data->cfg->type == sun50i_h6_phy) {
if (phy->index == 0) { if (phy->index == 0) {
val = readl(data->base + data->cfg->phyctl_offset); val = readl(data->base + data->cfg->phyctl_offset);
val |= PHY_CTL_VBUSVLDEXT; val |= PHY_CTL_VBUSVLDEXT;
...@@ -385,8 +374,7 @@ static int sun4i_usb_phy_exit(struct phy *_phy) ...@@ -385,8 +374,7 @@ static int sun4i_usb_phy_exit(struct phy *_phy)
struct sun4i_usb_phy_data *data = to_sun4i_usb_phy_data(phy); struct sun4i_usb_phy_data *data = to_sun4i_usb_phy_data(phy);
if (phy->index == 0) { if (phy->index == 0) {
if (data->cfg->type == sun8i_a83t_phy || if (data->cfg->siddq_in_base) {
data->cfg->type == sun50i_h6_phy) {
void __iomem *phyctl = data->base + void __iomem *phyctl = data->base +
data->cfg->phyctl_offset; data->cfg->phyctl_offset;
...@@ -466,9 +454,8 @@ static bool sun4i_usb_phy0_poll(struct sun4i_usb_phy_data *data) ...@@ -466,9 +454,8 @@ static bool sun4i_usb_phy0_poll(struct sun4i_usb_phy_data *data)
* vbus using the N_VBUSEN pin on the pmic, so we must poll * vbus using the N_VBUSEN pin on the pmic, so we must poll
* when using the pmic for vbus-det _and_ we're driving vbus. * when using the pmic for vbus-det _and_ we're driving vbus.
*/ */
if ((data->cfg->type == sun6i_a31_phy || if (data->cfg->poll_vbusen && data->vbus_power_supply &&
data->cfg->type == sun8i_a33_phy) && data->phys[0].regulator_on)
data->vbus_power_supply && data->phys[0].regulator_on)
return true; return true;
return false; return false;
...@@ -918,9 +905,15 @@ static int sun4i_usb_phy_probe(struct platform_device *pdev) ...@@ -918,9 +905,15 @@ static int sun4i_usb_phy_probe(struct platform_device *pdev)
return 0; return 0;
} }
static const struct sun4i_usb_phy_cfg suniv_f1c100s_cfg = {
.num_phys = 1,
.disc_thresh = 3,
.phyctl_offset = REG_PHYCTL_A10,
.dedicated_clocks = true,
};
static const struct sun4i_usb_phy_cfg sun4i_a10_cfg = { static const struct sun4i_usb_phy_cfg sun4i_a10_cfg = {
.num_phys = 3, .num_phys = 3,
.type = sun4i_a10_phy,
.disc_thresh = 3, .disc_thresh = 3,
.phyctl_offset = REG_PHYCTL_A10, .phyctl_offset = REG_PHYCTL_A10,
.dedicated_clocks = false, .dedicated_clocks = false,
...@@ -928,7 +921,6 @@ static const struct sun4i_usb_phy_cfg sun4i_a10_cfg = { ...@@ -928,7 +921,6 @@ static const struct sun4i_usb_phy_cfg sun4i_a10_cfg = {
static const struct sun4i_usb_phy_cfg sun5i_a13_cfg = { static const struct sun4i_usb_phy_cfg sun5i_a13_cfg = {
.num_phys = 2, .num_phys = 2,
.type = sun4i_a10_phy,
.disc_thresh = 2, .disc_thresh = 2,
.phyctl_offset = REG_PHYCTL_A10, .phyctl_offset = REG_PHYCTL_A10,
.dedicated_clocks = false, .dedicated_clocks = false,
...@@ -936,15 +928,14 @@ static const struct sun4i_usb_phy_cfg sun5i_a13_cfg = { ...@@ -936,15 +928,14 @@ static const struct sun4i_usb_phy_cfg sun5i_a13_cfg = {
static const struct sun4i_usb_phy_cfg sun6i_a31_cfg = { static const struct sun4i_usb_phy_cfg sun6i_a31_cfg = {
.num_phys = 3, .num_phys = 3,
.type = sun6i_a31_phy,
.disc_thresh = 3, .disc_thresh = 3,
.phyctl_offset = REG_PHYCTL_A10, .phyctl_offset = REG_PHYCTL_A10,
.dedicated_clocks = true, .dedicated_clocks = true,
.poll_vbusen = true,
}; };
static const struct sun4i_usb_phy_cfg sun7i_a20_cfg = { static const struct sun4i_usb_phy_cfg sun7i_a20_cfg = {
.num_phys = 3, .num_phys = 3,
.type = sun4i_a10_phy,
.disc_thresh = 2, .disc_thresh = 2,
.phyctl_offset = REG_PHYCTL_A10, .phyctl_offset = REG_PHYCTL_A10,
.dedicated_clocks = false, .dedicated_clocks = false,
...@@ -952,31 +943,30 @@ static const struct sun4i_usb_phy_cfg sun7i_a20_cfg = { ...@@ -952,31 +943,30 @@ static const struct sun4i_usb_phy_cfg sun7i_a20_cfg = {
static const struct sun4i_usb_phy_cfg sun8i_a23_cfg = { static const struct sun4i_usb_phy_cfg sun8i_a23_cfg = {
.num_phys = 2, .num_phys = 2,
.type = sun6i_a31_phy,
.disc_thresh = 3, .disc_thresh = 3,
.phyctl_offset = REG_PHYCTL_A10, .phyctl_offset = REG_PHYCTL_A10,
.dedicated_clocks = true, .dedicated_clocks = true,
.poll_vbusen = true,
}; };
static const struct sun4i_usb_phy_cfg sun8i_a33_cfg = { static const struct sun4i_usb_phy_cfg sun8i_a33_cfg = {
.num_phys = 2, .num_phys = 2,
.type = sun8i_a33_phy,
.disc_thresh = 3, .disc_thresh = 3,
.phyctl_offset = REG_PHYCTL_A33, .phyctl_offset = REG_PHYCTL_A33,
.dedicated_clocks = true, .dedicated_clocks = true,
.poll_vbusen = true,
}; };
static const struct sun4i_usb_phy_cfg sun8i_a83t_cfg = { static const struct sun4i_usb_phy_cfg sun8i_a83t_cfg = {
.num_phys = 3, .num_phys = 3,
.hsic_index = 2, .hsic_index = 2,
.type = sun8i_a83t_phy,
.phyctl_offset = REG_PHYCTL_A33, .phyctl_offset = REG_PHYCTL_A33,
.dedicated_clocks = true, .dedicated_clocks = true,
.siddq_in_base = true,
}; };
static const struct sun4i_usb_phy_cfg sun8i_h3_cfg = { static const struct sun4i_usb_phy_cfg sun8i_h3_cfg = {
.num_phys = 4, .num_phys = 4,
.type = sun8i_h3_phy,
.disc_thresh = 3, .disc_thresh = 3,
.phyctl_offset = REG_PHYCTL_A33, .phyctl_offset = REG_PHYCTL_A33,
.dedicated_clocks = true, .dedicated_clocks = true,
...@@ -986,7 +976,6 @@ static const struct sun4i_usb_phy_cfg sun8i_h3_cfg = { ...@@ -986,7 +976,6 @@ static const struct sun4i_usb_phy_cfg sun8i_h3_cfg = {
static const struct sun4i_usb_phy_cfg sun8i_r40_cfg = { static const struct sun4i_usb_phy_cfg sun8i_r40_cfg = {
.num_phys = 3, .num_phys = 3,
.type = sun8i_r40_phy,
.disc_thresh = 3, .disc_thresh = 3,
.phyctl_offset = REG_PHYCTL_A33, .phyctl_offset = REG_PHYCTL_A33,
.dedicated_clocks = true, .dedicated_clocks = true,
...@@ -996,7 +985,6 @@ static const struct sun4i_usb_phy_cfg sun8i_r40_cfg = { ...@@ -996,7 +985,6 @@ static const struct sun4i_usb_phy_cfg sun8i_r40_cfg = {
static const struct sun4i_usb_phy_cfg sun8i_v3s_cfg = { static const struct sun4i_usb_phy_cfg sun8i_v3s_cfg = {
.num_phys = 1, .num_phys = 1,
.type = sun8i_v3s_phy,
.disc_thresh = 3, .disc_thresh = 3,
.phyctl_offset = REG_PHYCTL_A33, .phyctl_offset = REG_PHYCTL_A33,
.dedicated_clocks = true, .dedicated_clocks = true,
...@@ -1006,16 +994,15 @@ static const struct sun4i_usb_phy_cfg sun8i_v3s_cfg = { ...@@ -1006,16 +994,15 @@ static const struct sun4i_usb_phy_cfg sun8i_v3s_cfg = {
static const struct sun4i_usb_phy_cfg sun20i_d1_cfg = { static const struct sun4i_usb_phy_cfg sun20i_d1_cfg = {
.num_phys = 2, .num_phys = 2,
.type = sun50i_h6_phy,
.phyctl_offset = REG_PHYCTL_A33, .phyctl_offset = REG_PHYCTL_A33,
.dedicated_clocks = true, .dedicated_clocks = true,
.hci_phy_ctl_clear = PHY_CTL_SIDDQ, .hci_phy_ctl_clear = PHY_CTL_SIDDQ,
.phy0_dual_route = true, .phy0_dual_route = true,
.siddq_in_base = true,
}; };
static const struct sun4i_usb_phy_cfg sun50i_a64_cfg = { static const struct sun4i_usb_phy_cfg sun50i_a64_cfg = {
.num_phys = 2, .num_phys = 2,
.type = sun50i_a64_phy,
.disc_thresh = 3, .disc_thresh = 3,
.phyctl_offset = REG_PHYCTL_A33, .phyctl_offset = REG_PHYCTL_A33,
.dedicated_clocks = true, .dedicated_clocks = true,
...@@ -1025,22 +1012,22 @@ static const struct sun4i_usb_phy_cfg sun50i_a64_cfg = { ...@@ -1025,22 +1012,22 @@ static const struct sun4i_usb_phy_cfg sun50i_a64_cfg = {
static const struct sun4i_usb_phy_cfg sun50i_h6_cfg = { static const struct sun4i_usb_phy_cfg sun50i_h6_cfg = {
.num_phys = 4, .num_phys = 4,
.type = sun50i_h6_phy,
.phyctl_offset = REG_PHYCTL_A33, .phyctl_offset = REG_PHYCTL_A33,
.dedicated_clocks = true, .dedicated_clocks = true,
.phy0_dual_route = true, .phy0_dual_route = true,
.missing_phys = BIT(1) | BIT(2), .missing_phys = BIT(1) | BIT(2),
.siddq_in_base = true,
}; };
static const struct sun4i_usb_phy_cfg sun50i_h616_cfg = { static const struct sun4i_usb_phy_cfg sun50i_h616_cfg = {
.num_phys = 4, .num_phys = 4,
.type = sun50i_h6_phy,
.disc_thresh = 3, .disc_thresh = 3,
.phyctl_offset = REG_PHYCTL_A33, .phyctl_offset = REG_PHYCTL_A33,
.dedicated_clocks = true, .dedicated_clocks = true,
.phy0_dual_route = true, .phy0_dual_route = true,
.hci_phy_ctl_clear = PHY_CTL_SIDDQ, .hci_phy_ctl_clear = PHY_CTL_SIDDQ,
.needs_phy2_siddq = true, .needs_phy2_siddq = true,
.siddq_in_base = true,
}; };
static const struct of_device_id sun4i_usb_phy_of_match[] = { static const struct of_device_id sun4i_usb_phy_of_match[] = {
...@@ -1059,6 +1046,8 @@ static const struct of_device_id sun4i_usb_phy_of_match[] = { ...@@ -1059,6 +1046,8 @@ static const struct of_device_id sun4i_usb_phy_of_match[] = {
.data = &sun50i_a64_cfg}, .data = &sun50i_a64_cfg},
{ .compatible = "allwinner,sun50i-h6-usb-phy", .data = &sun50i_h6_cfg }, { .compatible = "allwinner,sun50i-h6-usb-phy", .data = &sun50i_h6_cfg },
{ .compatible = "allwinner,sun50i-h616-usb-phy", .data = &sun50i_h616_cfg }, { .compatible = "allwinner,sun50i-h616-usb-phy", .data = &sun50i_h616_cfg },
{ .compatible = "allwinner,suniv-f1c100s-usb-phy",
.data = &suniv_f1c100s_cfg },
{ }, { },
}; };
MODULE_DEVICE_TABLE(of, sun4i_usb_phy_of_match); MODULE_DEVICE_TABLE(of, sun4i_usb_phy_of_match);
......
...@@ -39,8 +39,8 @@ static inline void mtk_phy_update_bits(void __iomem *reg, u32 mask, u32 val) ...@@ -39,8 +39,8 @@ static inline void mtk_phy_update_bits(void __iomem *reg, u32 mask, u32 val)
/* field @mask shall be constant and continuous */ /* field @mask shall be constant and continuous */
#define mtk_phy_update_field(reg, mask, val) \ #define mtk_phy_update_field(reg, mask, val) \
({ \ ({ \
typeof(mask) mask_ = (mask); \ BUILD_BUG_ON_MSG(!__builtin_constant_p(mask), "mask is not constant"); \
mtk_phy_update_bits(reg, mask_, FIELD_PREP(mask_, val)); \ mtk_phy_update_bits(reg, mask, FIELD_PREP(mask, val)); \
}) })
#endif #endif
...@@ -84,6 +84,10 @@ static const struct of_device_id can_transceiver_phy_ids[] = { ...@@ -84,6 +84,10 @@ static const struct of_device_id can_transceiver_phy_ids[] = {
.compatible = "ti,tcan1043", .compatible = "ti,tcan1043",
.data = &tcan1043_drvdata .data = &tcan1043_drvdata
}, },
{
.compatible = "nxp,tjr1443",
.data = &tcan1043_drvdata
},
{ } { }
}; };
MODULE_DEVICE_TABLE(of, can_transceiver_phy_ids); MODULE_DEVICE_TABLE(of, can_transceiver_phy_ids);
......
...@@ -766,27 +766,6 @@ struct phy *phy_get(struct device *dev, const char *string) ...@@ -766,27 +766,6 @@ struct phy *phy_get(struct device *dev, const char *string)
} }
EXPORT_SYMBOL_GPL(phy_get); EXPORT_SYMBOL_GPL(phy_get);
/**
* phy_optional_get() - lookup and obtain a reference to an optional phy.
* @dev: device that requests this phy
* @string: the phy name as given in the dt data or the name of the controller
* port for non-dt case
*
* Returns the phy driver, after getting a refcount to it; or
* NULL if there is no such phy. The caller is responsible for
* calling phy_put() to release that count.
*/
struct phy *phy_optional_get(struct device *dev, const char *string)
{
struct phy *phy = phy_get(dev, string);
if (PTR_ERR(phy) == -ENODEV)
phy = NULL;
return phy;
}
EXPORT_SYMBOL_GPL(phy_optional_get);
/** /**
* devm_phy_get() - lookup and obtain a reference to a phy. * devm_phy_get() - lookup and obtain a reference to a phy.
* @dev: device that requests this phy * @dev: device that requests this phy
...@@ -879,6 +858,36 @@ struct phy *devm_of_phy_get(struct device *dev, struct device_node *np, ...@@ -879,6 +858,36 @@ struct phy *devm_of_phy_get(struct device *dev, struct device_node *np,
} }
EXPORT_SYMBOL_GPL(devm_of_phy_get); EXPORT_SYMBOL_GPL(devm_of_phy_get);
/**
* devm_of_phy_optional_get() - lookup and obtain a reference to an optional
* phy.
* @dev: device that requests this phy
* @np: node containing the phy
* @con_id: name of the phy from device's point of view
*
* Gets the phy using of_phy_get(), and associates a device with it using
* devres. On driver detach, release function is invoked on the devres data,
* then, devres data is freed. This differs to devm_of_phy_get() in
* that if the phy does not exist, it is not considered an error and
* -ENODEV will not be returned. Instead the NULL phy is returned,
* which can be passed to all other phy consumer calls.
*/
struct phy *devm_of_phy_optional_get(struct device *dev, struct device_node *np,
const char *con_id)
{
struct phy *phy = devm_of_phy_get(dev, np, con_id);
if (PTR_ERR(phy) == -ENODEV)
phy = NULL;
if (IS_ERR(phy))
dev_err_probe(dev, PTR_ERR(phy), "failed to get PHY %pOF:%s",
np, con_id);
return phy;
}
EXPORT_SYMBOL_GPL(devm_of_phy_optional_get);
/** /**
* devm_of_phy_get_by_index() - lookup and obtain a reference to a phy by index. * devm_of_phy_get_by_index() - lookup and obtain a reference to a phy by index.
* @dev: device that requests this phy * @dev: device that requests this phy
......
...@@ -50,14 +50,56 @@ config PHY_QCOM_PCIE2 ...@@ -50,14 +50,56 @@ config PHY_QCOM_PCIE2
Enable this to support the Qualcomm PCIe PHY, used with the Synopsys Enable this to support the Qualcomm PCIe PHY, used with the Synopsys
based PCIe controller. based PCIe controller.
config PHY_QCOM_QMP menuconfig PHY_QCOM_QMP
tristate "Qualcomm QMP PHY Driver" tristate "Qualcomm QMP PHY Drivers"
depends on OF && COMMON_CLK && (ARCH_QCOM || COMPILE_TEST) depends on OF && COMMON_CLK && (ARCH_QCOM || COMPILE_TEST)
if PHY_QCOM_QMP
config PHY_QCOM_QMP_COMBO
tristate "Qualcomm QMP Combo PHY Driver"
default PHY_QCOM_QMP
select GENERIC_PHY select GENERIC_PHY
select MFD_SYSCON select MFD_SYSCON
help help
Enable this to support the QMP PHY transceiver that is used Enable this to support the QMP Combo PHY transceiver that is used
with controllers such as PCIe, UFS, and USB on Qualcomm chips. with USB3 and DisplayPort controllers on Qualcomm chips.
config PHY_QCOM_QMP_PCIE
tristate "Qualcomm QMP PCIe PHY Driver"
depends on PCI || COMPILE_TEST
select GENERIC_PHY
default PHY_QCOM_QMP
help
Enable this to support the QMP PCIe PHY transceiver that is used
with PCIe controllers on Qualcomm chips.
config PHY_QCOM_QMP_PCIE_8996
tristate "Qualcomm QMP PCIe 8996 PHY Driver"
depends on PCI || COMPILE_TEST
select GENERIC_PHY
default PHY_QCOM_QMP
help
Enable this to support the QMP PCIe PHY transceiver that is used
with PCIe controllers on Qualcomm msm8996 chips.
config PHY_QCOM_QMP_UFS
tristate "Qualcomm QMP UFS PHY Driver"
select GENERIC_PHY
default PHY_QCOM_QMP
help
Enable this to support the QMP UFS PHY transceiver that is used
with UFS controllers on Qualcomm chips.
config PHY_QCOM_QMP_USB
tristate "Qualcomm QMP USB PHY Driver"
select GENERIC_PHY
default PHY_QCOM_QMP
help
Enable this to support the QMP USB PHY transceiver that is used
with USB3 controllers on Qualcomm chips.
endif # PHY_QCOM_QMP
config PHY_QCOM_QUSB2 config PHY_QCOM_QUSB2
tristate "Qualcomm QUSB2 PHY Driver" tristate "Qualcomm QUSB2 PHY Driver"
...@@ -70,6 +112,24 @@ config PHY_QCOM_QUSB2 ...@@ -70,6 +112,24 @@ config PHY_QCOM_QUSB2
PHY which is usually paired with either the ChipIdea or Synopsys DWC3 PHY which is usually paired with either the ChipIdea or Synopsys DWC3
USB IPs on MSM SOCs. USB IPs on MSM SOCs.
config PHY_QCOM_SNPS_EUSB2
tristate "Qualcomm SNPS eUSB2 PHY Driver"
depends on OF && (ARCH_QCOM || COMPILE_TEST)
select GENERIC_PHY
help
Enable support for the USB high-speed SNPS eUSB2 phy on Qualcomm
chipsets. The PHY is paired with a Synopsys DWC3 USB controller
on Qualcomm SOCs.
config PHY_QCOM_EUSB2_REPEATER
tristate "Qualcomm SNPS eUSB2 Repeater Driver"
depends on OF && (ARCH_QCOM || COMPILE_TEST)
select GENERIC_PHY
help
Enable support for the USB high-speed SNPS eUSB2 repeater on Qualcomm
PMICs. The repeater is paired with a Synopsys eUSB2 Phy
on Qualcomm SOCs.
config PHY_QCOM_USB_HS config PHY_QCOM_USB_HS
tristate "Qualcomm USB HS PHY module" tristate "Qualcomm USB HS PHY module"
depends on USB_ULPI_BUS depends on USB_ULPI_BUS
......
...@@ -5,14 +5,16 @@ obj-$(CONFIG_PHY_QCOM_EDP) += phy-qcom-edp.o ...@@ -5,14 +5,16 @@ obj-$(CONFIG_PHY_QCOM_EDP) += phy-qcom-edp.o
obj-$(CONFIG_PHY_QCOM_IPQ4019_USB) += phy-qcom-ipq4019-usb.o obj-$(CONFIG_PHY_QCOM_IPQ4019_USB) += phy-qcom-ipq4019-usb.o
obj-$(CONFIG_PHY_QCOM_IPQ806X_SATA) += phy-qcom-ipq806x-sata.o obj-$(CONFIG_PHY_QCOM_IPQ806X_SATA) += phy-qcom-ipq806x-sata.o
obj-$(CONFIG_PHY_QCOM_PCIE2) += phy-qcom-pcie2.o obj-$(CONFIG_PHY_QCOM_PCIE2) += phy-qcom-pcie2.o
obj-$(CONFIG_PHY_QCOM_QMP) += \
phy-qcom-qmp-combo.o \ obj-$(CONFIG_PHY_QCOM_QMP_COMBO) += phy-qcom-qmp-combo.o
phy-qcom-qmp-pcie.o \ obj-$(CONFIG_PHY_QCOM_QMP_PCIE) += phy-qcom-qmp-pcie.o
phy-qcom-qmp-pcie-msm8996.o \ obj-$(CONFIG_PHY_QCOM_QMP_PCIE_8996) += phy-qcom-qmp-pcie-msm8996.o
phy-qcom-qmp-ufs.o \ obj-$(CONFIG_PHY_QCOM_QMP_UFS) += phy-qcom-qmp-ufs.o
phy-qcom-qmp-usb.o obj-$(CONFIG_PHY_QCOM_QMP_USB) += phy-qcom-qmp-usb.o
obj-$(CONFIG_PHY_QCOM_QUSB2) += phy-qcom-qusb2.o obj-$(CONFIG_PHY_QCOM_QUSB2) += phy-qcom-qusb2.o
obj-$(CONFIG_PHY_QCOM_SNPS_EUSB2) += phy-qcom-snps-eusb2.o
obj-$(CONFIG_PHY_QCOM_EUSB2_REPEATER) += phy-qcom-eusb2-repeater.o
obj-$(CONFIG_PHY_QCOM_USB_HS) += phy-qcom-usb-hs.o obj-$(CONFIG_PHY_QCOM_USB_HS) += phy-qcom-usb-hs.o
obj-$(CONFIG_PHY_QCOM_USB_HSIC) += phy-qcom-usb-hsic.o obj-$(CONFIG_PHY_QCOM_USB_HSIC) += phy-qcom-usb-hsic.o
obj-$(CONFIG_PHY_QCOM_USB_HS_28NM) += phy-qcom-usb-hs-28nm.o obj-$(CONFIG_PHY_QCOM_USB_HS_28NM) += phy-qcom-usb-hs-28nm.o
......
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...@@ -243,7 +243,11 @@ static int phy_pipe_clksrc_register(struct qcom_phy *qphy) ...@@ -243,7 +243,11 @@ static int phy_pipe_clksrc_register(struct qcom_phy *qphy)
fixed->fixed_rate = 250000000; fixed->fixed_rate = 250000000;
fixed->hw.init = &init; fixed->hw.init = &init;
return devm_clk_hw_register(qphy->dev, &fixed->hw); ret = devm_clk_hw_register(qphy->dev, &fixed->hw);
if (ret < 0)
return ret;
return devm_of_clk_add_hw_provider(qphy->dev, of_clk_hw_simple_get, &fixed->hw);
} }
static int qcom_pcie2_phy_probe(struct platform_device *pdev) static int qcom_pcie2_phy_probe(struct platform_device *pdev)
......
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...@@ -84,9 +84,9 @@ static const unsigned int pciephy_regs_layout[QPHY_LAYOUT_SIZE] = { ...@@ -84,9 +84,9 @@ static const unsigned int pciephy_regs_layout[QPHY_LAYOUT_SIZE] = {
[QPHY_COM_POWER_DOWN_CONTROL] = 0x404, [QPHY_COM_POWER_DOWN_CONTROL] = 0x404,
[QPHY_COM_START_CONTROL] = 0x408, [QPHY_COM_START_CONTROL] = 0x408,
[QPHY_COM_PCS_READY_STATUS] = 0x448, [QPHY_COM_PCS_READY_STATUS] = 0x448,
[QPHY_SW_RESET] = 0x00, [QPHY_SW_RESET] = QPHY_V2_PCS_SW_RESET,
[QPHY_START_CTRL] = 0x08, [QPHY_START_CTRL] = QPHY_V2_PCS_START_CONTROL,
[QPHY_PCS_STATUS] = 0x174, [QPHY_PCS_STATUS] = QPHY_V2_PCS_PCI_PCS_STATUS,
}; };
static const struct qmp_phy_init_tbl msm8996_pcie_serdes_tbl[] = { static const struct qmp_phy_init_tbl msm8996_pcie_serdes_tbl[] = {
......
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2023, Linaro Limited
*/
#ifndef QCOM_PHY_QMP_PCS_PCIE_V6_H_
#define QCOM_PHY_QMP_PCS_PCIE_V6_H_
/* Only for QMP V6 PHY - PCIE have different offsets than V5 */
#define QPHY_PCIE_V6_PCS_PCIE_POWER_STATE_CONFIG2 0x0c
#define QPHY_PCIE_V6_PCS_PCIE_POWER_STATE_CONFIG4 0x14
#define QPHY_PCIE_V6_PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x20
#define QPHY_PCIE_V6_PCS_PCIE_OSC_DTCT_ACTIONS 0x94
#endif
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2023, Linaro Limited
*/
#ifndef QCOM_PHY_QMP_PCS_PCIE_V6_20_H_
#define QCOM_PHY_QMP_PCS_PCIE_V6_20_H_
/* Only for QMP V6_20 PHY - PCIE have different offsets than V5 */
#define QPHY_PCIE_V6_20_PCS_POWER_STATE_CONFIG2 0x00c
#define QPHY_PCIE_V6_20_PCS_TX_RX_CONFIG 0x018
#define QPHY_PCIE_V6_20_PCS_ENDPOINT_REFCLK_DRIVE 0x01c
#define QPHY_PCIE_V6_20_PCS_OSC_DTCT_ATCIONS 0x090
#define QPHY_PCIE_V6_20_PCS_EQ_CONFIG1 0x0a0
#define QPHY_PCIE_V6_20_PCS_EQ_CONFIG5 0x108
#define QPHY_PCIE_V6_20_PCS_G4_PRE_GAIN 0x15c
#define QPHY_PCIE_V6_20_PCS_RX_MARGINING_CONFIG1 0x17c
#define QPHY_PCIE_V6_20_PCS_RX_MARGINING_CONFIG3 0x184
#define QPHY_PCIE_V6_20_PCS_RX_MARGINING_CONFIG5 0x18c
#define QPHY_PCIE_V6_20_PCS_G3_FOM_EQ_CONFIG5 0x1ac
#define QPHY_PCIE_V6_20_PCS_G4_FOM_EQ_CONFIG5 0x1c0
#endif
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...@@ -6,12 +6,15 @@ ...@@ -6,12 +6,15 @@
#ifndef QCOM_PHY_QMP_PCS_UFS_V3_H_ #ifndef QCOM_PHY_QMP_PCS_UFS_V3_H_
#define QCOM_PHY_QMP_PCS_UFS_V3_H_ #define QCOM_PHY_QMP_PCS_UFS_V3_H_
#define QPHY_V3_PCS_UFS_PHY_START 0x000
#define QPHY_V3_PCS_UFS_POWER_DOWN_CONTROL 0x004
#define QPHY_V3_PCS_UFS_TX_LARGE_AMP_DRV_LVL 0x02c #define QPHY_V3_PCS_UFS_TX_LARGE_AMP_DRV_LVL 0x02c
#define QPHY_V3_PCS_UFS_TX_SMALL_AMP_DRV_LVL 0x034 #define QPHY_V3_PCS_UFS_TX_SMALL_AMP_DRV_LVL 0x034
#define QPHY_V3_PCS_UFS_RX_SYM_RESYNC_CTRL 0x134 #define QPHY_V3_PCS_UFS_RX_SYM_RESYNC_CTRL 0x134
#define QPHY_V3_PCS_UFS_RX_MIN_HIBERN8_TIME 0x138 #define QPHY_V3_PCS_UFS_RX_MIN_HIBERN8_TIME 0x138
#define QPHY_V3_PCS_UFS_RX_SIGDET_CTRL1 0x13c #define QPHY_V3_PCS_UFS_RX_SIGDET_CTRL1 0x13c
#define QPHY_V3_PCS_UFS_RX_SIGDET_CTRL2 0x140 #define QPHY_V3_PCS_UFS_RX_SIGDET_CTRL2 0x140
#define QPHY_V3_PCS_UFS_READY_STATUS 0x160
#define QPHY_V3_PCS_UFS_TX_MID_TERM_CTRL1 0x1bc #define QPHY_V3_PCS_UFS_TX_MID_TERM_CTRL1 0x1bc
#define QPHY_V3_PCS_UFS_MULTI_LANE_CTRL1 0x1c4 #define QPHY_V3_PCS_UFS_MULTI_LANE_CTRL1 0x1c4
......
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