Commit 907e0cde authored by Shengjiu Wang's avatar Shengjiu Wang Committed by Mark Brown

ASoC: fsl_sai: Add pm qos cpu latency support

On SoCs such as i.MX7ULP, cpuidle has some levels which
may disable system/bus clocks, so need to add pm_qos to
prevent cpuidle from entering low level idles and make sure
system/bus clocks are enabled when sai is active.
Signed-off-by: default avatarShengjiu Wang <shengjiu.wang@nxp.com>
Link: https://lore.kernel.org/r/1613983220-5373-1-git-send-email-shengjiu.wang@nxp.comSigned-off-by: default avatarMark Brown <broonie@kernel.org>
parent 13fba3e8
......@@ -10,6 +10,7 @@
#include <linux/module.h>
#include <linux/of_address.h>
#include <linux/of_device.h>
#include <linux/pm_qos.h>
#include <linux/pm_runtime.h>
#include <linux/regmap.h>
#include <linux/slab.h>
......@@ -1177,6 +1178,7 @@ static const struct fsl_sai_soc_data fsl_sai_vf610_data = {
.fifo_depth = 32,
.reg_offset = 0,
.mclk0_is_mclk1 = false,
.flags = 0,
};
static const struct fsl_sai_soc_data fsl_sai_imx6sx_data = {
......@@ -1185,6 +1187,7 @@ static const struct fsl_sai_soc_data fsl_sai_imx6sx_data = {
.fifo_depth = 32,
.reg_offset = 0,
.mclk0_is_mclk1 = true,
.flags = 0,
};
static const struct fsl_sai_soc_data fsl_sai_imx7ulp_data = {
......@@ -1193,6 +1196,7 @@ static const struct fsl_sai_soc_data fsl_sai_imx7ulp_data = {
.fifo_depth = 16,
.reg_offset = 8,
.mclk0_is_mclk1 = false,
.flags = PMQOS_CPU_LATENCY,
};
static const struct fsl_sai_soc_data fsl_sai_imx8mq_data = {
......@@ -1201,6 +1205,7 @@ static const struct fsl_sai_soc_data fsl_sai_imx8mq_data = {
.fifo_depth = 128,
.reg_offset = 8,
.mclk0_is_mclk1 = false,
.flags = 0,
};
static const struct fsl_sai_soc_data fsl_sai_imx8qm_data = {
......@@ -1209,6 +1214,7 @@ static const struct fsl_sai_soc_data fsl_sai_imx8qm_data = {
.fifo_depth = 64,
.reg_offset = 0,
.mclk0_is_mclk1 = false,
.flags = 0,
};
static const struct of_device_id fsl_sai_ids[] = {
......@@ -1235,6 +1241,9 @@ static int fsl_sai_runtime_suspend(struct device *dev)
clk_disable_unprepare(sai->bus_clk);
if (sai->soc_data->flags & PMQOS_CPU_LATENCY)
cpu_latency_qos_remove_request(&sai->pm_qos_req);
regcache_cache_only(sai->regmap, true);
return 0;
......@@ -1264,6 +1273,9 @@ static int fsl_sai_runtime_resume(struct device *dev)
goto disable_tx_clk;
}
if (sai->soc_data->flags & PMQOS_CPU_LATENCY)
cpu_latency_qos_add_request(&sai->pm_qos_req, 0);
regcache_cache_only(sai->regmap, false);
regcache_mark_dirty(sai->regmap);
regmap_write(sai->regmap, FSL_SAI_TCSR(ofs), FSL_SAI_CSR_SR);
......
......@@ -216,12 +216,15 @@
#define FSL_SAI_MAXBURST_TX 6
#define FSL_SAI_MAXBURST_RX 6
#define PMQOS_CPU_LATENCY BIT(0)
struct fsl_sai_soc_data {
bool use_imx_pcm;
bool use_edma;
bool mclk0_is_mclk1;
unsigned int fifo_depth;
unsigned int reg_offset;
unsigned int flags;
};
/**
......@@ -273,6 +276,7 @@ struct fsl_sai {
struct snd_dmaengine_dai_dma_data dma_params_tx;
struct fsl_sai_verid verid;
struct fsl_sai_param param;
struct pm_qos_request pm_qos_req;
};
#define TX 1
......
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