Commit 90bc8e00 authored by Arkadiusz Kubalewski's avatar Arkadiusz Kubalewski Committed by Tony Nguyen

i40e: Add hardware configuration for software based DCB

Add registers and definitions required for applying
DCB related hardware configuration.

Add functions responsible for calculating and setting proper
hardware configuration values for software based DCB functionality.

Add function responsible for invoking Admin Queue command, which
results in applying new DCB configuration to the hardware.

Update copyright dates as appropriate.

Software based DCB is a brand-new feature in i40e driver.
Before, DCB was implemented by Firmware LLDP agent only. The agent was
responsible for handling incoming DCB-related LLDP frames and
applying received DCB configuration to hardware.

New communication channel between software and hardware is required
for software driver. It must be able to calculate and configure all
the registers related for DCB feature.
Signed-off-by: default avatarAleksandr Loktionov <aleksandr.loktionov@intel.com>
Signed-off-by: default avatarArkadiusz Kubalewski <arkadiusz.kubalewski@intel.com>
Tested-by: default avatarTony Brelinski <tonyx.brelinski@intel.com>
Signed-off-by: default avatarTony Nguyen <anthony.l.nguyen@intel.com>
parent dc9d8758
/* SPDX-License-Identifier: GPL-2.0 */
/* Copyright(c) 2013 - 2018 Intel Corporation. */
/* Copyright(c) 2013 - 2021 Intel Corporation. */
#ifndef _I40E_ADMINQ_CMD_H_
#define _I40E_ADMINQ_CMD_H_
......@@ -1080,6 +1080,7 @@ struct i40e_aqc_add_remove_control_packet_filter {
#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC 0x0001
#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP 0x0002
#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX 0x0008
#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_RX 0x0000
__le16 seid;
__le16 queue;
u8 reserved[2];
......@@ -2184,6 +2185,14 @@ I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_get_cee_dcb_cfg_resp);
* Used to replace the local MIB of a given LLDP agent. e.g. DCBx
*/
struct i40e_aqc_lldp_set_local_mib {
#define SET_LOCAL_MIB_AC_TYPE_DCBX_SHIFT 0
#define SET_LOCAL_MIB_AC_TYPE_DCBX_MASK (1 << \
SET_LOCAL_MIB_AC_TYPE_DCBX_SHIFT)
#define SET_LOCAL_MIB_AC_TYPE_LOCAL_MIB 0x0
#define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_SHIFT (1)
#define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_MASK (1 << \
SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_SHIFT)
#define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS 0x1
u8 type;
u8 reserved0;
__le16 length;
......
// SPDX-License-Identifier: GPL-2.0
/* Copyright(c) 2013 - 2018 Intel Corporation. */
/* Copyright(c) 2013 - 2021 Intel Corporation. */
#include "i40e.h"
#include "i40e_type.h"
......@@ -3661,6 +3661,46 @@ i40e_status i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type,
return status;
}
/**
* i40e_aq_set_lldp_mib - Set the LLDP MIB
* @hw: pointer to the hw struct
* @mib_type: Local, Remote or both Local and Remote MIBs
* @buff: pointer to a user supplied buffer to store the MIB block
* @buff_size: size of the buffer (in bytes)
* @cmd_details: pointer to command details structure or NULL
*
* Set the LLDP MIB.
**/
enum i40e_status_code
i40e_aq_set_lldp_mib(struct i40e_hw *hw,
u8 mib_type, void *buff, u16 buff_size,
struct i40e_asq_cmd_details *cmd_details)
{
struct i40e_aqc_lldp_set_local_mib *cmd;
enum i40e_status_code status;
struct i40e_aq_desc desc;
cmd = (struct i40e_aqc_lldp_set_local_mib *)&desc.params.raw;
if (buff_size == 0 || !buff)
return I40E_ERR_PARAM;
i40e_fill_default_direct_cmd_desc(&desc,
i40e_aqc_opc_lldp_set_local_mib);
/* Indirect Command */
desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
if (buff_size > I40E_AQ_LARGE_BUF)
desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
desc.datalen = cpu_to_le16(buff_size);
cmd->type = mib_type;
cmd->length = cpu_to_le16(buff_size);
cmd->address_high = cpu_to_le32(upper_32_bits((uintptr_t)buff));
cmd->address_low = cpu_to_le32(lower_32_bits((uintptr_t)buff));
status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
return status;
}
/**
* i40e_aq_cfg_lldp_mib_change_event
* @hw: pointer to the hw struct
......@@ -4479,6 +4519,29 @@ static i40e_status i40e_aq_alternate_read(struct i40e_hw *hw,
return status;
}
/**
* i40e_aq_suspend_port_tx
* @hw: pointer to the hardware structure
* @seid: port seid
* @cmd_details: pointer to command details structure or NULL
*
* Suspend port's Tx traffic
**/
i40e_status i40e_aq_suspend_port_tx(struct i40e_hw *hw, u16 seid,
struct i40e_asq_cmd_details *cmd_details)
{
struct i40e_aqc_tx_sched_ind *cmd;
struct i40e_aq_desc desc;
i40e_status status;
cmd = (struct i40e_aqc_tx_sched_ind *)&desc.params.raw;
i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_suspend_port_tx);
cmd->vsi_seid = cpu_to_le16(seid);
status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
return status;
}
/**
* i40e_aq_resume_port_tx
* @hw: pointer to the hardware structure
......
This diff is collapsed.
/* SPDX-License-Identifier: GPL-2.0 */
/* Copyright(c) 2013 - 2018 Intel Corporation. */
/* Copyright(c) 2013 - 2021 Intel Corporation. */
#ifndef _I40E_DCB_H_
#define _I40E_DCB_H_
#include "i40e_type.h"
#define I40E_DCBX_STATUS_NOT_STARTED 0
#define I40E_DCBX_STATUS_IN_PROGRESS 1
#define I40E_DCBX_STATUS_DONE 2
#define I40E_DCBX_STATUS_MULTIPLE_PEERS 3
#define I40E_DCBX_STATUS_DISABLED 7
#define I40E_TLV_TYPE_END 0
......@@ -22,6 +24,7 @@
#define I40E_CEE_DCBX_OUI 0x001b21
#define I40E_CEE_DCBX_TYPE 2
#define I40E_CEE_SUBTYPE_CTRL 1
#define I40E_CEE_SUBTYPE_PG_CFG 2
#define I40E_CEE_SUBTYPE_PFC_CFG 3
#define I40E_CEE_SUBTYPE_APP_PRI 4
......@@ -64,6 +67,8 @@
#define I40E_IEEE_TSA_ETS 2
/* Defines for IEEE PFC TLV */
#define I40E_DCB_PFC_ENABLED 2
#define I40E_DCB_PFC_FORCED_NUM_TC 2
#define I40E_IEEE_PFC_CAP_SHIFT 0
#define I40E_IEEE_PFC_CAP_MASK (0xF << I40E_IEEE_PFC_CAP_SHIFT)
#define I40E_IEEE_PFC_MBC_SHIFT 6
......@@ -77,9 +82,30 @@
#define I40E_IEEE_APP_PRIO_SHIFT 5
#define I40E_IEEE_APP_PRIO_MASK (0x7 << I40E_IEEE_APP_PRIO_SHIFT)
/* TLV definitions for preparing MIB */
#define I40E_TLV_ID_CHASSIS_ID 0
#define I40E_TLV_ID_PORT_ID 1
#define I40E_TLV_ID_TIME_TO_LIVE 2
#define I40E_IEEE_TLV_ID_ETS_CFG 3
#define I40E_IEEE_TLV_ID_ETS_REC 4
#define I40E_IEEE_TLV_ID_PFC_CFG 5
#define I40E_IEEE_TLV_ID_APP_PRI 6
#define I40E_TLV_ID_END_OF_LLDPPDU 7
#define I40E_TLV_ID_START I40E_IEEE_TLV_ID_ETS_CFG
#pragma pack(1)
#define I40E_IEEE_TLV_HEADER_LENGTH 2
#define I40E_IEEE_ETS_TLV_LENGTH 25
#define I40E_IEEE_PFC_TLV_LENGTH 6
#define I40E_IEEE_APP_TLV_LENGTH 11
/* Defines for default SW DCB config */
#define I40E_IEEE_DEFAULT_ETS_TCBW 100
#define I40E_IEEE_DEFAULT_ETS_WILLING 1
#define I40E_IEEE_DEFAULT_PFC_WILLING 1
#define I40E_IEEE_DEFAULT_NUM_APPS 1
#define I40E_IEEE_DEFAULT_APP_PRIO 3
#pragma pack(1)
/* IEEE 802.1AB LLDP Organization specific TLV */
struct i40e_lldp_org_tlv {
__be16 typelength;
......@@ -102,7 +128,9 @@ struct i40e_cee_ctrl_tlv {
struct i40e_cee_feat_tlv {
struct i40e_cee_tlv_hdr hdr;
u8 en_will_err; /* Bits: |En|Will|Err|Reserved(5)| */
#define I40E_CEE_FEAT_TLV_ENABLE_MASK 0x80
#define I40E_CEE_FEAT_TLV_WILLING_MASK 0x40
#define I40E_CEE_FEAT_TLV_ERR_MASK 0x20
u8 subtype;
u8 tlvinfo[1];
};
......@@ -116,13 +144,140 @@ struct i40e_cee_app_prio {
};
#pragma pack()
enum i40e_get_fw_lldp_status_resp {
I40E_GET_FW_LLDP_STATUS_DISABLED = 0,
I40E_GET_FW_LLDP_STATUS_ENABLED = 1
};
/* Data structures to pass for SW DCBX */
struct i40e_rx_pb_config {
u32 shared_pool_size;
u32 shared_pool_high_wm;
u32 shared_pool_low_wm;
u32 shared_pool_high_thresh[I40E_MAX_TRAFFIC_CLASS];
u32 shared_pool_low_thresh[I40E_MAX_TRAFFIC_CLASS];
u32 tc_pool_size[I40E_MAX_TRAFFIC_CLASS];
u32 tc_pool_high_wm[I40E_MAX_TRAFFIC_CLASS];
u32 tc_pool_low_wm[I40E_MAX_TRAFFIC_CLASS];
};
enum i40e_dcb_arbiter_mode {
I40E_DCB_ARB_MODE_STRICT_PRIORITY = 0,
I40E_DCB_ARB_MODE_ROUND_ROBIN = 1
};
#define I40E_DCB_DEFAULT_MAX_EXPONENT 0xB
#define I40E_DEFAULT_PAUSE_TIME 0xffff
#define I40E_MAX_FRAME_SIZE 4608 /* 4.5 KB */
#define I40E_DEVICE_RPB_SIZE 968000 /* 968 KB */
/* BitTimes (BT) conversion */
#define I40E_BT2KB(BT) (((BT) + (8 * 1024 - 1)) / (8 * 1024))
#define I40E_B2BT(BT) ((BT) * 8)
#define I40E_BT2B(BT) (((BT) + (8 - 1)) / 8)
/* Max Frame(TC) = MFS(max) + MFS(TC) */
#define I40E_MAX_FRAME_TC(mfs_max, mfs_tc) I40E_B2BT((mfs_max) + (mfs_tc))
/* EEE Tx LPI Exit time in Bit Times */
#define I40E_EEE_TX_LPI_EXIT_TIME 142500
/* PCI Round Trip Time in Bit Times */
#define I40E_PCIRTT_LINK_SPEED_10G 20000
#define I40E_PCIRTT_BYTE_LINK_SPEED_20G 40000
#define I40E_PCIRTT_BYTE_LINK_SPEED_40G 80000
/* PFC Frame Delay Bit Times */
#define I40E_PFC_FRAME_DELAY 672
/* Worst case Cable (10GBase-T) Delay Bit Times */
#define I40E_CABLE_DELAY 5556
/* Higher Layer Delay @10G Bit Times */
#define I40E_HIGHER_LAYER_DELAY_10G 6144
/* Interface Delays in Bit Times */
/* TODO: Add for other link speeds 20G/40G/etc. */
#define I40E_INTERFACE_DELAY_10G_MAC_CONTROL 8192
#define I40E_INTERFACE_DELAY_10G_MAC 8192
#define I40E_INTERFACE_DELAY_10G_RS 8192
#define I40E_INTERFACE_DELAY_XGXS 2048
#define I40E_INTERFACE_DELAY_XAUI 2048
#define I40E_INTERFACE_DELAY_10G_BASEX_PCS 2048
#define I40E_INTERFACE_DELAY_10G_BASER_PCS 3584
#define I40E_INTERFACE_DELAY_LX4_PMD 512
#define I40E_INTERFACE_DELAY_CX4_PMD 512
#define I40E_INTERFACE_DELAY_SERIAL_PMA 512
#define I40E_INTERFACE_DELAY_PMD 512
#define I40E_INTERFACE_DELAY_10G_BASET 25600
/* Hardware RX DCB config related defines */
#define I40E_DCB_1_PORT_THRESHOLD 0xF
#define I40E_DCB_1_PORT_FIFO_SIZE 0x10
#define I40E_DCB_2_PORT_THRESHOLD_LOW_NUM_TC 0xF
#define I40E_DCB_2_PORT_FIFO_SIZE_LOW_NUM_TC 0x10
#define I40E_DCB_2_PORT_THRESHOLD_HIGH_NUM_TC 0xC
#define I40E_DCB_2_PORT_FIFO_SIZE_HIGH_NUM_TC 0x8
#define I40E_DCB_4_PORT_THRESHOLD_LOW_NUM_TC 0x9
#define I40E_DCB_4_PORT_FIFO_SIZE_LOW_NUM_TC 0x8
#define I40E_DCB_4_PORT_THRESHOLD_HIGH_NUM_TC 0x6
#define I40E_DCB_4_PORT_FIFO_SIZE_HIGH_NUM_TC 0x4
#define I40E_DCB_WATERMARK_START_FACTOR 0x2
/* delay values for with 10G BaseT in Bit Times */
#define I40E_INTERFACE_DELAY_10G_COPPER \
(I40E_INTERFACE_DELAY_10G_MAC + (2 * I40E_INTERFACE_DELAY_XAUI) \
+ I40E_INTERFACE_DELAY_10G_BASET)
#define I40E_DV_TC(mfs_max, mfs_tc) \
((2 * I40E_MAX_FRAME_TC(mfs_max, mfs_tc)) \
+ I40E_PFC_FRAME_DELAY \
+ (2 * I40E_CABLE_DELAY) \
+ (2 * I40E_INTERFACE_DELAY_10G_COPPER) \
+ I40E_HIGHER_LAYER_DELAY_10G)
static inline u32 I40E_STD_DV_TC(u32 mfs_max, u32 mfs_tc)
{
return I40E_DV_TC(mfs_max, mfs_tc) + I40E_B2BT(mfs_max);
}
/* APIs for SW DCBX */
void i40e_dcb_hw_rx_fifo_config(struct i40e_hw *hw,
enum i40e_dcb_arbiter_mode ets_mode,
enum i40e_dcb_arbiter_mode non_ets_mode,
u32 max_exponent, u8 lltc_map);
void i40e_dcb_hw_rx_cmd_monitor_config(struct i40e_hw *hw,
u8 num_tc, u8 num_ports);
void i40e_dcb_hw_pfc_config(struct i40e_hw *hw,
u8 pfc_en, u8 *prio_tc);
void i40e_dcb_hw_set_num_tc(struct i40e_hw *hw, u8 num_tc);
u8 i40e_dcb_hw_get_num_tc(struct i40e_hw *hw);
void i40e_dcb_hw_rx_ets_bw_config(struct i40e_hw *hw, u8 *bw_share,
u8 *mode, u8 *prio_type);
void i40e_dcb_hw_rx_up2tc_config(struct i40e_hw *hw, u8 *prio_tc);
void i40e_dcb_hw_calculate_pool_sizes(struct i40e_hw *hw,
u8 num_ports, bool eee_enabled,
u8 pfc_en, u32 *mfs_tc,
struct i40e_rx_pb_config *pb_cfg);
void i40e_dcb_hw_rx_pb_config(struct i40e_hw *hw,
struct i40e_rx_pb_config *old_pb_cfg,
struct i40e_rx_pb_config *new_pb_cfg);
i40e_status i40e_get_dcbx_status(struct i40e_hw *hw,
u16 *status);
u16 *status);
i40e_status i40e_lldp_to_dcb_config(u8 *lldpmib,
struct i40e_dcbx_config *dcbcfg);
struct i40e_dcbx_config *dcbcfg);
i40e_status i40e_aq_get_dcb_config(struct i40e_hw *hw, u8 mib_type,
u8 bridgetype,
struct i40e_dcbx_config *dcbcfg);
u8 bridgetype,
struct i40e_dcbx_config *dcbcfg);
i40e_status i40e_get_dcb_config(struct i40e_hw *hw);
i40e_status i40e_init_dcb(struct i40e_hw *hw, bool enable_mib_change);
i40e_status i40e_init_dcb(struct i40e_hw *hw,
bool enable_mib_change);
enum i40e_status_code
i40e_get_fw_lldp_status(struct i40e_hw *hw,
enum i40e_get_fw_lldp_status_resp *lldp_status);
i40e_status i40e_set_dcb_config(struct i40e_hw *hw);
i40e_status i40e_dcb_config_to_lldp(u8 *lldpmib, u16 *miblen,
struct i40e_dcbx_config *dcbcfg);
#endif /* _I40E_DCB_H_ */
/* SPDX-License-Identifier: GPL-2.0 */
/* Copyright(c) 2013 - 2018 Intel Corporation. */
/* Copyright(c) 2013 - 2021 Intel Corporation. */
#ifndef _I40E_PROTOTYPE_H_
#define _I40E_PROTOTYPE_H_
......@@ -200,6 +200,10 @@ i40e_status i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type,
u8 mib_type, void *buff, u16 buff_size,
u16 *local_len, u16 *remote_len,
struct i40e_asq_cmd_details *cmd_details);
enum i40e_status_code
i40e_aq_set_lldp_mib(struct i40e_hw *hw,
u8 mib_type, void *buff, u16 buff_size,
struct i40e_asq_cmd_details *cmd_details);
i40e_status i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw *hw,
bool enable_update,
struct i40e_asq_cmd_details *cmd_details);
......@@ -289,6 +293,9 @@ i40e_aq_rem_cloud_filters_bb(struct i40e_hw *hw, u16 seid,
u8 filter_count);
i40e_status i40e_read_lldp_cfg(struct i40e_hw *hw,
struct i40e_lldp_variables *lldp_cfg);
enum i40e_status_code
i40e_aq_suspend_port_tx(struct i40e_hw *hw, u16 seid,
struct i40e_asq_cmd_details *cmd_details);
/* i40e_common */
i40e_status i40e_init_shared_code(struct i40e_hw *hw);
i40e_status i40e_pf_reset(struct i40e_hw *hw);
......
/* SPDX-License-Identifier: GPL-2.0 */
/* Copyright(c) 2013 - 2018 Intel Corporation. */
/* Copyright(c) 2013 - 2021 Intel Corporation. */
#ifndef _I40E_TYPE_H_
#define _I40E_TYPE_H_
......@@ -517,6 +517,7 @@ struct i40e_dcbx_config {
#define I40E_DCBX_MODE_CEE 0x1
#define I40E_DCBX_MODE_IEEE 0x2
u8 app_mode;
#define I40E_DCBX_APPS_NON_WILLING 0x1
u32 numapps;
u32 tlv_status; /* CEE mode TLV status */
struct i40e_dcb_ets_config etscfg;
......
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