Commit 90e93648 authored by Linus Torvalds's avatar Linus Torvalds

Merge branch 'fixes' of master.kernel.org:/home/rmk/linux-2.6-arm

* 'fixes' of master.kernel.org:/home/rmk/linux-2.6-arm:
  ARM: pm: avoid writing the auxillary control register for ARMv7
  ARM: pm: some ARMv7 requires a dsb in resume to ensure correctness
  ARM: pm: arm920/926: fix number of registers saved
  ARM: pm: CPU specific code should not overwrite r1 (v:p offset)
  ARM: 7066/1: proc-v7: disable SCTLR.TE when disabling MMU
  ARM: 7065/1: kexec: ensure new kernel is entered in ARM state
  ARM: 7003/1: vexpress: Add clock definition for the SP805.
  ARM: 7051/1: cpuimx* boards: fix mach-types errors
  ARM: 7019/1: Footbridge: select CLKEVT_I8253 for ARCH_NETWINDER
  ARM: 7015/1: ARM errata: Possible cache data corruption with hit-under-miss enabled
  ARM: 7014/1: cache-l2x0: Fix L2 Cache size calculation.
  ARM: 6967/1: ep93xx: ts72xx: fix board model detection
  ARM: 6965/1: ep93xx: add model detection for ts-7300 and ts-7400 boards
  ARM: cache: detect VIPT aliasing I-cache on ARMv6
  ARM: twd: register clockevents device before enabling PPI
  ARM: realview: ensure visibility of writes during reset
  ARM: perf: make name of arm_pmu_type consistent
  ARM: perf: fix prototype of release_pmu
  ARM: fix perf build with uclibc toolchains
parents 3ae627b5 25904157
...@@ -1271,6 +1271,18 @@ config ARM_ERRATA_754327 ...@@ -1271,6 +1271,18 @@ config ARM_ERRATA_754327
This workaround defines cpu_relax() as smp_mb(), preventing correctly This workaround defines cpu_relax() as smp_mb(), preventing correctly
written polling loops from denying visibility of updates to memory. written polling loops from denying visibility of updates to memory.
config ARM_ERRATA_364296
bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
depends on CPU_V6 && !SMP
help
This options enables the workaround for the 364296 ARM1136
r0p2 erratum (possible cache data corruption with
hit-under-miss enabled). It sets the undocumented bit 31 in
the auxiliary control register and the FI bit in the control
register, thus disabling hit-under-miss without putting the
processor into full low interrupt latency mode. ARM11MPCore
is not affected.
endmenu endmenu
source "arch/arm/common/Kconfig" source "arch/arm/common/Kconfig"
......
...@@ -64,7 +64,7 @@ ...@@ -64,7 +64,7 @@
#define L2X0_AUX_CTRL_MASK 0xc0000fff #define L2X0_AUX_CTRL_MASK 0xc0000fff
#define L2X0_AUX_CTRL_ASSOCIATIVITY_SHIFT 16 #define L2X0_AUX_CTRL_ASSOCIATIVITY_SHIFT 16
#define L2X0_AUX_CTRL_WAY_SIZE_SHIFT 17 #define L2X0_AUX_CTRL_WAY_SIZE_SHIFT 17
#define L2X0_AUX_CTRL_WAY_SIZE_MASK (0x3 << 17) #define L2X0_AUX_CTRL_WAY_SIZE_MASK (0x7 << 17)
#define L2X0_AUX_CTRL_SHARE_OVERRIDE_SHIFT 22 #define L2X0_AUX_CTRL_SHARE_OVERRIDE_SHIFT 22
#define L2X0_AUX_CTRL_NS_LOCKDOWN_SHIFT 26 #define L2X0_AUX_CTRL_NS_LOCKDOWN_SHIFT 26
#define L2X0_AUX_CTRL_NS_INT_CTRL_SHIFT 27 #define L2X0_AUX_CTRL_NS_INT_CTRL_SHIFT 27
......
...@@ -41,7 +41,7 @@ struct arm_pmu_platdata { ...@@ -41,7 +41,7 @@ struct arm_pmu_platdata {
* encoded error on failure. * encoded error on failure.
*/ */
extern struct platform_device * extern struct platform_device *
reserve_pmu(enum arm_pmu_type device); reserve_pmu(enum arm_pmu_type type);
/** /**
* release_pmu() - Relinquish control of the performance counters * release_pmu() - Relinquish control of the performance counters
...@@ -62,26 +62,26 @@ release_pmu(enum arm_pmu_type type); ...@@ -62,26 +62,26 @@ release_pmu(enum arm_pmu_type type);
* the actual hardware initialisation. * the actual hardware initialisation.
*/ */
extern int extern int
init_pmu(enum arm_pmu_type device); init_pmu(enum arm_pmu_type type);
#else /* CONFIG_CPU_HAS_PMU */ #else /* CONFIG_CPU_HAS_PMU */
#include <linux/err.h> #include <linux/err.h>
static inline struct platform_device * static inline struct platform_device *
reserve_pmu(enum arm_pmu_type device) reserve_pmu(enum arm_pmu_type type)
{ {
return ERR_PTR(-ENODEV); return ERR_PTR(-ENODEV);
} }
static inline int static inline int
release_pmu(struct platform_device *pdev) release_pmu(enum arm_pmu_type type)
{ {
return -ENODEV; return -ENODEV;
} }
static inline int static inline int
init_pmu(enum arm_pmu_type device) init_pmu(enum arm_pmu_type type)
{ {
return -ENODEV; return -ENODEV;
} }
......
...@@ -31,7 +31,7 @@ static int __devinit pmu_register(struct platform_device *pdev, ...@@ -31,7 +31,7 @@ static int __devinit pmu_register(struct platform_device *pdev,
{ {
if (type < 0 || type >= ARM_NUM_PMU_DEVICES) { if (type < 0 || type >= ARM_NUM_PMU_DEVICES) {
pr_warning("received registration request for unknown " pr_warning("received registration request for unknown "
"device %d\n", type); "PMU device type %d\n", type);
return -EINVAL; return -EINVAL;
} }
...@@ -112,17 +112,17 @@ static int __init register_pmu_driver(void) ...@@ -112,17 +112,17 @@ static int __init register_pmu_driver(void)
device_initcall(register_pmu_driver); device_initcall(register_pmu_driver);
struct platform_device * struct platform_device *
reserve_pmu(enum arm_pmu_type device) reserve_pmu(enum arm_pmu_type type)
{ {
struct platform_device *pdev; struct platform_device *pdev;
if (test_and_set_bit_lock(device, &pmu_lock)) { if (test_and_set_bit_lock(type, &pmu_lock)) {
pdev = ERR_PTR(-EBUSY); pdev = ERR_PTR(-EBUSY);
} else if (pmu_devices[device] == NULL) { } else if (pmu_devices[type] == NULL) {
clear_bit_unlock(device, &pmu_lock); clear_bit_unlock(type, &pmu_lock);
pdev = ERR_PTR(-ENODEV); pdev = ERR_PTR(-ENODEV);
} else { } else {
pdev = pmu_devices[device]; pdev = pmu_devices[type];
} }
return pdev; return pdev;
...@@ -130,11 +130,11 @@ reserve_pmu(enum arm_pmu_type device) ...@@ -130,11 +130,11 @@ reserve_pmu(enum arm_pmu_type device)
EXPORT_SYMBOL_GPL(reserve_pmu); EXPORT_SYMBOL_GPL(reserve_pmu);
int int
release_pmu(enum arm_pmu_type device) release_pmu(enum arm_pmu_type type)
{ {
if (WARN_ON(!pmu_devices[device])) if (WARN_ON(!pmu_devices[type]))
return -EINVAL; return -EINVAL;
clear_bit_unlock(device, &pmu_lock); clear_bit_unlock(type, &pmu_lock);
return 0; return 0;
} }
EXPORT_SYMBOL_GPL(release_pmu); EXPORT_SYMBOL_GPL(release_pmu);
...@@ -182,17 +182,17 @@ init_cpu_pmu(void) ...@@ -182,17 +182,17 @@ init_cpu_pmu(void)
} }
int int
init_pmu(enum arm_pmu_type device) init_pmu(enum arm_pmu_type type)
{ {
int err = 0; int err = 0;
switch (device) { switch (type) {
case ARM_PMU_DEVICE_CPU: case ARM_PMU_DEVICE_CPU:
err = init_cpu_pmu(); err = init_cpu_pmu();
break; break;
default: default:
pr_warning("attempt to initialise unknown device %d\n", pr_warning("attempt to initialise PMU of unknown "
device); "type %d\n", type);
err = -EINVAL; err = -EINVAL;
} }
......
...@@ -57,7 +57,8 @@ relocate_new_kernel: ...@@ -57,7 +57,8 @@ relocate_new_kernel:
mov r0,#0 mov r0,#0
ldr r1,kexec_mach_type ldr r1,kexec_mach_type
ldr r2,kexec_boot_atags ldr r2,kexec_boot_atags
mov pc,lr ARM( mov pc, lr )
THUMB( bx lr )
.align .align
......
...@@ -280,18 +280,19 @@ static void __init cacheid_init(void) ...@@ -280,18 +280,19 @@ static void __init cacheid_init(void)
if (arch >= CPU_ARCH_ARMv6) { if (arch >= CPU_ARCH_ARMv6) {
if ((cachetype & (7 << 29)) == 4 << 29) { if ((cachetype & (7 << 29)) == 4 << 29) {
/* ARMv7 register format */ /* ARMv7 register format */
arch = CPU_ARCH_ARMv7;
cacheid = CACHEID_VIPT_NONALIASING; cacheid = CACHEID_VIPT_NONALIASING;
if ((cachetype & (3 << 14)) == 1 << 14) if ((cachetype & (3 << 14)) == 1 << 14)
cacheid |= CACHEID_ASID_TAGGED; cacheid |= CACHEID_ASID_TAGGED;
else if (cpu_has_aliasing_icache(CPU_ARCH_ARMv7))
cacheid |= CACHEID_VIPT_I_ALIASING;
} else if (cachetype & (1 << 23)) {
cacheid = CACHEID_VIPT_ALIASING;
} else { } else {
cacheid = CACHEID_VIPT_NONALIASING; arch = CPU_ARCH_ARMv6;
if (cpu_has_aliasing_icache(CPU_ARCH_ARMv6)) if (cachetype & (1 << 23))
cacheid |= CACHEID_VIPT_I_ALIASING; cacheid = CACHEID_VIPT_ALIASING;
else
cacheid = CACHEID_VIPT_NONALIASING;
} }
if (cpu_has_aliasing_icache(arch))
cacheid |= CACHEID_VIPT_I_ALIASING;
} else { } else {
cacheid = CACHEID_VIVT; cacheid = CACHEID_VIVT;
} }
......
...@@ -137,8 +137,8 @@ void __cpuinit twd_timer_setup(struct clock_event_device *clk) ...@@ -137,8 +137,8 @@ void __cpuinit twd_timer_setup(struct clock_event_device *clk)
clk->max_delta_ns = clockevent_delta2ns(0xffffffff, clk); clk->max_delta_ns = clockevent_delta2ns(0xffffffff, clk);
clk->min_delta_ns = clockevent_delta2ns(0xf, clk); clk->min_delta_ns = clockevent_delta2ns(0xf, clk);
clockevents_register_device(clk);
/* Make sure our local interrupt controller has this enabled */ /* Make sure our local interrupt controller has this enabled */
gic_enable_ppi(clk->irq); gic_enable_ppi(clk->irq);
clockevents_register_device(clk);
} }
...@@ -6,7 +6,7 @@ ...@@ -6,7 +6,7 @@
* TS72xx memory map: * TS72xx memory map:
* *
* virt phys size * virt phys size
* febff000 22000000 4K model number register * febff000 22000000 4K model number register (bits 0-2)
* febfe000 22400000 4K options register * febfe000 22400000 4K options register
* febfd000 22800000 4K options register #2 * febfd000 22800000 4K options register #2
* febf9000 10800000 4K TS-5620 RTC index register * febf9000 10800000 4K TS-5620 RTC index register
...@@ -20,6 +20,9 @@ ...@@ -20,6 +20,9 @@
#define TS72XX_MODEL_TS7200 0x00 #define TS72XX_MODEL_TS7200 0x00
#define TS72XX_MODEL_TS7250 0x01 #define TS72XX_MODEL_TS7250 0x01
#define TS72XX_MODEL_TS7260 0x02 #define TS72XX_MODEL_TS7260 0x02
#define TS72XX_MODEL_TS7300 0x03
#define TS72XX_MODEL_TS7400 0x04
#define TS72XX_MODEL_MASK 0x07
#define TS72XX_OPTIONS_PHYS_BASE 0x22400000 #define TS72XX_OPTIONS_PHYS_BASE 0x22400000
...@@ -51,19 +54,34 @@ ...@@ -51,19 +54,34 @@
#ifndef __ASSEMBLY__ #ifndef __ASSEMBLY__
static inline int ts72xx_model(void)
{
return __raw_readb(TS72XX_MODEL_VIRT_BASE) & TS72XX_MODEL_MASK;
}
static inline int board_is_ts7200(void) static inline int board_is_ts7200(void)
{ {
return __raw_readb(TS72XX_MODEL_VIRT_BASE) == TS72XX_MODEL_TS7200; return ts72xx_model() == TS72XX_MODEL_TS7200;
} }
static inline int board_is_ts7250(void) static inline int board_is_ts7250(void)
{ {
return __raw_readb(TS72XX_MODEL_VIRT_BASE) == TS72XX_MODEL_TS7250; return ts72xx_model() == TS72XX_MODEL_TS7250;
} }
static inline int board_is_ts7260(void) static inline int board_is_ts7260(void)
{ {
return __raw_readb(TS72XX_MODEL_VIRT_BASE) == TS72XX_MODEL_TS7260; return ts72xx_model() == TS72XX_MODEL_TS7260;
}
static inline int board_is_ts7300(void)
{
return ts72xx_model() == TS72XX_MODEL_TS7300;
}
static inline int board_is_ts7400(void)
{
return ts72xx_model() == TS72XX_MODEL_TS7400;
} }
static inline int is_max197_installed(void) static inline int is_max197_installed(void)
......
...@@ -62,6 +62,7 @@ config ARCH_EBSA285_HOST ...@@ -62,6 +62,7 @@ config ARCH_EBSA285_HOST
config ARCH_NETWINDER config ARCH_NETWINDER
bool "NetWinder" bool "NetWinder"
select CLKSRC_I8253 select CLKSRC_I8253
select CLKEVT_I8253
select FOOTBRIDGE_HOST select FOOTBRIDGE_HOST
select ISA select ISA
select ISA_DMA select ISA_DMA
......
...@@ -310,7 +310,7 @@ static struct sys_timer eukrea_cpuimx27_timer = { ...@@ -310,7 +310,7 @@ static struct sys_timer eukrea_cpuimx27_timer = {
.init = eukrea_cpuimx27_timer_init, .init = eukrea_cpuimx27_timer_init,
}; };
MACHINE_START(CPUIMX27, "EUKREA CPUIMX27") MACHINE_START(EUKREA_CPUIMX27, "EUKREA CPUIMX27")
.boot_params = MX27_PHYS_OFFSET + 0x100, .boot_params = MX27_PHYS_OFFSET + 0x100,
.map_io = mx27_map_io, .map_io = mx27_map_io,
.init_early = imx27_init_early, .init_early = imx27_init_early,
......
...@@ -192,7 +192,7 @@ struct sys_timer eukrea_cpuimx35_timer = { ...@@ -192,7 +192,7 @@ struct sys_timer eukrea_cpuimx35_timer = {
.init = eukrea_cpuimx35_timer_init, .init = eukrea_cpuimx35_timer_init,
}; };
MACHINE_START(EUKREA_CPUIMX35, "Eukrea CPUIMX35") MACHINE_START(EUKREA_CPUIMX35SD, "Eukrea CPUIMX35")
/* Maintainer: Eukrea Electromatique */ /* Maintainer: Eukrea Electromatique */
.boot_params = MX3x_PHYS_OFFSET + 0x100, .boot_params = MX3x_PHYS_OFFSET + 0x100,
.map_io = mx35_map_io, .map_io = mx35_map_io,
......
...@@ -161,7 +161,7 @@ static struct sys_timer eukrea_cpuimx25_timer = { ...@@ -161,7 +161,7 @@ static struct sys_timer eukrea_cpuimx25_timer = {
.init = eukrea_cpuimx25_timer_init, .init = eukrea_cpuimx25_timer_init,
}; };
MACHINE_START(EUKREA_CPUIMX25, "Eukrea CPUIMX25") MACHINE_START(EUKREA_CPUIMX25SD, "Eukrea CPUIMX25")
/* Maintainer: Eukrea Electromatique */ /* Maintainer: Eukrea Electromatique */
.boot_params = MX25_PHYS_OFFSET + 0x100, .boot_params = MX25_PHYS_OFFSET + 0x100,
.map_io = mx25_map_io, .map_io = mx25_map_io,
......
...@@ -44,6 +44,7 @@ static inline void arch_reset(char mode, const char *cmd) ...@@ -44,6 +44,7 @@ static inline void arch_reset(char mode, const char *cmd)
*/ */
if (realview_reset) if (realview_reset)
realview_reset(mode); realview_reset(mode);
dsb();
} }
#endif #endif
...@@ -318,6 +318,10 @@ static struct clk v2m_sp804_clk = { ...@@ -318,6 +318,10 @@ static struct clk v2m_sp804_clk = {
.rate = 1000000, .rate = 1000000,
}; };
static struct clk v2m_ref_clk = {
.rate = 32768,
};
static struct clk dummy_apb_pclk; static struct clk dummy_apb_pclk;
static struct clk_lookup v2m_lookups[] = { static struct clk_lookup v2m_lookups[] = {
...@@ -348,6 +352,9 @@ static struct clk_lookup v2m_lookups[] = { ...@@ -348,6 +352,9 @@ static struct clk_lookup v2m_lookups[] = {
}, { /* CLCD */ }, { /* CLCD */
.dev_id = "mb:clcd", .dev_id = "mb:clcd",
.clk = &osc1_clk, .clk = &osc1_clk,
}, { /* SP805 WDT */
.dev_id = "mb:wdt",
.clk = &v2m_ref_clk,
}, { /* SP804 timers */ }, { /* SP804 timers */
.dev_id = "sp804", .dev_id = "sp804",
.con_id = "v2m-timer0", .con_id = "v2m-timer0",
......
...@@ -379,7 +379,7 @@ ENTRY(cpu_arm920_set_pte_ext) ...@@ -379,7 +379,7 @@ ENTRY(cpu_arm920_set_pte_ext)
/* Suspend/resume support: taken from arch/arm/plat-s3c24xx/sleep.S */ /* Suspend/resume support: taken from arch/arm/plat-s3c24xx/sleep.S */
.globl cpu_arm920_suspend_size .globl cpu_arm920_suspend_size
.equ cpu_arm920_suspend_size, 4 * 3 .equ cpu_arm920_suspend_size, 4 * 4
#ifdef CONFIG_PM_SLEEP #ifdef CONFIG_PM_SLEEP
ENTRY(cpu_arm920_do_suspend) ENTRY(cpu_arm920_do_suspend)
stmfd sp!, {r4 - r7, lr} stmfd sp!, {r4 - r7, lr}
......
...@@ -394,7 +394,7 @@ ENTRY(cpu_arm926_set_pte_ext) ...@@ -394,7 +394,7 @@ ENTRY(cpu_arm926_set_pte_ext)
/* Suspend/resume support: taken from arch/arm/plat-s3c24xx/sleep.S */ /* Suspend/resume support: taken from arch/arm/plat-s3c24xx/sleep.S */
.globl cpu_arm926_suspend_size .globl cpu_arm926_suspend_size
.equ cpu_arm926_suspend_size, 4 * 3 .equ cpu_arm926_suspend_size, 4 * 4
#ifdef CONFIG_PM_SLEEP #ifdef CONFIG_PM_SLEEP
ENTRY(cpu_arm926_do_suspend) ENTRY(cpu_arm926_do_suspend)
stmfd sp!, {r4 - r7, lr} stmfd sp!, {r4 - r7, lr}
......
...@@ -182,11 +182,11 @@ ENDPROC(cpu_sa1100_do_suspend) ...@@ -182,11 +182,11 @@ ENDPROC(cpu_sa1100_do_suspend)
ENTRY(cpu_sa1100_do_resume) ENTRY(cpu_sa1100_do_resume)
ldmia r0, {r4 - r7} @ load cp regs ldmia r0, {r4 - r7} @ load cp regs
mov r1, #0 mov ip, #0
mcr p15, 0, r1, c8, c7, 0 @ flush I+D TLBs mcr p15, 0, ip, c8, c7, 0 @ flush I+D TLBs
mcr p15, 0, r1, c7, c7, 0 @ flush I&D cache mcr p15, 0, ip, c7, c7, 0 @ flush I&D cache
mcr p15, 0, r1, c9, c0, 0 @ invalidate RB mcr p15, 0, ip, c9, c0, 0 @ invalidate RB
mcr p15, 0, r1, c9, c0, 5 @ allow user space to use RB mcr p15, 0, ip, c9, c0, 5 @ allow user space to use RB
mcr p15, 0, r4, c3, c0, 0 @ domain ID mcr p15, 0, r4, c3, c0, 0 @ domain ID
mcr p15, 0, r5, c2, c0, 0 @ translation table base addr mcr p15, 0, r5, c2, c0, 0 @ translation table base addr
......
...@@ -223,6 +223,22 @@ __v6_setup: ...@@ -223,6 +223,22 @@ __v6_setup:
mrc p15, 0, r0, c1, c0, 0 @ read control register mrc p15, 0, r0, c1, c0, 0 @ read control register
bic r0, r0, r5 @ clear bits them bic r0, r0, r5 @ clear bits them
orr r0, r0, r6 @ set them orr r0, r0, r6 @ set them
#ifdef CONFIG_ARM_ERRATA_364296
/*
* Workaround for the 364296 ARM1136 r0p2 erratum (possible cache data
* corruption with hit-under-miss enabled). The conditional code below
* (setting the undocumented bit 31 in the auxiliary control register
* and the FI bit in the control register) disables hit-under-miss
* without putting the processor into full low interrupt latency mode.
*/
ldr r6, =0x4107b362 @ id for ARM1136 r0p2
mrc p15, 0, r5, c0, c0, 0 @ get processor id
teq r5, r6 @ check for the faulty core
mrceq p15, 0, r5, c1, c0, 1 @ load aux control reg
orreq r5, r5, #(1 << 31) @ set the undocumented bit 31
mcreq p15, 0, r5, c1, c0, 1 @ write aux control reg
orreq r0, r0, #(1 << 21) @ low interrupt latency configuration
#endif
mov pc, lr @ return to head.S:__ret mov pc, lr @ return to head.S:__ret
/* /*
......
...@@ -66,6 +66,7 @@ ENDPROC(cpu_v7_proc_fin) ...@@ -66,6 +66,7 @@ ENDPROC(cpu_v7_proc_fin)
ENTRY(cpu_v7_reset) ENTRY(cpu_v7_reset)
mrc p15, 0, r1, c1, c0, 0 @ ctrl register mrc p15, 0, r1, c1, c0, 0 @ ctrl register
bic r1, r1, #0x1 @ ...............m bic r1, r1, #0x1 @ ...............m
THUMB( bic r1, r1, #1 << 30 ) @ SCTLR.TE (Thumb exceptions)
mcr p15, 0, r1, c1, c0, 0 @ disable MMU mcr p15, 0, r1, c1, c0, 0 @ disable MMU
isb isb
mov pc, r0 mov pc, r0
...@@ -247,13 +248,16 @@ ENTRY(cpu_v7_do_resume) ...@@ -247,13 +248,16 @@ ENTRY(cpu_v7_do_resume)
mcr p15, 0, r7, c2, c0, 0 @ TTB 0 mcr p15, 0, r7, c2, c0, 0 @ TTB 0
mcr p15, 0, r8, c2, c0, 1 @ TTB 1 mcr p15, 0, r8, c2, c0, 1 @ TTB 1
mcr p15, 0, ip, c2, c0, 2 @ TTB control register mcr p15, 0, ip, c2, c0, 2 @ TTB control register
mcr p15, 0, r10, c1, c0, 1 @ Auxiliary control register mrc p15, 0, r4, c1, c0, 1 @ Read Auxiliary control register
teq r4, r10 @ Is it already set?
mcrne p15, 0, r10, c1, c0, 1 @ No, so write it
mcr p15, 0, r11, c1, c0, 2 @ Co-processor access control mcr p15, 0, r11, c1, c0, 2 @ Co-processor access control
ldr r4, =PRRR @ PRRR ldr r4, =PRRR @ PRRR
ldr r5, =NMRR @ NMRR ldr r5, =NMRR @ NMRR
mcr p15, 0, r4, c10, c2, 0 @ write PRRR mcr p15, 0, r4, c10, c2, 0 @ write PRRR
mcr p15, 0, r5, c10, c2, 1 @ write NMRR mcr p15, 0, r5, c10, c2, 1 @ write NMRR
isb isb
dsb
mov r0, r9 @ control register mov r0, r9 @ control register
mov r2, r7, lsr #14 @ get TTB0 base mov r2, r7, lsr #14 @ get TTB0 base
mov r2, r2, lsl #14 mov r2, r2, lsl #14
......
...@@ -406,7 +406,7 @@ ENTRY(cpu_xsc3_set_pte_ext) ...@@ -406,7 +406,7 @@ ENTRY(cpu_xsc3_set_pte_ext)
.align .align
.globl cpu_xsc3_suspend_size .globl cpu_xsc3_suspend_size
.equ cpu_xsc3_suspend_size, 4 * 8 .equ cpu_xsc3_suspend_size, 4 * 7
#ifdef CONFIG_PM_SLEEP #ifdef CONFIG_PM_SLEEP
ENTRY(cpu_xsc3_do_suspend) ENTRY(cpu_xsc3_do_suspend)
stmfd sp!, {r4 - r10, lr} stmfd sp!, {r4 - r10, lr}
...@@ -418,12 +418,12 @@ ENTRY(cpu_xsc3_do_suspend) ...@@ -418,12 +418,12 @@ ENTRY(cpu_xsc3_do_suspend)
mrc p15, 0, r9, c1, c0, 1 @ auxiliary control reg mrc p15, 0, r9, c1, c0, 1 @ auxiliary control reg
mrc p15, 0, r10, c1, c0, 0 @ control reg mrc p15, 0, r10, c1, c0, 0 @ control reg
bic r4, r4, #2 @ clear frequency change bit bic r4, r4, #2 @ clear frequency change bit
stmia r0, {r1, r4 - r10} @ store v:p offset + cp regs stmia r0, {r4 - r10} @ store cp regs
ldmia sp!, {r4 - r10, pc} ldmia sp!, {r4 - r10, pc}
ENDPROC(cpu_xsc3_do_suspend) ENDPROC(cpu_xsc3_do_suspend)
ENTRY(cpu_xsc3_do_resume) ENTRY(cpu_xsc3_do_resume)
ldmia r0, {r1, r4 - r10} @ load v:p offset + cp regs ldmia r0, {r4 - r10} @ load cp regs
mov ip, #0 mov ip, #0
mcr p15, 0, ip, c7, c7, 0 @ invalidate I & D caches, BTB mcr p15, 0, ip, c7, c7, 0 @ invalidate I & D caches, BTB
mcr p15, 0, ip, c7, c10, 4 @ drain write (&fill) buffer mcr p15, 0, ip, c7, c10, 4 @ drain write (&fill) buffer
......
...@@ -351,7 +351,7 @@ centro MACH_CENTRO CENTRO 1944 ...@@ -351,7 +351,7 @@ centro MACH_CENTRO CENTRO 1944
nokia_rx51 MACH_NOKIA_RX51 NOKIA_RX51 1955 nokia_rx51 MACH_NOKIA_RX51 NOKIA_RX51 1955
omap_zoom2 MACH_OMAP_ZOOM2 OMAP_ZOOM2 1967 omap_zoom2 MACH_OMAP_ZOOM2 OMAP_ZOOM2 1967
cpuat9260 MACH_CPUAT9260 CPUAT9260 1973 cpuat9260 MACH_CPUAT9260 CPUAT9260 1973
eukrea_cpuimx27 MACH_CPUIMX27 CPUIMX27 1975 eukrea_cpuimx27 MACH_EUKREA_CPUIMX27 EUKREA_CPUIMX27 1975
acs5k MACH_ACS5K ACS5K 1982 acs5k MACH_ACS5K ACS5K 1982
snapper_9260 MACH_SNAPPER_9260 SNAPPER_9260 1987 snapper_9260 MACH_SNAPPER_9260 SNAPPER_9260 1987
dsm320 MACH_DSM320 DSM320 1988 dsm320 MACH_DSM320 DSM320 1988
...@@ -476,8 +476,8 @@ cns3420vb MACH_CNS3420VB CNS3420VB 2776 ...@@ -476,8 +476,8 @@ cns3420vb MACH_CNS3420VB CNS3420VB 2776
omap4_panda MACH_OMAP4_PANDA OMAP4_PANDA 2791 omap4_panda MACH_OMAP4_PANDA OMAP4_PANDA 2791
ti8168evm MACH_TI8168EVM TI8168EVM 2800 ti8168evm MACH_TI8168EVM TI8168EVM 2800
teton_bga MACH_TETON_BGA TETON_BGA 2816 teton_bga MACH_TETON_BGA TETON_BGA 2816
eukrea_cpuimx25sd MACH_EUKREA_CPUIMX25 EUKREA_CPUIMX25 2820 eukrea_cpuimx25sd MACH_EUKREA_CPUIMX25SD EUKREA_CPUIMX25SD 2820
eukrea_cpuimx35sd MACH_EUKREA_CPUIMX35 EUKREA_CPUIMX35 2821 eukrea_cpuimx35sd MACH_EUKREA_CPUIMX35SD EUKREA_CPUIMX35SD 2821
eukrea_cpuimx51sd MACH_EUKREA_CPUIMX51SD EUKREA_CPUIMX51SD 2822 eukrea_cpuimx51sd MACH_EUKREA_CPUIMX51SD EUKREA_CPUIMX51SD 2822
eukrea_cpuimx51 MACH_EUKREA_CPUIMX51 EUKREA_CPUIMX51 2823 eukrea_cpuimx51 MACH_EUKREA_CPUIMX51 EUKREA_CPUIMX51 2823
smdkc210 MACH_SMDKC210 SMDKC210 2838 smdkc210 MACH_SMDKC210 SMDKC210 2838
......
...@@ -8,7 +8,10 @@ ...@@ -8,7 +8,10 @@
* published by the Free Software Foundation. * published by the Free Software Foundation.
*/ */
#include <stdlib.h>
#ifndef __UCLIBC__
#include <libio.h> #include <libio.h>
#endif
#include <dwarf-regs.h> #include <dwarf-regs.h>
struct pt_regs_dwarfnum { struct pt_regs_dwarfnum {
......
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