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Commit 918c8223 authored by Arnd Bergmann's avatar Arnd Bergmann
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Merge tag 'renesas-arm64-dt2-for-v4.15' of... 

Merge tag 'renesas-arm64-dt2-for-v4.15' of https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/dt

Pull "Second Round of Renesas ARM64 Based SoC DT Updates for v4.15" from Simon Horman:

* r8a7795 (H3) and r8a7796 (M3-W) SoCs
  - Use R-Car Gen 3 fallback compat string for GPIO

    Simon Horman says "Use newly added R-Car GPIO Gen 1, 2 and 3 fallback
    compat strings in peace of now deprecated non-generation specific R-Car
    GPIO fallback compat string in the DT of Renesas ARM and arm64 based
    SoCs.

* r8a7795 (H3) and r8a7796 (M3-W) Salvator boards
  - Add dr_mode property for USB2.0 channel 0

    Shimoda-san says "Since Salvator-X[S] have a USB2.0 dual-role channel
    (CN9), this patch
    adds dr_mode property for USB2.0 channel 0 (EHCI/OHCI and HS-USB)
    as "otg".

    Using dual-role channel (or not) is related to the type of USB receptor
    on board specification. So, I added the property into the
    salvator-common.dtsi."

  - Add pfc node for USB3.0 channel 0

    Shimoda-san says "Since a R-Car Gen3 bootloader enables the PFC of
    USB3.0 channel 0, the USB3.0 host controller works without this setting
    on the kernel.  But, this setting should have salvator-common.dtsi. So,
    this patch adds the pfc node for USB3.0 channel 0."

* r8a7795 (H3) and r8a7796 (M3-W) Salvator and ULCB boards
  - Correct audio_clkout

    Morimoto-san says ""audio_clkout" is dummy clock of <&rcar_sound 0> to
    avoid clock loop which invites probe conflct. Thus <&rcar_sound 0> and
    "audio_clkout" should be same value."

* r8a7795 (H3) and r8a7796 (M3-W) Salvator and ULCB, and
  r8a77995 (D3) Draak boards
  - Drop "avb_phy_int" from avb_pins

    Shimoda-san says "Since the Ethernet AVB driver doesn't support
    AVB_PHY_INT handling and it will be handled by a phy driver as a gpio
    pin, this patch removes the "avb_phy_int" from the avb_pins node."

* r8a77995 (D3) Draak board
  - Enable PWM channels

    Shimoda-san says "Each channel connects to LTC2644 for brightness
    control."

* r8a77970 (V3M) Eagle and ULCB Kingfisher boards
  - Add initial device tree support

* tag 'renesas-arm64-dt2-for-v4.15' of https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: (31 commits)
  arm64: dts: renesas: salvator-common: add dr_mode property for USB2.0 channel 0
  arm64: dts: r8a7796: Use R-Car GPIO Gen3 fallback compat string
  arm64: dts: r8a7795: Use R-Car GPIO Gen3 fallback compat string
  arm64: renesas: ulcb: fixup audio_clkout
  arm64: renesas: salvator-common: fixup audio_clkout
  arm64: dts: renesas: eagle: add EtherAVB support
  arm64: dts: r8a77995: Add INTC-EX device node
  arm64: dts: r8a77970: Add INTC-EX device node
  arm64: dts: r8a7796: Add INTC-EX device node
  arm64: dts: ulcb-kf: hog USB3 hub control gpios
  arm64: dts: ulcb-kf: enable PCA9548 on I2C4
  arm64: dts: ulcb-kf: enable PCA9548 on I2C2
  arm64: dts: ulcb-kf: enable TCA9539 on I2C4
  arm64: dts: ulcb-kf: enable TCA9539 on I2C2
  arm64: dts: ulcb-kf: enable USB3.0 Host
  arm64: dts: ulcb-kf: enable PCIE0/1
  arm64: dts: ulcb-kf: enable USB2.0 Host channel 0
  arm64: dts: ulcb-kf: enable HSUSB
  arm64: dts: ulcb-kf: enable CAN0/1
  arm64: dts: ulcb-kf: enable SCIF1
  ...
parents 11c3889c e9ce3538
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arch/arm64/boot/dts/renesas/Makefile
View file @ 918c8223
dtb-$(CONFIG_ARCH_R8A7795) += r8a7795-salvator-x.dtb r8a7795-h3ulcb.dtb
dtb-$(CONFIG_ARCH_R8A7795) += r8a7795-h3ulcb-kf.dtb
dtb-$(CONFIG_ARCH_R8A7795) += r8a7795-salvator-xs.dtb
dtb-$(CONFIG_ARCH_R8A7795) += r8a7795-es1-salvator-x.dtb r8a7795-es1-h3ulcb.dtb
dtb-$(CONFIG_ARCH_R8A7795) += r8a7795-es1-h3ulcb-kf.dtb
dtb-$(CONFIG_ARCH_R8A7796) += r8a7796-salvator-x.dtb r8a7796-m3ulcb.dtb
dtb-$(CONFIG_ARCH_R8A7796) += r8a7796-m3ulcb-kf.dtb
dtb-$(CONFIG_ARCH_R8A77970) += r8a77970-eagle.dtb
dtb-$(CONFIG_ARCH_R8A77995) += r8a77995-draak.dtb
always := $(dtb-y)
......
arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb-kf.dts 0 → 100644
View file @ 918c8223
/*
* Device Tree Source for the H3ULCB Kingfisher board
*
* Copyright (C) 2017 Renesas Electronics Corp.
* Copyright (C) 2017 Cogent Embedded, Inc.
*
* This file is licensed under the terms of the GNU General Public License
* version 2. This program is licensed "as is" without any warranty of any
* kind, whether express or implied.
*/
#include "r8a7795-es1-h3ulcb.dts"
#include "ulcb-kf.dtsi"
/ {
model = "Renesas H3ULCB Kingfisher board based on r8a7795 ES1.x";
compatible = "shimafuji,kingfisher", "renesas,h3ulcb",
"renesas,r8a7795";
};
arch/arm64/boot/dts/renesas/r8a7795-h3ulcb-kf.dts 0 → 100644
View file @ 918c8223
/*
* Device Tree Source for the H3ULCB Kingfisher board
*
* Copyright (C) 2017 Renesas Electronics Corp.
* Copyright (C) 2017 Cogent Embedded, Inc.
*
* This file is licensed under the terms of the GNU General Public License
* version 2. This program is licensed "as is" without any warranty of any
* kind, whether express or implied.
*/
#include "r8a7795-h3ulcb.dts"
#include "ulcb-kf.dtsi"
/ {
model = "Renesas H3ULCB Kingfisher board based on r8a7795 ES2.0+";
compatible = "shimafuji,kingfisher", "renesas,h3ulcb",
"renesas,r8a7795";
};
arch/arm64/boot/dts/renesas/r8a7795.dtsi
View file @ 918c8223
......@@ -220,7 +220,7 @@ wdt0: watchdog@e6020000 {
gpio0: gpio@e6050000 {
compatible = "renesas,gpio-r8a7795",
"renesas,gpio-rcar";
"renesas,rcar-gen3-gpio";
reg = <0 0xe6050000 0 0x50>;
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
......@@ -235,7 +235,7 @@ gpio0: gpio@e6050000 {
gpio1: gpio@e6051000 {
compatible = "renesas,gpio-r8a7795",
"renesas,gpio-rcar";
"renesas,rcar-gen3-gpio";
reg = <0 0xe6051000 0 0x50>;
interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
......@@ -250,7 +250,7 @@ gpio1: gpio@e6051000 {
gpio2: gpio@e6052000 {
compatible = "renesas,gpio-r8a7795",
"renesas,gpio-rcar";
"renesas,rcar-gen3-gpio";
reg = <0 0xe6052000 0 0x50>;
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
......@@ -265,7 +265,7 @@ gpio2: gpio@e6052000 {
gpio3: gpio@e6053000 {
compatible = "renesas,gpio-r8a7795",
"renesas,gpio-rcar";
"renesas,rcar-gen3-gpio";
reg = <0 0xe6053000 0 0x50>;
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
......@@ -280,7 +280,7 @@ gpio3: gpio@e6053000 {
gpio4: gpio@e6054000 {
compatible = "renesas,gpio-r8a7795",
"renesas,gpio-rcar";
"renesas,rcar-gen3-gpio";
reg = <0 0xe6054000 0 0x50>;
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
......@@ -295,7 +295,7 @@ gpio4: gpio@e6054000 {
gpio5: gpio@e6055000 {
compatible = "renesas,gpio-r8a7795",
"renesas,gpio-rcar";
"renesas,rcar-gen3-gpio";
reg = <0 0xe6055000 0 0x50>;
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
......@@ -310,7 +310,7 @@ gpio5: gpio@e6055000 {
gpio6: gpio@e6055400 {
compatible = "renesas,gpio-r8a7795",
"renesas,gpio-rcar";
"renesas,rcar-gen3-gpio";
reg = <0 0xe6055400 0 0x50>;
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
......@@ -325,7 +325,7 @@ gpio6: gpio@e6055400 {
gpio7: gpio@e6055800 {
compatible = "renesas,gpio-r8a7795",
"renesas,gpio-rcar";
"renesas,rcar-gen3-gpio";
reg = <0 0xe6055800 0 0x50>;
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
......
arch/arm64/boot/dts/renesas/r8a7796-m3ulcb-kf.dts 0 → 100644
View file @ 918c8223
/*
* Device Tree Source for the M3ULCB Kingfisher board
*
* Copyright (C) 2017 Renesas Electronics Corp.
* Copyright (C) 2017 Cogent Embedded, Inc.
*
* This file is licensed under the terms of the GNU General Public License
* version 2. This program is licensed "as is" without any warranty of any
* kind, whether express or implied.
*/
#include "r8a7796-m3ulcb.dts"
#include "ulcb-kf.dtsi"
/ {
model = "Renesas M3ULCB Kingfisher board based on r8a7796";
compatible = "shimafuji,kingfisher", "renesas,m3ulcb",
"renesas,r8a7796";
};
arch/arm64/boot/dts/renesas/r8a7796.dtsi
View file @ 918c8223
......@@ -214,7 +214,7 @@ wdt0: watchdog@e6020000 {
gpio0: gpio@e6050000 {
compatible = "renesas,gpio-r8a7796",
"renesas,gpio-rcar";
"renesas,rcar-gen3-gpio";
reg = <0 0xe6050000 0 0x50>;
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
......@@ -229,7 +229,7 @@ gpio0: gpio@e6050000 {
gpio1: gpio@e6051000 {
compatible = "renesas,gpio-r8a7796",
"renesas,gpio-rcar";
"renesas,rcar-gen3-gpio";
reg = <0 0xe6051000 0 0x50>;
interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
......@@ -244,7 +244,7 @@ gpio1: gpio@e6051000 {
gpio2: gpio@e6052000 {
compatible = "renesas,gpio-r8a7796",
"renesas,gpio-rcar";
"renesas,rcar-gen3-gpio";
reg = <0 0xe6052000 0 0x50>;
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
......@@ -259,7 +259,7 @@ gpio2: gpio@e6052000 {
gpio3: gpio@e6053000 {
compatible = "renesas,gpio-r8a7796",
"renesas,gpio-rcar";
"renesas,rcar-gen3-gpio";
reg = <0 0xe6053000 0 0x50>;
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
......@@ -274,7 +274,7 @@ gpio3: gpio@e6053000 {
gpio4: gpio@e6054000 {
compatible = "renesas,gpio-r8a7796",
"renesas,gpio-rcar";
"renesas,rcar-gen3-gpio";
reg = <0 0xe6054000 0 0x50>;
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
......@@ -289,7 +289,7 @@ gpio4: gpio@e6054000 {
gpio5: gpio@e6055000 {
compatible = "renesas,gpio-r8a7796",
"renesas,gpio-rcar";
"renesas,rcar-gen3-gpio";
reg = <0 0xe6055000 0 0x50>;
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
......@@ -304,7 +304,7 @@ gpio5: gpio@e6055000 {
gpio6: gpio@e6055400 {
compatible = "renesas,gpio-r8a7796",
"renesas,gpio-rcar";
"renesas,rcar-gen3-gpio";
reg = <0 0xe6055400 0 0x50>;
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
......@@ -319,7 +319,7 @@ gpio6: gpio@e6055400 {
gpio7: gpio@e6055800 {
compatible = "renesas,gpio-r8a7796",
"renesas,gpio-rcar";
"renesas,rcar-gen3-gpio";
reg = <0 0xe6055800 0 0x50>;
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
......@@ -383,6 +383,22 @@ sysc: system-controller@e6180000 {
#power-domain-cells = <1>;
};
intc_ex: interrupt-controller@e61c0000 {
compatible = "renesas,intc-ex-r8a7796", "renesas,irqc";
#interrupt-cells = <2>;
interrupt-controller;
reg = <0 0xe61c0000 0 0x200>;
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 407>;
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
resets = <&cpg 407>;
};
i2c_dvfs: i2c@e60b0000 {
#address-cells = <1>;
#size-cells = <0>;
......
arch/arm64/boot/dts/renesas/r8a77970-eagle.dts 0 → 100644
View file @ 918c8223
/*
* Device Tree Source for the Eagle board
*
* Copyright (C) 2016-2017 Renesas Electronics Corp.
* Copyright (C) 2017 Cogent Embedded, Inc.
*
* This file is licensed under the terms of the GNU General Public License
* version 2. This program is licensed "as is" without any warranty of any
* kind, whether express or implied.
*/
/dts-v1/;
#include "r8a77970.dtsi"
/ {
model = "Renesas Eagle board based on r8a77970";
compatible = "renesas,eagle", "renesas,r8a77970";
aliases {
serial0 = &scif0;
ethernet0 = &avb;
};
chosen {
bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
stdout-path = "serial0:115200n8";
};
memory@48000000 {
device_type = "memory";
/* first 128MB is reserved for secure area. */
reg = <0x0 0x48000000 0x0 0x38000000>;
};
};
&extal_clk {
clock-frequency = <16666666>;
};
&extalr_clk {
clock-frequency = <32768>;
};
&scif0 {
status = "okay";
};
&avb {
renesas,no-ether-link;
phy-handle = <&phy0>;
status = "okay";
phy0: ethernet-phy@0 {
rxc-skew-ps = <1500>;
reg = <0>;
};
};
arch/arm64/boot/dts/renesas/r8a77970.dtsi
View file @ 918c8223
......@@ -124,6 +124,22 @@ sysc: system-controller@e6180000 {
#power-domain-cells = <1>;
};
intc_ex: interrupt-controller@e61c0000 {
compatible = "renesas,intc-ex-r8a77970", "renesas,irqc";
#interrupt-cells = <2>;
interrupt-controller;
reg = <0 0xe61c0000 0 0x200>;
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 407>;
power-domains = <&sysc 32>;
resets = <&cpg 407>;
};
prr: chipid@fff00044 {
compatible = "renesas,prr";
reg = <0 0xfff00044 0 4>;
......
arch/arm64/boot/dts/renesas/r8a77995-draak.dts
View file @ 918c8223
......@@ -41,12 +41,21 @@ &extal_clk {
&pfc {
avb0_pins: avb {
mux {
groups = "avb0_link", "avb0_phy_int", "avb0_mdc",
"avb0_mii";
groups = "avb0_link", "avb0_mdc", "avb0_mii";
function = "avb0";
};
};
pwm0_pins: pwm0 {
groups = "pwm0_c";
function = "pwm0";
};
pwm1_pins: pwm1 {
groups = "pwm1_c";
function = "pwm1";
};
scif2_pins: scif2 {
groups = "scif2_data";
function = "scif2";
......@@ -95,6 +104,20 @@ &usb2_phy0 {
status = "okay";
};
&pwm0 {
pinctrl-0 = <&pwm0_pins>;
pinctrl-names = "default";
status = "okay";
};
&pwm1 {
pinctrl-0 = <&pwm1_pins>;
pinctrl-names = "default";
status = "okay";
};
&rwdt {
timeout-sec = <60>;
status = "okay";
......
arch/arm64/boot/dts/renesas/r8a77995.dtsi
View file @ 918c8223
......@@ -139,6 +139,22 @@ sysc: system-controller@e6180000 {
#power-domain-cells = <1>;
};
intc_ex: interrupt-controller@e61c0000 {
compatible = "renesas,intc-ex-r8a77995", "renesas,irqc";
#interrupt-cells = <2>;
interrupt-controller;
reg = <0 0xe61c0000 0 0x200>;
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 407>;
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
resets = <&cpg 407>;
};
gpio0: gpio@e6050000 {
compatible = "renesas,gpio-r8a77995",
"renesas,rcar-gen3-gpio",
......@@ -310,6 +326,46 @@ scif2: serial@e6e88000 {
status = "disabled";
};
pwm0: pwm@e6e30000 {
compatible = "renesas,pwm-r8a77995", "renesas,pwm-rcar";
reg = <0 0xe6e30000 0 0x8>;
#pwm-cells = <2>;
clocks = <&cpg CPG_MOD 523>;
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
resets = <&cpg 523>;
status = "disabled";
};
pwm1: pwm@e6e31000 {
compatible = "renesas,pwm-r8a77995", "renesas,pwm-rcar";
reg = <0 0xe6e31000 0 0x8>;
#pwm-cells = <2>;
clocks = <&cpg CPG_MOD 523>;
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
resets = <&cpg 523>;
status = "disabled";
};
pwm2: pwm@e6e32000 {
compatible = "renesas,pwm-r8a77995", "renesas,pwm-rcar";
reg = <0 0xe6e32000 0 0x8>;
#pwm-cells = <2>;
clocks = <&cpg CPG_MOD 523>;
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
resets = <&cpg 523>;
status = "disabled";
};
pwm3: pwm@e6e33000 {
compatible = "renesas,pwm-r8a77995", "renesas,pwm-rcar";
reg = <0 0xe6e33000 0 0x8>;
#pwm-cells = <2>;
clocks = <&cpg CPG_MOD 523>;
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
resets = <&cpg 523>;
status = "disabled";
};
ehci0: usb@ee080100 {
compatible = "generic-ehci";
reg = <0 0xee080100 0 0x100>;
......
arch/arm64/boot/dts/renesas/salvator-common.dtsi
View file @ 918c8223
......@@ -52,7 +52,7 @@ audio_clkout: audio-clkout {
*/
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <11289600>;
clock-frequency = <12288000>;
};
backlight: backlight {
......@@ -272,6 +272,7 @@ endpoint {
};
&ehci0 {
dr_mode = "otg";
status = "okay";
};
......@@ -284,6 +285,7 @@ &extalr_clk {
};
&hsusb {
dr_mode = "otg";
status = "okay";
};
......@@ -346,6 +348,7 @@ &i2c_dvfs {
};
&ohci0 {
dr_mode = "otg";
status = "okay";
};
......@@ -371,8 +374,7 @@ &pfc {
avb_pins: avb {
mux {
groups = "avb_link", "avb_phy_int", "avb_mdc",
"avb_mii";
groups = "avb_link", "avb_mdc", "avb_mii";
function = "avb";
};
......@@ -486,6 +488,11 @@ pwen {
bias-pull-down;
};
};
usb30_pins: usb30 {
groups = "usb30";
function = "usb30";
};
};
&pwm1 {
......@@ -621,5 +628,8 @@ &wdt0 {
};
&xhci0 {
pinctrl-0 = <&usb30_pins>;
pinctrl-names = "default";
status = "okay";
};
arch/arm64/boot/dts/renesas/ulcb-kf.dtsi 0 → 100644
View file @ 918c8223
/*
* Device Tree Source for the Kingfisher (ULCB extension) board
*
* Copyright (C) 2017 Renesas Electronics Corp.
* Copyright (C) 2017 Cogent Embedded, Inc.
*
* This file is licensed under the terms of the GNU General Public License
* version 2. This program is licensed "as is" without any warranty of any
* kind, whether express or implied.
*/
/ {
aliases {
serial1 = &hscif0;
serial2 = &scif1;
};
};
&can0 {
pinctrl-0 = <&can0_pins>;
pinctrl-names = "default";
status = "okay";
};
&can1 {
pinctrl-0 = <&can1_pins>;
pinctrl-names = "default";
status = "okay";
};
&ehci0 {
status = "okay";
};
&hscif0 {
pinctrl-0 = <&hscif0_pins>;
pinctrl-names = "default";
uart-has-rtscts;
status = "okay";
};
&hsusb {
status = "okay";
};
&i2c2 {
gpio_exp_74: gpio@74 {
compatible = "ti,tca9539";
reg = <0x74>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
interrupt-parent = <&gpio6>;
interrupts = <8 IRQ_TYPE_EDGE_FALLING>;
hub_pwen {
gpio-hog;
gpios = <6 GPIO_ACTIVE_HIGH>;
output-high;
line-name = "HUB pwen";
};
hub_rst {
gpio-hog;
gpios = <7 GPIO_ACTIVE_HIGH>;
output-high;
line-name = "HUB rst";
};
};
gpio_exp_75: gpio@75 {
compatible = "ti,tca9539";
reg = <0x75>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
interrupt-parent = <&gpio6>;
interrupts = <4 IRQ_TYPE_EDGE_FALLING>;
};
i2cswitch2: i2c-switch@71 {
compatible = "nxp,pca9548";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x71>;
reset-gpios = <&gpio5 3 GPIO_ACTIVE_LOW>;
};
};
&i2c4 {
gpio_exp_76: gpio@76 {
compatible = "ti,tca9539";
reg = <0x76>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
interrupt-parent = <&gpio7>;
interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
};
gpio_exp_77: gpio@77 {
compatible = "ti,tca9539";
reg = <0x77>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
interrupt-parent = <&gpio5>;
interrupts = <9 IRQ_TYPE_EDGE_FALLING>;
};
i2cswitch4: i2c-switch@71 {
compatible = "nxp,pca9548";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x71>;
reset-gpios= <&gpio3 15 GPIO_ACTIVE_LOW>;
};
};
&ohci0 {
status = "okay";
};
&pcie_bus_clk {
clock-frequency = <100000000>;
};
&pciec0 {
status = "okay";
};
&pciec1 {
status = "okay";
};
&pfc {
can0_pins: can0 {
groups = "can0_data_a";
function = "can0";
};
can1_pins: can1 {
groups = "can1_data";
function = "can1";
};
hscif0_pins: hscif0 {
groups = "hscif0_data", "hscif0_ctrl";
function = "hscif0";
};
scif1_pins: scif1 {
groups = "scif1_data_b", "scif1_ctrl";
function = "scif1";
};
};
&scif1 {
pinctrl-0 = <&scif1_pins>;
pinctrl-names = "default";
uart-has-rtscts;
status = "okay";
};
&xhci0 {
status = "okay";
};
arch/arm64/boot/dts/renesas/ulcb.dtsi
View file @ 918c8223
......@@ -31,7 +31,7 @@ audio_clkout: audio-clkout {
*/
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <11289600>;
clock-frequency = <12288000>;
};
hdmi0-out {
......@@ -254,8 +254,7 @@ &pfc {
avb_pins: avb {
mux {
groups = "avb_link", "avb_phy_int", "avb_mdc",
"avb_mii";
groups = "avb_link", "avb_mdc", "avb_mii";
function = "avb";
};
......
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